On 1/16/2026 11:34 AM, Ravi Bangoria wrote:
> Load latency filter threshold is encoded in config1[11:0]. Define a mask
> for it instead of hardcoded 0xFFF. Unlike "config" fields whose layout
> maps to PERF_{FETCH|OP}_CTL MSR, layout of "config1" is custom defined
> so a new set of macros are needed for "config1" fields.
>
> Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com>
> ---
> arch/x86/events/amd/ibs.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c
> index 27b764eee6c7..02e7bffe1208 100644
> --- a/arch/x86/events/amd/ibs.c
> +++ b/arch/x86/events/amd/ibs.c
> @@ -32,6 +32,9 @@ static u32 ibs_caps;
> /* attr.config2 */
> #define IBS_SW_FILTER_MASK 1
>
> +/* attr.config1 */
> +#define IBS_OP_CONFIG1_LDLAT_MASK (0xFFFULL << 0)
> +
> /*
> * IBS states:
> *
> @@ -274,7 +277,7 @@ static bool perf_ibs_ldlat_event(struct perf_ibs *perf_ibs,
> {
> return perf_ibs == &perf_ibs_op &&
> (ibs_caps & IBS_CAPS_OPLDLAT) &&
> - (event->attr.config1 & 0xFFF);
> + (event->attr.config1 & IBS_OP_CONFIG1_LDLAT_MASK);
> }
>
> static int perf_ibs_init(struct perf_event *event)
> @@ -349,7 +352,7 @@ static int perf_ibs_init(struct perf_event *event)
> }
>
> if (perf_ibs_ldlat_event(perf_ibs, event)) {
> - u64 ldlat = event->attr.config1 & 0xFFF;
> + u64 ldlat = event->attr.config1 & IBS_OP_CONFIG1_LDLAT_MASK;
>
> if (ldlat < 128 || ldlat > 2048)
> return -EINVAL;
> @@ -1302,7 +1305,7 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)
> * within [128, 2048] range.
> */
> if (!op_data3.ld_op || !op_data3.dc_miss ||
> - op_data3.dc_miss_lat <= (event->attr.config1 & 0xFFF)) {
> + op_data3.dc_miss_lat <= (event->attr.config1 & IBS_OP_CONFIG1_LDLAT_MASK)) {
> throttle = perf_event_account_interrupt(event);
> goto out;
> }
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>