Use BIT() and GENMASK() (and *_ULL() variants) to define the bitmasks in
svm.h.

Opportunistically switch the definitions of AVIC_ENABLE_{SHIFT/MASK}
and X2APIC_MODE_{SHIFT/MASK}, as well as SVM_EVTINJ_VALID and
SVM_EVTINJ_VALID_ERR, such that the bitmasks are defined in the correct
order.

No functional change intended.

Signed-off-by: Yosry Ahmed <yosry.ahmed@linux.dev>
---
 arch/x86/include/asm/svm.h | 78 +++++++++++++++++++-------------------
 1 file changed, 39 insertions(+), 39 deletions(-)

diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h
index 770c7aed5fa5..0bc26b2b3fd7 100644
--- a/arch/x86/include/asm/svm.h
+++ b/arch/x86/include/asm/svm.h
@@ -189,39 +189,39 @@ struct __attribute__ ((__packed__)) vmcb_control_area {
 #define V_TPR_MASK 0x0f
 
 #define V_IRQ_SHIFT 8
-#define V_IRQ_MASK (1 << V_IRQ_SHIFT)
+#define V_IRQ_MASK BIT(V_IRQ_SHIFT)
 
 #define V_GIF_SHIFT 9
-#define V_GIF_MASK (1 << V_GIF_SHIFT)
+#define V_GIF_MASK BIT(V_GIF_SHIFT)
 
 #define V_NMI_PENDING_SHIFT 11
-#define V_NMI_PENDING_MASK (1 << V_NMI_PENDING_SHIFT)
+#define V_NMI_PENDING_MASK BIT(V_NMI_PENDING_SHIFT)
 
 #define V_NMI_BLOCKING_SHIFT 12
-#define V_NMI_BLOCKING_MASK (1 << V_NMI_BLOCKING_SHIFT)
+#define V_NMI_BLOCKING_MASK BIT(V_NMI_BLOCKING_SHIFT)
 
 #define V_INTR_PRIO_SHIFT 16
-#define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
+#define V_INTR_PRIO_MASK GENMASK(V_INTR_PRIO_SHIFT + 3, V_INTR_PRIO_SHIFT)
 
 #define V_IGN_TPR_SHIFT 20
-#define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
+#define V_IGN_TPR_MASK BIT(V_IGN_TPR_SHIFT)
 
 #define V_IRQ_INJECTION_BITS_MASK (V_IRQ_MASK | V_INTR_PRIO_MASK | V_IGN_TPR_MASK)
 
 #define V_INTR_MASKING_SHIFT 24
-#define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
+#define V_INTR_MASKING_MASK BIT(V_INTR_MASKING_SHIFT)
 
 #define V_GIF_ENABLE_SHIFT 25
-#define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT)
+#define V_GIF_ENABLE_MASK BIT(V_GIF_ENABLE_SHIFT)
 
 #define V_NMI_ENABLE_SHIFT 26
-#define V_NMI_ENABLE_MASK (1 << V_NMI_ENABLE_SHIFT)
-
-#define AVIC_ENABLE_SHIFT 31
-#define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
+#define V_NMI_ENABLE_MASK BIT(V_NMI_ENABLE_SHIFT)
 
 #define X2APIC_MODE_SHIFT 30
-#define X2APIC_MODE_MASK (1 << X2APIC_MODE_SHIFT)
+#define X2APIC_MODE_MASK BIT(X2APIC_MODE_SHIFT)
+
+#define AVIC_ENABLE_SHIFT 31
+#define AVIC_ENABLE_MASK BIT(AVIC_ENABLE_SHIFT)
 
 #define SVM_INTERRUPT_SHADOW_MASK	BIT_ULL(0)
 #define SVM_GUEST_INTERRUPT_MASK	BIT_ULL(1)
@@ -232,10 +232,10 @@ struct __attribute__ ((__packed__)) vmcb_control_area {
 #define SVM_IOIO_ASIZE_SHIFT 7
 
 #define SVM_IOIO_TYPE_MASK 1
-#define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
-#define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
-#define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
-#define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
+#define SVM_IOIO_STR_MASK BIT(SVM_IOIO_STR_SHIFT)
+#define SVM_IOIO_REP_MASK BIT(SVM_IOIO_REP_SHIFT)
+#define SVM_IOIO_SIZE_MASK GENMASK(SVM_IOIO_SIZE_SHIFT + 2, SVM_IOIO_SIZE_SHIFT)
+#define SVM_IOIO_ASIZE_MASK GENMASK(SVM_IOIO_ASIZE_SHIFT + 2, SVM_IOIO_ASIZE_SHIFT)
 
 #define SVM_MISC_CTL_NP_ENABLE		BIT(0)
 #define SVM_MISC_CTL_SEV_ENABLE		BIT(1)
@@ -251,9 +251,9 @@ struct __attribute__ ((__packed__)) vmcb_control_area {
 
 
 /* AVIC */
-#define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK	(0xFFULL)
+#define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK	GENMASK_ULL(7, 0)
 #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT			31
-#define AVIC_LOGICAL_ID_ENTRY_VALID_MASK		(1 << 31)
+#define AVIC_LOGICAL_ID_ENTRY_VALID_MASK		BIT(AVIC_LOGICAL_ID_ENTRY_VALID_BIT)
 
 /*
  * GA_LOG_INTR is a synthetic flag that's never propagated to hardware-visible
@@ -264,15 +264,15 @@ struct __attribute__ ((__packed__)) vmcb_control_area {
 
 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK	GENMASK_ULL(11, 0)
 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK	GENMASK_ULL(51, 12)
-#define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK		(1ULL << 62)
-#define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK		(1ULL << 63)
-#define AVIC_PHYSICAL_ID_TABLE_SIZE_MASK		(0xFFULL)
+#define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK		BIT_ULL(62)
+#define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK		BIT_ULL(63)
+#define AVIC_PHYSICAL_ID_TABLE_SIZE_MASK		GENMASK_ULL(7, 0)
 
 #define AVIC_DOORBELL_PHYSICAL_ID_MASK			GENMASK_ULL(11, 0)
 
 #define AVIC_UNACCEL_ACCESS_WRITE_MASK		1
-#define AVIC_UNACCEL_ACCESS_OFFSET_MASK		0xFF0
-#define AVIC_UNACCEL_ACCESS_VECTOR_MASK		0xFFFFFFFF
+#define AVIC_UNACCEL_ACCESS_OFFSET_MASK		GENMASK(11, 4)
+#define AVIC_UNACCEL_ACCESS_VECTOR_MASK		GENMASK(31, 0)
 
 enum avic_ipi_failure_cause {
 	AVIC_IPI_FAILURE_INVALID_INT_TYPE,
@@ -611,30 +611,30 @@ static inline void __unused_size_checks(void)
 #define SVM_SELECTOR_G_SHIFT 11
 
 #define SVM_SELECTOR_TYPE_MASK (0xf)
-#define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
-#define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
-#define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
-#define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
-#define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
-#define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
-#define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
-
-#define SVM_SELECTOR_WRITE_MASK (1 << 1)
+#define SVM_SELECTOR_S_MASK BIT(SVM_SELECTOR_S_SHIFT)
+#define SVM_SELECTOR_DPL_MASK GENMASK(SVM_SELECTOR_DPL_SHIFT + 1, SVM_SELECTOR_DPL_SHIFT)
+#define SVM_SELECTOR_P_MASK BIT(SVM_SELECTOR_P_SHIFT)
+#define SVM_SELECTOR_AVL_MASK BIT(SVM_SELECTOR_AVL_SHIFT)
+#define SVM_SELECTOR_L_MASK BIT(SVM_SELECTOR_L_SHIFT)
+#define SVM_SELECTOR_DB_MASK BIT(SVM_SELECTOR_DB_SHIFT)
+#define SVM_SELECTOR_G_MASK BIT(SVM_SELECTOR_G_SHIFT)
+
+#define SVM_SELECTOR_WRITE_MASK BIT(1)
 #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
-#define SVM_SELECTOR_CODE_MASK (1 << 3)
+#define SVM_SELECTOR_CODE_MASK BIT(3)
 
-#define SVM_EVTINJ_VEC_MASK 0xff
+#define SVM_EVTINJ_VEC_MASK GENMASK(7, 0)
 
 #define SVM_EVTINJ_TYPE_SHIFT 8
-#define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
+#define SVM_EVTINJ_TYPE_MASK GENMASK(SVM_EVTINJ_TYPE_SHIFT + 2, SVM_EVTINJ_TYPE_SHIFT)
 
 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
 #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
 #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
 #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
 
-#define SVM_EVTINJ_VALID (1 << 31)
-#define SVM_EVTINJ_VALID_ERR (1 << 11)
+#define SVM_EVTINJ_VALID_ERR BIT(11)
+#define SVM_EVTINJ_VALID BIT(31)
 
 #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
 #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
@@ -651,7 +651,7 @@ static inline void __unused_size_checks(void)
 #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
 #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
 
-#define SVM_EXITINFO_REG_MASK 0x0F
+#define SVM_EXITINFO_REG_MASK GENMASK(3, 0)
 
 #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
 
-- 
2.52.0.457.g6b5491de43-goog

On Thu, Jan 15, 2026, Yosry Ahmed wrote:
> Use BIT() and GENMASK() (and *_ULL() variants) to define the bitmasks in
> svm.h.

Oh, hey, just what I was talking about.  But why is this buried as patch 22/26?
AFAICT, it's got nothing to do with the rest of the series.

> Opportunistically switch the definitions of AVIC_ENABLE_{SHIFT/MASK}
> and X2APIC_MODE_{SHIFT/MASK}, as well as SVM_EVTINJ_VALID and
> SVM_EVTINJ_VALID_ERR, such that the bitmasks are defined in the correct
> order.
> 
> No functional change intended.
> 
> Signed-off-by: Yosry Ahmed <yosry.ahmed@linux.dev>
> ---
>  arch/x86/include/asm/svm.h | 78 +++++++++++++++++++-------------------
>  1 file changed, 39 insertions(+), 39 deletions(-)
> 
> diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h
> index 770c7aed5fa5..0bc26b2b3fd7 100644
> --- a/arch/x86/include/asm/svm.h
> +++ b/arch/x86/include/asm/svm.h
> @@ -189,39 +189,39 @@ struct __attribute__ ((__packed__)) vmcb_control_area {
>  #define V_TPR_MASK 0x0f
>  
>  #define V_IRQ_SHIFT 8
> -#define V_IRQ_MASK (1 << V_IRQ_SHIFT)
> +#define V_IRQ_MASK BIT(V_IRQ_SHIFT)

I vote (and if anyone disagrees, their vote doesn't count) to purge the _SHIFT
and _MASK crud.  There is zero reason to define the shifts.

And then when we rename, I would like to try and find better names, e.g. maybe
things like V_GIF and V_ENABLE_GIF_VIRTUALIZATION?

Anyways, that's partly why I asked why this patch is here.  If we're changing
things, then I'd like to do some cleanup.  But this series is already a chonker,
so I'd much prefer to do any cleanup in a separate series.

On Thu, Feb 05, 2026 at 05:37:21PM -0800, Sean Christopherson wrote:
> On Thu, Jan 15, 2026, Yosry Ahmed wrote:
> > Use BIT() and GENMASK() (and *_ULL() variants) to define the bitmasks in
> > svm.h.
> 
> Oh, hey, just what I was talking about.  But why is this buried as patch 22/26?
> AFAICT, it's got nothing to do with the rest of the series.
> 
> > Opportunistically switch the definitions of AVIC_ENABLE_{SHIFT/MASK}
> > and X2APIC_MODE_{SHIFT/MASK}, as well as SVM_EVTINJ_VALID and
> > SVM_EVTINJ_VALID_ERR, such that the bitmasks are defined in the correct
> > order.
> > 
> > No functional change intended.
> > 
> > Signed-off-by: Yosry Ahmed <yosry.ahmed@linux.dev>
> > ---
> >  arch/x86/include/asm/svm.h | 78 +++++++++++++++++++-------------------
> >  1 file changed, 39 insertions(+), 39 deletions(-)
> > 
> > diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h
> > index 770c7aed5fa5..0bc26b2b3fd7 100644
> > --- a/arch/x86/include/asm/svm.h
> > +++ b/arch/x86/include/asm/svm.h
> > @@ -189,39 +189,39 @@ struct __attribute__ ((__packed__)) vmcb_control_area {
> >  #define V_TPR_MASK 0x0f
> >  
> >  #define V_IRQ_SHIFT 8
> > -#define V_IRQ_MASK (1 << V_IRQ_SHIFT)
> > +#define V_IRQ_MASK BIT(V_IRQ_SHIFT)
> 
> I vote (and if anyone disagrees, their vote doesn't count) to purge the _SHIFT
> and _MASK crud.  There is zero reason to define the shifts.
> 
> And then when we rename, I would like to try and find better names, e.g. maybe
> things like V_GIF and V_ENABLE_GIF_VIRTUALIZATION?
> 
> Anyways, that's partly why I asked why this patch is here.  If we're changing
> things, then I'd like to do some cleanup.  But this series is already a chonker,
> so I'd much prefer to do any cleanup in a separate series.

Makes sense, will drop this patch.