Add a node describing the QSPI controller.
There are 2 clocks feeding this controller:
- one for the reference clock
- one that feeds both the ahb and the apb interfaces
As the binding expect either the ref clock, or all three (ref, ahb and
apb) clocks, it makes sense to provide the same clock twice.
Signed-off-by: Miquel Raynal (Schneider Electric) <miquel.raynal@bootlin.com>
---
arch/arm/boot/dts/renesas/r9a06g032.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
index 8debb77803bb..802db8d74178 100644
--- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
@@ -66,6 +66,20 @@ soc {
#size-cells = <1>;
ranges;
+ qspi0: spi@40005000 {
+ compatible = "renesas,r9a06g032-qspi", "renesas,rzn1-qspi", "cdns,qspi-nor";
+ reg = <0x40005000 0x1000>, <0x10000000 0x10000000>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sysctrl R9A06G032_CLK_QSPI0>, <&sysctrl R9A06G032_HCLK_QSPI0>,
+ <&sysctrl R9A06G032_HCLK_QSPI0>;
+ clock-names = "ref", "ahb", "apb";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0>;
+ status = "disabled";
+ };
+
rtc0: rtc@40006000 {
compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc";
reg = <0x40006000 0x1000>;
--
2.51.1Hi Miquel,
On Thu, 15 Jan 2026 at 10:25, Miquel Raynal (Schneider Electric)
<miquel.raynal@bootlin.com> wrote:
> Add a node describing the QSPI controller.
> There are 2 clocks feeding this controller:
> - one for the reference clock
> - one that feeds both the ahb and the apb interfaces
> As the binding expect either the ref clock, or all three (ref, ahb and
> apb) clocks, it makes sense to provide the same clock twice.
>
> Signed-off-by: Miquel Raynal (Schneider Electric) <miquel.raynal@bootlin.com>
Thanks for your patch!
> --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi
> +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
> @@ -66,6 +66,20 @@ soc {
> #size-cells = <1>;
> ranges;
>
> + qspi0: spi@40005000 {
> + compatible = "renesas,r9a06g032-qspi", "renesas,rzn1-qspi", "cdns,qspi-nor";
> + reg = <0x40005000 0x1000>, <0x10000000 0x10000000>;
> + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&sysctrl R9A06G032_CLK_QSPI0>, <&sysctrl R9A06G032_HCLK_QSPI0>,
> + <&sysctrl R9A06G032_HCLK_QSPI0>;
> + clock-names = "ref", "ahb", "apb";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cdns,fifo-width = <4>;
<4> is the default, right?
> + cdns,trigger-address = <0>;
Where in the RZ/N1 docs can I find if these two properties are correct?
> + status = "disabled";
> + };
> +
> rtc0: rtc@40006000 {
> compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc";
> reg = <0x40006000 0x1000>;
The rest LGTM, ignoring my comments on the bindings:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Geert,
On 15/01/2026 at 14:00:49 +01, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> Hi Miquel,
>
> On Thu, 15 Jan 2026 at 10:25, Miquel Raynal (Schneider Electric)
> <miquel.raynal@bootlin.com> wrote:
>> Add a node describing the QSPI controller.
>> There are 2 clocks feeding this controller:
>> - one for the reference clock
>> - one that feeds both the ahb and the apb interfaces
>> As the binding expect either the ref clock, or all three (ref, ahb and
>> apb) clocks, it makes sense to provide the same clock twice.
>>
>> Signed-off-by: Miquel Raynal (Schneider Electric) <miquel.raynal@bootlin.com>
>
> Thanks for your patch!
>
>> --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi
>> +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
>> @@ -66,6 +66,20 @@ soc {
>> #size-cells = <1>;
>> ranges;
>>
>> + qspi0: spi@40005000 {
>> + compatible = "renesas,r9a06g032-qspi", "renesas,rzn1-qspi", "cdns,qspi-nor";
>> + reg = <0x40005000 0x1000>, <0x10000000 0x10000000>;
>> + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&sysctrl R9A06G032_CLK_QSPI0>, <&sysctrl R9A06G032_HCLK_QSPI0>,
>> + <&sysctrl R9A06G032_HCLK_QSPI0>;
>> + clock-names = "ref", "ahb", "apb";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + cdns,fifo-width = <4>;
>
> <4> is the default, right?
>
>> + cdns,trigger-address = <0>;
>
> Where in the RZ/N1 docs can I find if these two properties are
> correct?
Actually, fifo-width, fifo-depth and trigger-address have no meaning for
the RZ/N1 IP, as they are only useful for indirect accesses, which are
not supported. For the field that has a register for dynamic discovery,
it is marked reserved and returns nothing useful. So I will just adapt
the bindings according to these limitations and simply drop these
properties from the DTSI.
Thanks,
Miquèl
Hi Geert,
>> + qspi0: spi@40005000 {
>> + compatible = "renesas,r9a06g032-qspi", "renesas,rzn1-qspi", "cdns,qspi-nor";
>> + reg = <0x40005000 0x1000>, <0x10000000 0x10000000>;
>> + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&sysctrl R9A06G032_CLK_QSPI0>, <&sysctrl R9A06G032_HCLK_QSPI0>,
>> + <&sysctrl R9A06G032_HCLK_QSPI0>;
>> + clock-names = "ref", "ahb", "apb";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + cdns,fifo-width = <4>;
>
> <4> is the default, right?
It is the default in the bindings indeed, however the driver does not
imply that default and errors out if the property is missing. The
property is also marked required in the bindings, which is kind of
incorrect I guess. Also, all DTS explicitly set this value to 4.
However looking into the RM I found "Transmit and receive FIFOs are 16
bytes". I haven't tested that, I will.
>> + cdns,trigger-address = <0>;
>
> Where in the RZ/N1 docs can I find if these two properties are
> correct?
This property is mandatory. Maybe I could just discard it for my
compatible, because it is only relevant for indirect modes, which are
unsupported.
>> + status = "disabled";
>> + };
>> +
>> rtc0: rtc@40006000 {
>> compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc";
>> reg = <0x40006000 0x1000>;
>
> The rest LGTM, ignoring my comments on the bindings:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks for the review, but I guess if I end up changing the DTS snippet
I might drop it. Or would you like me to keep it anyway?
Thanks,
Miquèl
Hi Miquel,
On Fri, 16 Jan 2026 at 10:49, Miquel Raynal <miquel.raynal@bootlin.com> wrote:
> >> + qspi0: spi@40005000 {
> >> + compatible = "renesas,r9a06g032-qspi", "renesas,rzn1-qspi", "cdns,qspi-nor";
> >> + reg = <0x40005000 0x1000>, <0x10000000 0x10000000>;
> >> + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
> >> + clocks = <&sysctrl R9A06G032_CLK_QSPI0>, <&sysctrl R9A06G032_HCLK_QSPI0>,
> >> + <&sysctrl R9A06G032_HCLK_QSPI0>;
> >> + clock-names = "ref", "ahb", "apb";
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> + cdns,fifo-width = <4>;
> >
> > <4> is the default, right?
>
> It is the default in the bindings indeed, however the driver does not
> imply that default and errors out if the property is missing. The
> property is also marked required in the bindings, which is kind of
> incorrect I guess. Also, all DTS explicitly set this value to 4.
OK.
>
> However looking into the RM I found "Transmit and receive FIFOs are 16
> bytes". I haven't tested that, I will.
Oh, that bullet is not present in the docs on the CD I looked at.
It is indeed documented in newer versions.
There's also cdns,fifo-depth, which thus should be 4?
>
> >> + cdns,trigger-address = <0>;
> >
> > Where in the RZ/N1 docs can I find if these two properties are
> > correct?
>
> This property is mandatory. Maybe I could just discard it for my
> compatible, because it is only relevant for indirect modes, which are
> unsupported.
OK.
> >> + status = "disabled";
> >> + };
> >> +
> >> rtc0: rtc@40006000 {
> >> compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc";
> >> reg = <0x40006000 0x1000>;
> >
> > The rest LGTM, ignoring my comments on the bindings:
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Thanks for the review, but I guess if I end up changing the DTS snippet
> I might drop it. Or would you like me to keep it anyway?
Please keep it as long as you don't change the (SoC integration)
things I typically focus on (address, interrupts, clocks), and don't make
too wild changes ;-)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On 16/01/2026 at 11:07:03 +01, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> Hi Miquel,
>
> On Fri, 16 Jan 2026 at 10:49, Miquel Raynal <miquel.raynal@bootlin.com> wrote:
>> >> + qspi0: spi@40005000 {
>> >> + compatible = "renesas,r9a06g032-qspi", "renesas,rzn1-qspi", "cdns,qspi-nor";
>> >> + reg = <0x40005000 0x1000>, <0x10000000 0x10000000>;
>> >> + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
>> >> + clocks = <&sysctrl R9A06G032_CLK_QSPI0>, <&sysctrl R9A06G032_HCLK_QSPI0>,
>> >> + <&sysctrl R9A06G032_HCLK_QSPI0>;
>> >> + clock-names = "ref", "ahb", "apb";
>> >> + #address-cells = <1>;
>> >> + #size-cells = <0>;
>> >> + cdns,fifo-width = <4>;
>> >
>> > <4> is the default, right?
>>
>> It is the default in the bindings indeed, however the driver does not
>> imply that default and errors out if the property is missing. The
>> property is also marked required in the bindings, which is kind of
>> incorrect I guess. Also, all DTS explicitly set this value to 4.
>
> OK.
>
>>
>> However looking into the RM I found "Transmit and receive FIFOs are 16
>> bytes". I haven't tested that, I will.
>
> Oh, that bullet is not present in the docs on the CD I looked at.
> It is indeed documented in newer versions.
>
> There's also cdns,fifo-depth, which thus should be 4?
Ah, that's right. You mean fifo-width = 4 and fifo-depth = 4, right?
It is marked as being discoverable by reading CQSPI_REG_SRAMPARTITION,
but on my board this register returns 0. So I guess yes, I will go for
fifo-depth = 4 and we should be fine.
...
>> > The rest LGTM, ignoring my comments on the bindings:
>> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>>
>> Thanks for the review, but I guess if I end up changing the DTS snippet
>> I might drop it. Or would you like me to keep it anyway?
>
> Please keep it as long as you don't change the (SoC integration)
> things I typically focus on (address, interrupts, clocks), and don't make
> too wild changes ;-)
Thanks,
Miquèl
© 2016 - 2026 Red Hat, Inc.