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[PATCH v2] Documentation: hwmon: coretemp: Fix malformed RST table

Laveesh Bansal posted 1 patch 3 weeks, 4 days ago 
Documentation/hwmon/coretemp.rst | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
[PATCH v2] Documentation: hwmon: coretemp: Fix malformed RST table
Posted by Laveesh Bansal 3 weeks, 4 days ago 
Shorten the Celeron/Pentium processor entries in the TjMax table to fit
within the 47-character column width, fixing the RST table parsing error.

The following entries exceeded the column width:
  - "Celeron/Pentium Processors (Goldmont/Apollo Lake)" (49 chars)
  - "Celeron/Pentium Processors (Goldmont Plus/Gemini Lake)" (54 chars)
  - "Celeron/Pentium Processors (Tremont/Jasper Lake)" (48 chars)

Drop "Processors" from these entries as this preserves all searchable
technical keywords (Celeron, Pentium, Goldmont, Gemini Lake, etc.) while
"Processors" is implied by the chip names and adds no search value.

Fixes: 099cc1051df7 ("Documentation: hwmon: coretemp: Update supported CPUs and TjMax values")
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Closes: https://lore.kernel.org/linux-next/20260113155444.57c7775b@canb.auug.org.au/
Signed-off-by: Laveesh Bansal <laveeshb@laveeshbansal.com>
---
v2:
  - Shorten text instead of widening columns (widening would require
    adjusting 101 data rows to realign TjMax values)

Tested with:
  - python3 -m docutils Documentation/hwmon/coretemp.rst /dev/null
  - make htmldocs

Open to alternative approaches if anyone has a better solution.
---
 Documentation/hwmon/coretemp.rst | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/Documentation/hwmon/coretemp.rst b/Documentation/hwmon/coretemp.rst
index 3afb179e0ced..3ba44b57d028 100644
--- a/Documentation/hwmon/coretemp.rst
+++ b/Documentation/hwmon/coretemp.rst
@@ -120,12 +120,12 @@ Process		Processor					TjMax(C)
 		x5-E3940/E3930					105
 		x7-E3950					105
 
-14nm		Celeron/Pentium Processors (Goldmont/Apollo Lake)
+14nm		Celeron/Pentium (Goldmont/Apollo Lake)
 		J3455/J3355					105
 		N3450/N3350					105
 		N4200						105
 
-14nm		Celeron/Pentium Processors (Goldmont Plus/Gemini Lake)
+14nm		Celeron/Pentium (Goldmont Plus/Gemini Lake)
 		J4105/J4005					105
 		N4100/N4000					105
 		N5000						105
@@ -133,7 +133,7 @@ Process		Processor					TjMax(C)
 10nm		Atom Processors (Tremont/Elkhart Lake)
 		x6000E						105
 
-10nm		Celeron/Pentium Processors (Tremont/Jasper Lake)
+10nm		Celeron/Pentium (Tremont/Jasper Lake)
 		N4500/N5100/N6000 series			105
 
 45nm		Xeon Processors 5400 Quad-Core
-- 
2.43.0
Re: [PATCH v2] Documentation: hwmon: coretemp: Fix malformed RST table
Posted by Guenter Roeck 3 weeks, 4 days ago 
On 1/12/26 23:53, Laveesh Bansal wrote:
> Shorten the Celeron/Pentium processor entries in the TjMax table to fit
> within the 47-character column width, fixing the RST table parsing error.
> 
> The following entries exceeded the column width:
>    - "Celeron/Pentium Processors (Goldmont/Apollo Lake)" (49 chars)
>    - "Celeron/Pentium Processors (Goldmont Plus/Gemini Lake)" (54 chars)
>    - "Celeron/Pentium Processors (Tremont/Jasper Lake)" (48 chars)
> 
> Drop "Processors" from these entries as this preserves all searchable
> technical keywords (Celeron, Pentium, Goldmont, Gemini Lake, etc.) while
> "Processors" is implied by the chip names and adds no search value.
> 
> Fixes: 099cc1051df7 ("Documentation: hwmon: coretemp: Update supported CPUs and TjMax values")
> Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
> Closes: https://lore.kernel.org/linux-next/20260113155444.57c7775b@canb.auug.org.au/
> Signed-off-by: Laveesh Bansal <laveeshb@laveeshbansal.com>
> ---
> v2:
>    - Shorten text instead of widening columns (widening would require
>      adjusting 101 data rows to realign TjMax values)
> 
> Tested with:
>    - python3 -m docutils Documentation/hwmon/coretemp.rst /dev/null
>    - make htmldocs
> 
> Open to alternative approaches if anyone has a better solution.
> ---
>   Documentation/hwmon/coretemp.rst | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/hwmon/coretemp.rst b/Documentation/hwmon/coretemp.rst
> index 3afb179e0ced..3ba44b57d028 100644
> --- a/Documentation/hwmon/coretemp.rst
> +++ b/Documentation/hwmon/coretemp.rst
> @@ -120,12 +120,12 @@ Process		Processor					TjMax(C)
>   		x5-E3940/E3930					105
>   		x7-E3950					105
>   
> -14nm		Celeron/Pentium Processors (Goldmont/Apollo Lake)
> +14nm		Celeron/Pentium (Goldmont/Apollo Lake)

I updated the patch to split the affected lines.

		Celeron/Pentium Processors
		(Goldmont/Apollo Lake)

Guenter
Re: [PATCH v2] Documentation: hwmon: coretemp: Fix malformed RST table
Posted by Randy Dunlap 3 weeks, 4 days ago 

On 1/12/26 11:53 PM, Laveesh Bansal wrote:
> Shorten the Celeron/Pentium processor entries in the TjMax table to fit
> within the 47-character column width, fixing the RST table parsing error.
> 
> The following entries exceeded the column width:
>   - "Celeron/Pentium Processors (Goldmont/Apollo Lake)" (49 chars)
>   - "Celeron/Pentium Processors (Goldmont Plus/Gemini Lake)" (54 chars)
>   - "Celeron/Pentium Processors (Tremont/Jasper Lake)" (48 chars)
> 
> Drop "Processors" from these entries as this preserves all searchable
> technical keywords (Celeron, Pentium, Goldmont, Gemini Lake, etc.) while
> "Processors" is implied by the chip names and adds no search value.
> 
> Fixes: 099cc1051df7 ("Documentation: hwmon: coretemp: Update supported CPUs and TjMax values")
> Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
> Closes: https://lore.kernel.org/linux-next/20260113155444.57c7775b@canb.auug.org.au/
> Signed-off-by: Laveesh Bansal <laveeshb@laveeshbansal.com>

Works for me. Thanks.

Acked-by: Randy Dunlap <rdunlap@infradead.org>
Tested-by: Randy Dunlap <rdunlap@infradead.org>

> ---
> v2:
>   - Shorten text instead of widening columns (widening would require
>     adjusting 101 data rows to realign TjMax values)
> 
> Tested with:
>   - python3 -m docutils Documentation/hwmon/coretemp.rst /dev/null
>   - make htmldocs
> 
> Open to alternative approaches if anyone has a better solution.
> ---
>  Documentation/hwmon/coretemp.rst | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/hwmon/coretemp.rst b/Documentation/hwmon/coretemp.rst
> index 3afb179e0ced..3ba44b57d028 100644
> --- a/Documentation/hwmon/coretemp.rst
> +++ b/Documentation/hwmon/coretemp.rst
> @@ -120,12 +120,12 @@ Process		Processor					TjMax(C)
>  		x5-E3940/E3930					105
>  		x7-E3950					105
>  
> -14nm		Celeron/Pentium Processors (Goldmont/Apollo Lake)
> +14nm		Celeron/Pentium (Goldmont/Apollo Lake)
>  		J3455/J3355					105
>  		N3450/N3350					105
>  		N4200						105
>  
> -14nm		Celeron/Pentium Processors (Goldmont Plus/Gemini Lake)
> +14nm		Celeron/Pentium (Goldmont Plus/Gemini Lake)
>  		J4105/J4005					105
>  		N4100/N4000					105
>  		N5000						105
> @@ -133,7 +133,7 @@ Process		Processor					TjMax(C)
>  10nm		Atom Processors (Tremont/Elkhart Lake)
>  		x6000E						105
>  
> -10nm		Celeron/Pentium Processors (Tremont/Jasper Lake)
> +10nm		Celeron/Pentium (Tremont/Jasper Lake)
>  		N4500/N5100/N6000 series			105
>  
>  45nm		Xeon Processors 5400 Quad-Core

-- 
~Randy

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