Some parallel panels have a pixelclk of 24.19 MHz. Add support for
241.90 MHz so a by 10 divider can be used to derive the exact pixelclk.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
 drivers/clk/imx/clk-fracn-gppll.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c
index 579f76494eb041dfba58b8cd10eb2453a0ec4178..eb3d5e3c53946f3caf83bcff654c6481611375e3 100644
--- a/drivers/clk/imx/clk-fracn-gppll.c
+++ b/drivers/clk/imx/clk-fracn-gppll.c
@@ -89,7 +89,8 @@ static const struct imx_fracn_gppll_rate_table fracn_tbl[] = {
 	PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12),
 	PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10),
 	PLL_FRACN_GP(332600000U, 138, 584, 1000, 0, 10),
-	PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12)
+	PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12),
+	PLL_FRACN_GP(241900000U, 201, 584, 1000, 0, 20)
 };
 
 struct imx_fracn_gppll_clk imx_fracn_gppll = {

-- 
2.47.3

On Tue, Jan 13, 2026 at 2:29 PM Marco Felsch <m.felsch@pengutronix.de> wrote:
>
> Some parallel panels have a pixelclk of 24.19 MHz. Add support for
> 241.90 MHz so a by 10 divider can be used to derive the exact pixelclk.
>
> Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
> ---
>  drivers/clk/imx/clk-fracn-gppll.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c
> index 579f76494eb041dfba58b8cd10eb2453a0ec4178..eb3d5e3c53946f3caf83bcff654c6481611375e3 100644
> --- a/drivers/clk/imx/clk-fracn-gppll.c
> +++ b/drivers/clk/imx/clk-fracn-gppll.c
> @@ -89,7 +89,8 @@ static const struct imx_fracn_gppll_rate_table fracn_tbl[] = {
>         PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12),
>         PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10),
>         PLL_FRACN_GP(332600000U, 138, 584, 1000, 0, 10),
> -       PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12)
> +       PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12),
> +       PLL_FRACN_GP(241900000U, 201, 584, 1000, 0, 20)

Can you please end this line with a comma so that next addition at the end of
the array will create a simpler diff?

Look for example at int_tbl array in the same file.

thanks,
Daniel.

On 26-01-13, Daniel Baluta wrote:
> On Tue, Jan 13, 2026 at 2:29 PM Marco Felsch <m.felsch@pengutronix.de> wrote:
> >
> > Some parallel panels have a pixelclk of 24.19 MHz. Add support for
> > 241.90 MHz so a by 10 divider can be used to derive the exact pixelclk.
> >
> > Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
> > ---
> >  drivers/clk/imx/clk-fracn-gppll.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c
> > index 579f76494eb041dfba58b8cd10eb2453a0ec4178..eb3d5e3c53946f3caf83bcff654c6481611375e3 100644
> > --- a/drivers/clk/imx/clk-fracn-gppll.c
> > +++ b/drivers/clk/imx/clk-fracn-gppll.c
> > @@ -89,7 +89,8 @@ static const struct imx_fracn_gppll_rate_table fracn_tbl[] = {
> >         PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12),
> >         PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10),
> >         PLL_FRACN_GP(332600000U, 138, 584, 1000, 0, 10),
> > -       PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12)
> > +       PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12),
> > +       PLL_FRACN_GP(241900000U, 201, 584, 1000, 0, 20)
> 
> Can you please end this line with a comma so that next addition at the end of
> the array will create a simpler diff?

Thought about this too but I don't know why I didn't added this.

Thanks for the input.

Regards,
  Marco

> Look for example at int_tbl array in the same file.
> 
> thanks,
> Daniel.
> 

-- 
#gernperDu 
#CallMeByMyFirstName

Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | https://www.pengutronix.de/ |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-9    |