From: Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>
Enable gpio-line-names property in the schema and add example showing
how to use it with multiple MCP23S08/17/18 chips sharing the same SPI
chip select. Names are assigned sequentially in hardware address order.
Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>
---
.../bindings/pinctrl/microchip,mcp23s08.yaml | 33 ++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,mcp23s08.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,mcp23s08.yaml
index e07f4723de17..667be31b6da3 100644
--- a/Documentation/devicetree/bindings/pinctrl/microchip,mcp23s08.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/microchip,mcp23s08.yaml
@@ -42,6 +42,8 @@ properties:
interrupts:
maxItems: 1
+ gpio-line-names: true
+
reset-gpios:
description: GPIO specifier for active-low reset pin.
maxItems: 1
@@ -159,3 +161,34 @@ examples:
microchip,spi-present-mask = /bits/ 8 <0x01>;
};
};
+
+ - |
+ /* Multiple chips sharing same SPI CS with gpio-line-names */
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio@0 {
+ compatible = "microchip,mcp23s17";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ spi-max-frequency = <10000000>;
+ /* Two chips at hardware addresses 0 and 1 */
+ microchip,spi-present-mask = /bits/ 8 <0x03>;
+ /*
+ * Names assigned sequentially in address order.
+ * First 16 names for chip at address 0 (GPA0-7, GPB0-7).
+ * Next 16 names for chip at address 1 (GPA0-7, GPB0-7).
+ */
+ gpio-line-names =
+ "EXP0_GPA0", "EXP0_GPA1", "EXP0_GPA2", "EXP0_GPA3",
+ "EXP0_GPA4", "EXP0_GPA5", "EXP0_GPA6", "EXP0_GPA7",
+ "EXP0_GPB0", "EXP0_GPB1", "EXP0_GPB2", "EXP0_GPB3",
+ "EXP0_GPB4", "EXP0_GPB5", "EXP0_GPB6", "EXP0_GPB7",
+ "EXP1_GPA0", "EXP1_GPA1", "EXP1_GPA2", "EXP1_GPA3",
+ "EXP1_GPA4", "EXP1_GPA5", "EXP1_GPA6", "EXP1_GPA7",
+ "EXP1_GPB0", "EXP1_GPB1", "EXP1_GPB2", "EXP1_GPB3",
+ "EXP1_GPB4", "EXP1_GPB5", "EXP1_GPB6", "EXP1_GPB7";
+ };
+ };
--
2.39.5Hi Jean-Michel,
thanks for your patch!
On Tue, Jan 13, 2026 at 3:29 PM Jean-Michel Hautbois via B4 Relay
<devnull+jeanmichel.hautbois.yoseli.org@kernel.org> wrote:
> + gpio-line-names: true
I have a bit of similar concerns as Krzysztof, this is unlimited.
This is actually:
- 8 for microchip,mcp23008 and microchip,mcp23s08
- 16 for microchip,mcp23017, microchip,mcp23018, microchip,mcp23s17
and microchip,mcp23s18
(The "s" variants are just the SPI variants of the same chip...)
Make some fancy - if: clauses to decide the maxItems from the compatible.
Don't hesitate to ask for help if this gets complicated, I get a panic
every time I have to deal with it because of the whitespacing business.
+ /*
> + * Names assigned sequentially in address order.
> + * First 16 names for chip at address 0 (GPA0-7, GPB0-7).
> + * Next 16 names for chip at address 1 (GPA0-7, GPB0-7).
> + */
> + gpio-line-names =
> + "EXP0_GPA0", "EXP0_GPA1", "EXP0_GPA2", "EXP0_GPA3",
> + "EXP0_GPA4", "EXP0_GPA5", "EXP0_GPA6", "EXP0_GPA7",
> + "EXP0_GPB0", "EXP0_GPB1", "EXP0_GPB2", "EXP0_GPB3",
> + "EXP0_GPB4", "EXP0_GPB5", "EXP0_GPB6", "EXP0_GPB7",
> + "EXP1_GPA0", "EXP1_GPA1", "EXP1_GPA2", "EXP1_GPA3",
> + "EXP1_GPA4", "EXP1_GPA5", "EXP1_GPA6", "EXP1_GPA7",
> + "EXP1_GPB0", "EXP1_GPB1", "EXP1_GPB2", "EXP1_GPB3",
> + "EXP1_GPB4", "EXP1_GPB5", "EXP1_GPB6", "EXP1_GPB7";
So we get this, and we already have this (from the example):
gpiopullups: pinmux {
pins = "gpio0", "gpio1", "gpio2", "gpio3",
"gpio4", "gpio5", "gpio6", "gpio7",
"gpio8", "gpio9", "gpio10", "gpio11",
"gpio12", "gpio13", "gpio14", "gpio15";
bias-pull-up;
};
This is wild, we need some constraints I think.
Whatever we come up with to limit the number of items in gpio-line-names
should also be applied to the "pins" list in the pinmux node.
Yours,
Linus Walleij
On Tue, Jan 13, 2026 at 03:29:48PM +0100, Jean-Michel Hautbois wrote:
> Enable gpio-line-names property in the schema and add example showing
> how to use it with multiple MCP23S08/17/18 chips sharing the same SPI
> chip select. Names are assigned sequentially in hardware address order.
>
> Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>
> ---
> .../bindings/pinctrl/microchip,mcp23s08.yaml | 33 ++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,mcp23s08.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,mcp23s08.yaml
> index e07f4723de17..667be31b6da3 100644
> --- a/Documentation/devicetree/bindings/pinctrl/microchip,mcp23s08.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/microchip,mcp23s08.yaml
> @@ -42,6 +42,8 @@ properties:
> interrupts:
> maxItems: 1
>
> + gpio-line-names: true
Variable number of GPIOs? No constraints possible at all?
> +
> reset-gpios:
> description: GPIO specifier for active-low reset pin.
> maxItems: 1
> @@ -159,3 +161,34 @@ examples:
> microchip,spi-present-mask = /bits/ 8 <0x01>;
> };
> };
> +
> + - |
> + /* Multiple chips sharing same SPI CS with gpio-line-names */
> + spi {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + gpio@0 {
> + compatible = "microchip,mcp23s17";
> + reg = <0>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + spi-max-frequency = <10000000>;
> + /* Two chips at hardware addresses 0 and 1 */
> + microchip,spi-present-mask = /bits/ 8 <0x03>;
> + /*
> + * Names assigned sequentially in address order.
> + * First 16 names for chip at address 0 (GPA0-7, GPB0-7).
> + * Next 16 names for chip at address 1 (GPA0-7, GPB0-7).
> + */
> + gpio-line-names =
Just extend existing example. There is little point in adding one new
example per one new different property.
Best regards,
Krzysztof
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