From: Wesley Cheng <wesley.cheng@oss.qualcomm.com>
The Glymur USB system contains 3 USB type C ports, 1 USB multiport
controller and a USB 2.0 only controller. This encompasses 5 SS USB QMP
PHYs (3 combo and 2 uni) and 6 M31 eUSB2 PHYs. All controllers are SNPS
DWC3 based, so describe them as flattened DWC3 QCOM nodes.
Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com>
Co-developed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur.dtsi | 663 ++++++++++++++++++++++++++++++++++-
1 file changed, 658 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index eb042541cfe1..53b8ab7580bd 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -750,11 +750,11 @@ gcc: clock-controller@100000 {
<0>,
<0>,
<0>,
- <0>,
- <0>,
- <0>,
- <0>,
- <0>,
+ <&usb1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
+ <&usb1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
+ <&usb1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
+ <&usb_mp_qmpphy0 QMP_USB43DP_USB3_PIPE_CLK>,
+ <&usb_mp_qmpphy1 QMP_USB43DP_USB3_PIPE_CLK>,
<0>,
<0>,
<0>,
@@ -2224,6 +2224,249 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
};
};
+ usb_mp_hsphy0: phy@fa1000 {
+ compatible = "qcom,glymur-m31-eusb2-phy",
+ "qcom,sm8750-m31-eusb2-phy";
+
+ reg = <0 0x00fa1000 0 0x29c>;
+ #phy-cells = <0>;
+
+ clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
+
+ status = "disabled";
+ };
+
+ usb_mp_hsphy1: phy@fa2000 {
+ compatible = "qcom,glymur-m31-eusb2-phy",
+ "qcom,sm8750-m31-eusb2-phy";
+
+ reg = <0 0x00fa2000 0 0x29c>;
+ #phy-cells = <0>;
+
+ clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
+
+ status = "disabled";
+ };
+
+ usb_mp_qmpphy0: phy@fa3000 {
+ compatible = "qcom,glymur-qmp-usb3-uni-phy";
+ reg = <0 0x00fa3000 0 0x2000>;
+
+ clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
+ <&tcsr TCSR_USB3_0_CLKREF_EN>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
+ clock-names = "aux",
+ "clkref",
+ "ref",
+ "com_aux",
+ "pipe";
+
+ power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>;
+
+ resets = <&gcc GCC_USB3_MP_SS0_PHY_BCR>,
+ <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
+ reset-names = "phy",
+ "phy_phy";
+
+ clock-output-names = "usb3_uni_phy_0_pipe_clk_src";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb_mp_qmpphy1: phy@fa5000 {
+ compatible = "qcom,glymur-qmp-usb3-uni-phy";
+ reg = <0 0x00fa5000 0 0x2000>;
+
+ clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
+ <&tcsr TCSR_USB3_1_CLKREF_EN>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
+ clock-names = "aux",
+ "clkref",
+ "ref",
+ "com_aux",
+ "pipe";
+
+ power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>;
+
+ resets = <&gcc GCC_USB3_MP_SS1_PHY_BCR>,
+ <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
+ reset-names = "phy",
+ "phy_phy";
+
+ clock-output-names = "usb3_uni_phy_1_pipe_clk_src";
+
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb1_ss0_hsphy: phy@fd3000 {
+ compatible = "qcom,glymur-m31-eusb2-phy",
+ "qcom,sm8750-m31-eusb2-phy";
+
+ reg = <0 0x00fd3000 0 0x29c>;
+ #phy-cells = <0>;
+
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+
+ status = "disabled";
+ };
+
+ usb1_ss0_qmpphy: phy@fd5000 {
+ compatible = "qcom,glymur-qmp-usb3-dp-phy";
+ reg = <0 0x00fd5000 0 0x8000>;
+
+ clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "com_aux",
+ "usb3_pipe";
+
+ resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
+ <&gcc GCC_USB3PHY_PHY_PRIM_BCR>;
+
+ reset-names = "phy",
+ "common";
+
+ power-domains = <&gcc GCC_USB_0_PHY_GDSC>;
+
+ #clock-cells = <1>;
+ #phy-cells = <1>;
+
+ mode-switch;
+ orientation-switch;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb1_ss0_qmpphy_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb1_ss0_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb1_ss0_dwc3_ss>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ usb_dp_qmpphy_dp_in: endpoint {
+ };
+ };
+ };
+ };
+
+ usb1_ss1_hsphy: phy@fdd000 {
+ compatible = "qcom,glymur-m31-eusb2-phy",
+ "qcom,sm8750-m31-eusb2-phy";
+
+ reg = <0 0x00fdd000 0 0x29c>;
+ #phy-cells = <0>;
+
+ resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
+
+ status = "disabled";
+ };
+
+ usb1_ss1_qmpphy: phy@fde000 {
+ compatible = "qcom,glymur-qmp-usb3-dp-phy";
+ reg = <0 0x00fde000 0 0x8000>;
+
+ clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>,
+ <&tcsr TCSR_USB4_1_CLKREF_EN>;
+ clock-names = "aux",
+ "ref",
+ "com_aux",
+ "usb3_pipe",
+ "clkref";
+
+ power-domains = <&gcc GCC_USB_1_PHY_GDSC>;
+
+ resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
+ <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
+ reset-names = "phy",
+ "common";
+
+ #clock-cells = <1>;
+ #phy-cells = <1>;
+
+ mode-switch;
+ orientation-switch;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb1_ss1_qmpphy_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb1_ss1_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb1_ss1_dwc3_ss>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ usb1_ss1_qmpphy_dp_in: endpoint {
+ };
+ };
+ };
+ };
+
+ usb_2_hsphy: phy@fa0000 {
+ compatible = "qcom,glymur-m31-eusb2-phy",
+ "qcom,sm8750-m31-eusb2-phy";
+ reg = <0 0x00fa0000 0 0x154>;
+ #phy-cells = <0>;
+
+ clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>;
+
+ status = "disabled";
+ };
+
+
cnoc_main: interconnect@1500000 {
compatible = "qcom,glymur-cnoc-main";
reg = <0x0 0x01500000 0x0 0x17080>;
@@ -3164,6 +3407,416 @@ lpass_ag_noc: interconnect@7e40000 {
#interconnect-cells = <2>;
};
+ usb1_ss2_hsphy: phy@88e0000 {
+ compatible = "qcom,glymur-m31-eusb2-phy",
+ "qcom,sm8750-m31-eusb2-phy";
+
+ reg = <0 0x088e0000 0 0x29c>;
+ #phy-cells = <0>;
+
+ clocks = <&tcsr TCSR_USB2_4_CLKREF_EN>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_TERT_BCR>;
+
+ status = "disabled";
+ };
+
+ usb1_ss2_qmpphy: phy@88e1000 {
+ compatible = "qcom,glymur-qmp-usb3-dp-phy";
+ reg = <0 0x088e1000 0 0x8000>;
+
+ clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>,
+ <&tcsr TCSR_USB4_2_CLKREF_EN>;
+ clock-names = "aux",
+ "ref",
+ "com_aux",
+ "usb3_pipe",
+ "clkref";
+
+ power-domains = <&gcc GCC_USB_2_PHY_GDSC>;
+
+ resets = <&gcc GCC_USB3_PHY_TERT_BCR>,
+ <&gcc GCC_USB3PHY_PHY_TERT_BCR>;
+ reset-names = "phy",
+ "common";
+
+ #clock-cells = <1>;
+ #phy-cells = <1>;
+
+ mode-switch;
+ orientation-switch;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb1_ss2_qmpphy_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb1_ss2_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb1_ss2_dwc3_ss>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ usb1_ss2_qmpphy_dp_in: endpoint {
+ };
+ };
+ };
+ };
+
+ usb1_ss0: usb@a600000 {
+ compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3";
+ reg = <0 0x0a600000 0 0xfc100>;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>,
+ <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi",
+ "noc_aggr_north",
+ "noc_aggr_south";
+
+ interrupts-extended = <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 90 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 60 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 17 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "dwc_usb3",
+ "pwr_event",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
+
+ power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
+ resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+ iommus = <&apps_smmu 0x1420 0x0>;
+ phys = <&usb1_ss0_hsphy>,
+ <&usb1_ss0_qmpphy QMP_USB43DP_USB3_PHY>;
+ phy-names = "usb2-phy",
+ "usb3-phy";
+
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,usb2-lpm-disable;
+
+ usb-role-switch;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb1_ss0_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb1_ss0_dwc3_ss: endpoint {
+ remote-endpoint = <&usb1_ss0_qmpphy_usb_ss_in>;
+ };
+ };
+ };
+ };
+
+ usb1_ss1: usb@a800000 {
+ compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3";
+ reg = <0 0x0a800000 0 0xfc100>;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
+ <&gcc GCC_USB30_SEC_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
+ <&gcc GCC_USB30_SEC_SLEEP_CLK>,
+ <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
+ <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>,
+ <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi",
+ "noc_aggr_north",
+ "noc_aggr_south";
+
+ interrupts-extended = <&intc GIC_SPI 875 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 88 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 87 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 76 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "dwc_usb3",
+ "pwr_event",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
+
+ resets = <&gcc GCC_USB30_SEC_BCR>;
+ power-domains = <&gcc GCC_USB30_SEC_GDSC>;
+
+ iommus = <&apps_smmu 0x1460 0x0>;
+
+ phys = <&usb1_ss1_hsphy>,
+ <&usb1_ss1_qmpphy QMP_USB43DP_USB3_PHY>;
+ phy-names = "usb2-phy",
+ "usb3-phy";
+
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,usb2-lpm-disable;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb1_ss1_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb1_ss1_dwc3_ss: endpoint {
+ remote-endpoint = <&usb1_ss1_qmpphy_usb_ss_in>;
+ };
+ };
+ };
+ };
+
+ usb1_ss2: usb@a000000 {
+ compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3";
+ reg = <0 0x0a000000 0 0xfc100>;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>,
+ <&gcc GCC_USB30_TERT_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>,
+ <&gcc GCC_USB30_TERT_SLEEP_CLK>,
+ <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>,
+ <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>,
+ <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi",
+ "noc_aggr_north",
+ "noc_aggr_south";
+
+ interrupts-extended = <&intc GIC_SPI 871 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 89 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 81 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 75 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "dwc_usb3",
+ "pwr_event",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
+
+ resets = <&gcc GCC_USB30_TERT_BCR>;
+ power-domains = <&gcc GCC_USB30_TERT_GDSC>;
+
+ iommus = <&apps_smmu 0x420 0x0>;
+
+ phys = <&usb1_ss2_hsphy>,
+ <&usb1_ss2_qmpphy QMP_USB43DP_USB3_PHY>;
+ phy-names = "usb2-phy",
+ "usb3-phy";
+
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,usb2-lpm-disable;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb1_ss2_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb1_ss2_dwc3_ss: endpoint {
+ remote-endpoint = <&usb1_ss2_qmpphy_usb_ss_in>;
+ };
+ };
+ };
+ };
+
+ usb_2: usb@a2f8800 {
+ compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3";
+ reg = <0 0x0a200000 0 0xfc100>;
+
+ clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
+ <&gcc GCC_USB20_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
+ <&gcc GCC_USB20_SLEEP_CLK>,
+ <&gcc GCC_USB20_MOCK_UTMI_CLK>,
+ <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>,
+ <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi",
+ "noc_aggr_north",
+ "noc_aggr_south";
+
+ assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB20_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <200000000>;
+
+ interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 92 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 57 IRQ_TYPE_EDGE_BOTH>,
+ <&intc GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dwc_usb3",
+ "pwr_event",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "hs_phy_irq";
+
+ resets = <&gcc GCC_USB20_PRIM_BCR>;
+
+ power-domains = <&gcc GCC_USB20_PRIM_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ iommus = <&apps_smmu 0x0ce0 0x0>;
+
+ interconnects = <&aggre3_noc MASTER_USB2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_USB2 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "usb-ddr",
+ "apps-usb";
+
+ phys = <&usb_2_hsphy>;
+ phy-names = "usb2-phy";
+
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+
+ dr_mode = "host";
+
+ maximum-speed = "high-speed";
+
+ status = "disabled";
+ };
+
+ usb_mp: usb@a400000 {
+ compatible = "qcom,glymur-dwc3-mp", "qcom,snps-dwc3";
+ reg = <0 0x0a400000 0 0xfc100>;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
+ <&gcc GCC_USB30_MP_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
+ <&gcc GCC_USB30_MP_SLEEP_CLK>,
+ <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
+ <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>,
+ <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi",
+ "noc_aggr_north",
+ "noc_aggr_south";
+
+ interrupts-extended = <&intc GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 12 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 11 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 14 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 13 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 78 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 77 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dwc_usb3",
+ "pwr_event_1",
+ "pwr_event_2",
+ "hs_phy_1",
+ "hs_phy_2",
+ "dp_hs_phy_1",
+ "dm_hs_phy_1",
+ "dp_hs_phy_2",
+ "dm_hs_phy_2",
+ "ss_phy_1",
+ "ss_phy_2";
+
+ resets = <&gcc GCC_USB30_MP_BCR>;
+ power-domains = <&gcc GCC_USB30_MP_GDSC>;
+
+ iommus = <&apps_smmu 0xda0 0x0>;
+
+ phys = <&usb_mp_hsphy0>,
+ <&usb_mp_qmpphy0>,
+ <&usb_mp_hsphy1>,
+ <&usb_mp_qmpphy1>;
+ phy-names = "usb2-0",
+ "usb3-0",
+ "usb2-1",
+ "usb3-1";
+
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ snps,usb3_lpm_capable;
+ snps,dis_u3_susphy_quirk;
+ snps,usb2-lpm-disable;
+
+ dr_mode = "host";
+
+ status = "disabled";
+ };
+
+
dispcc: clock-controller@af00000 {
compatible = "qcom,glymur-dispcc";
reg = <0x0 0x0af00000 0x0 0x20000>;
--
2.48.1On Tue, Jan 13, 2026 at 02:33:05PM +0200, Abel Vesa wrote:
> From: Wesley Cheng <wesley.cheng@oss.qualcomm.com>
>
> The Glymur USB system contains 3 USB type C ports, 1 USB multiport
> controller and a USB 2.0 only controller. This encompasses 5 SS USB QMP
> PHYs (3 combo and 2 uni) and 6 M31 eUSB2 PHYs. All controllers are SNPS
> DWC3 based, so describe them as flattened DWC3 QCOM nodes.
>
> Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com>
> Co-developed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur.dtsi | 663 ++++++++++++++++++++++++++++++++++-
> 1 file changed, 658 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> index eb042541cfe1..53b8ab7580bd 100644
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> @@ -750,11 +750,11 @@ gcc: clock-controller@100000 {
> <0>,
> <0>,
> <0>,
> - <0>,
> - <0>,
> - <0>,
> - <0>,
> - <0>,
> + <&usb1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
> + <&usb1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
> + <&usb1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
> + <&usb_mp_qmpphy0 QMP_USB43DP_USB3_PIPE_CLK>,
> + <&usb_mp_qmpphy1 QMP_USB43DP_USB3_PIPE_CLK>,
> <0>,
> <0>,
> <0>,
> @@ -2224,6 +2224,249 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
> };
> };
>
> + usb_mp_hsphy0: phy@fa1000 {
> + compatible = "qcom,glymur-m31-eusb2-phy",
> + "qcom,sm8750-m31-eusb2-phy";
> +
> + reg = <0 0x00fa1000 0 0x29c>;
Here and everywhere else, 0x0 instead of just 0 in the reg properties.
> + #phy-cells = <0>;
> +
> + clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
> + clock-names = "ref";
> +
> + resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
> +
> + status = "disabled";
> + };
> +
--
With best wishes
Dmitry
On 1/13/26 1:33 PM, Abel Vesa wrote:
> From: Wesley Cheng <wesley.cheng@oss.qualcomm.com>
>
> The Glymur USB system contains 3 USB type C ports, 1 USB multiport
> controller and a USB 2.0 only controller. This encompasses 5 SS USB QMP
> PHYs (3 combo and 2 uni) and 6 M31 eUSB2 PHYs. All controllers are SNPS
> DWC3 based, so describe them as flattened DWC3 QCOM nodes.
>
> Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com>
> Co-developed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---
[...]
>
> + usb_mp_hsphy0: phy@fa1000 {
> + compatible = "qcom,glymur-m31-eusb2-phy",
> + "qcom,sm8750-m31-eusb2-phy";
> +
> + reg = <0 0x00fa1000 0 0x29c>;
> + #phy-cells = <0>;
> +
> + clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
> + clock-names = "ref";
> +
> + resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
> +
> + status = "disabled";
> + };
> +
> + usb_mp_hsphy1: phy@fa2000 {
> + compatible = "qcom,glymur-m31-eusb2-phy",
> + "qcom,sm8750-m31-eusb2-phy";
> +
> + reg = <0 0x00fa2000 0 0x29c>;
> + #phy-cells = <0>;
> +
> + clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>;
> + clock-names = "ref";
> +
> + resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
> +
> + status = "disabled";
> + };
[...]
> + usb1_ss0_hsphy: phy@fd3000 {
Let's not repeat the mess introduced in hamoa..
Perhaps let's fall back to usb_0 etc.?
[...]
> + snps,dis_u2_susphy_quirk;
> + snps,dis_enblslpm_quirk;
> + snps,dis_u3_susphy_quirk;
> + snps,usb2-lpm-disable;
Other SoCs have a list that's much longer, please consult Wesley if
this list is enough
Konrad
On 26-01-13 14:13:32, Konrad Dybcio wrote: > On 1/13/26 1:33 PM, Abel Vesa wrote: > > From: Wesley Cheng <wesley.cheng@oss.qualcomm.com> > > > > The Glymur USB system contains 3 USB type C ports, 1 USB multiport > > controller and a USB 2.0 only controller. This encompasses 5 SS USB QMP > > PHYs (3 combo and 2 uni) and 6 M31 eUSB2 PHYs. All controllers are SNPS > > DWC3 based, so describe them as flattened DWC3 QCOM nodes. > > > > Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com> > > Co-developed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> > > Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> > > --- > > [...] > > > + snps,dis_u2_susphy_quirk; > > + snps,dis_enblslpm_quirk; > > + snps,dis_u3_susphy_quirk; > > + snps,usb2-lpm-disable; > > Other SoCs have a list that's much longer, please consult Wesley if > this list is enough Checked with Wesley. He confirmed that this trimmed list is fine. He said he dropped the rest since they are related to the power saving features like USB2/3 LPM (l1 or u1/u2) and we don't seem need those. > > Konrad
On 1/27/26 12:41 PM, Abel Vesa wrote: > On 26-01-13 14:13:32, Konrad Dybcio wrote: >> On 1/13/26 1:33 PM, Abel Vesa wrote: >>> From: Wesley Cheng <wesley.cheng@oss.qualcomm.com> >>> >>> The Glymur USB system contains 3 USB type C ports, 1 USB multiport >>> controller and a USB 2.0 only controller. This encompasses 5 SS USB QMP >>> PHYs (3 combo and 2 uni) and 6 M31 eUSB2 PHYs. All controllers are SNPS >>> DWC3 based, so describe them as flattened DWC3 QCOM nodes. >>> >>> Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com> >>> Co-developed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> >>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> >>> --- >> >> [...] >> >>> + snps,dis_u2_susphy_quirk; >>> + snps,dis_enblslpm_quirk; >>> + snps,dis_u3_susphy_quirk; >>> + snps,usb2-lpm-disable; >> >> Other SoCs have a list that's much longer, please consult Wesley if >> this list is enough > > Checked with Wesley. He confirmed that this trimmed list is fine. > He said he dropped the rest since they are related to the power saving > features like USB2/3 LPM (l1 or u1/u2) and we don't seem need those. Is that to say that those erratas were fixed in this hardware? Low-power states of the link are no less than desired is possible.. Konrad
On 1/27/2026 3:46 AM, Konrad Dybcio wrote: > On 1/27/26 12:41 PM, Abel Vesa wrote: >> On 26-01-13 14:13:32, Konrad Dybcio wrote: >>> On 1/13/26 1:33 PM, Abel Vesa wrote: >>>> From: Wesley Cheng <wesley.cheng@oss.qualcomm.com> >>>> >>>> The Glymur USB system contains 3 USB type C ports, 1 USB multiport >>>> controller and a USB 2.0 only controller. This encompasses 5 SS USB QMP >>>> PHYs (3 combo and 2 uni) and 6 M31 eUSB2 PHYs. All controllers are SNPS >>>> DWC3 based, so describe them as flattened DWC3 QCOM nodes. >>>> >>>> Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com> >>>> Co-developed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> >>>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> >>>> --- >>> >>> [...] >>> >>>> + snps,dis_u2_susphy_quirk; >>>> + snps,dis_enblslpm_quirk; >>>> + snps,dis_u3_susphy_quirk; >>>> + snps,usb2-lpm-disable; >>> >>> Other SoCs have a list that's much longer, please consult Wesley if >>> this list is enough >> >> Checked with Wesley. He confirmed that this trimmed list is fine. >> He said he dropped the rest since they are related to the power saving >> features like USB2/3 LPM (l1 or u1/u2) and we don't seem need those. > > Is that to say that those erratas were fixed in this hardware? > > Low-power states of the link are no less than desired is possible.. > I think it was misunderstood. We should keep the same quirks as our previous targets to enable USB LPM support in certain cases. snps,hird-threshold = /bits/ 8 <0x0>; snps,usb2-gadget-lpm-disable; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; snps,is-utmi-l1-suspend; snps,usb3_lpm_capable; snps,has-lpm-erratum; tx-fifo-resize; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; snps,usb2-lpm-disable; There are some questionable ones that I'm on the fence though, which we should consider removing: snps,usb2-lpm-disable snps,usb2-gadget-lpm-disable USB L1 support is routinely being verified on our devices (in host and device modes), so if its power over performance, we should consider removing the properties to disable USB L1. (esp since we're defining the HIRD threshold as well...) Thanks Wesley Cheng
On 1/27/26 11:26 PM, Wesley Cheng wrote: > > > On 1/27/2026 3:46 AM, Konrad Dybcio wrote: >> On 1/27/26 12:41 PM, Abel Vesa wrote: >>> On 26-01-13 14:13:32, Konrad Dybcio wrote: >>>> On 1/13/26 1:33 PM, Abel Vesa wrote: >>>>> From: Wesley Cheng <wesley.cheng@oss.qualcomm.com> >>>>> >>>>> The Glymur USB system contains 3 USB type C ports, 1 USB multiport >>>>> controller and a USB 2.0 only controller. This encompasses 5 SS USB QMP >>>>> PHYs (3 combo and 2 uni) and 6 M31 eUSB2 PHYs. All controllers are SNPS >>>>> DWC3 based, so describe them as flattened DWC3 QCOM nodes. >>>>> >>>>> Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com> >>>>> Co-developed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> >>>>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> >>>>> --- >>>> >>>> [...] >>>> >>>>> + snps,dis_u2_susphy_quirk; >>>>> + snps,dis_enblslpm_quirk; >>>>> + snps,dis_u3_susphy_quirk; >>>>> + snps,usb2-lpm-disable; >>>> >>>> Other SoCs have a list that's much longer, please consult Wesley if >>>> this list is enough >>> >>> Checked with Wesley. He confirmed that this trimmed list is fine. >>> He said he dropped the rest since they are related to the power saving >>> features like USB2/3 LPM (l1 or u1/u2) and we don't seem need those. >> >> Is that to say that those erratas were fixed in this hardware? >> >> Low-power states of the link are no less than desired is possible.. >> > > I think it was misunderstood. We should keep the same quirks as our previous targets to enable USB LPM support in certain cases. > > snps,hird-threshold = /bits/ 8 <0x0>; > snps,usb2-gadget-lpm-disable; > snps,dis-u1-entry-quirk; > snps,dis-u2-entry-quirk; > snps,is-utmi-l1-suspend; > snps,usb3_lpm_capable; > snps,has-lpm-erratum; > tx-fifo-resize; > snps,dis_u2_susphy_quirk; > snps,dis_enblslpm_quirk; > snps,usb2-lpm-disable; > > There are some questionable ones that I'm on the fence though, which we should consider removing: > snps,usb2-lpm-disable > snps,usb2-gadget-lpm-disable > > USB L1 support is routinely being verified on our devices (in host and device modes), so if its power over performance, we should consider removing the properties to disable USB L1. Does the fact that we allow L1 entry impact performance itself, or is there some room for improvement in the drivers? (esp since we're defining the HIRD threshold as well...) Wouldn't HIRD threshold be related to *U*1(/2) though? I see in the list above you decalred snps,dis-u1-entry-quirk snps,dis-u2-entry-quirk which forbid them and the threshold is set to 0, so IIUC that means entry is only allowed for devices that don't ""really"" suspend Konrad
On 1/28/2026 1:53 AM, Konrad Dybcio wrote: > On 1/27/26 11:26 PM, Wesley Cheng wrote: >> >> >> On 1/27/2026 3:46 AM, Konrad Dybcio wrote: >>> On 1/27/26 12:41 PM, Abel Vesa wrote: >>>> On 26-01-13 14:13:32, Konrad Dybcio wrote: >>>>> On 1/13/26 1:33 PM, Abel Vesa wrote: >>>>>> From: Wesley Cheng <wesley.cheng@oss.qualcomm.com> >>>>>> >>>>>> The Glymur USB system contains 3 USB type C ports, 1 USB multiport >>>>>> controller and a USB 2.0 only controller. This encompasses 5 SS USB QMP >>>>>> PHYs (3 combo and 2 uni) and 6 M31 eUSB2 PHYs. All controllers are SNPS >>>>>> DWC3 based, so describe them as flattened DWC3 QCOM nodes. >>>>>> >>>>>> Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com> >>>>>> Co-developed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> >>>>>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> >>>>>> --- >>>>> >>>>> [...] >>>>> >>>>>> + snps,dis_u2_susphy_quirk; >>>>>> + snps,dis_enblslpm_quirk; >>>>>> + snps,dis_u3_susphy_quirk; >>>>>> + snps,usb2-lpm-disable; >>>>> >>>>> Other SoCs have a list that's much longer, please consult Wesley if >>>>> this list is enough >>>> >>>> Checked with Wesley. He confirmed that this trimmed list is fine. >>>> He said he dropped the rest since they are related to the power saving >>>> features like USB2/3 LPM (l1 or u1/u2) and we don't seem need those. >>> >>> Is that to say that those erratas were fixed in this hardware? >>> >>> Low-power states of the link are no less than desired is possible.. >>> >> >> I think it was misunderstood. We should keep the same quirks as our previous targets to enable USB LPM support in certain cases. >> >> snps,hird-threshold = /bits/ 8 <0x0>; >> snps,usb2-gadget-lpm-disable; >> snps,dis-u1-entry-quirk; >> snps,dis-u2-entry-quirk; >> snps,is-utmi-l1-suspend; >> snps,usb3_lpm_capable; >> snps,has-lpm-erratum; >> tx-fifo-resize; >> snps,dis_u2_susphy_quirk; >> snps,dis_enblslpm_quirk; >> snps,usb2-lpm-disable; >> >> There are some questionable ones that I'm on the fence though, which we should consider removing: >> snps,usb2-lpm-disable >> snps,usb2-gadget-lpm-disable >> >> USB L1 support is routinely being verified on our devices (in host and device modes), so if its power over performance, we should consider removing the properties to disable USB L1. > > Does the fact that we allow L1 entry impact performance itself, or is > there some room for improvement in the drivers? > Hi Konrad, Its not exactly something USB drivers have control of, as USB L1 LPM is a feature handled within the controller. The only reason why we might see some performance hit is if we have to frequently enter/exit L1 states, but if the link never make transitions into L1, then we obviously won't take a hit. > > (esp since we're defining the HIRD threshold as well...) > > Wouldn't HIRD threshold be related to *U*1(/2) though? > I see in the list above you decalred > U1/U2 are USB3 LPM states, which utilize the BESL, not HIRD. > snps,dis-u1-entry-quirk > snps,dis-u2-entry-quirk > > which forbid them > These disable them for when we are in gadget/peripheral mode, but u1/u2 while in host mode is still enabled. I'm not sure we are confident enough yet at this point to enable them (U1/U2) for device mode use cases. > and the threshold is set to 0, so IIUC that means entry is only allowed > for devices that don't ""really"" suspend > HIRD specifies the L1 exit latency that our device will require, and programming that to 0 will mean we'll require the minimum HIRD latency to exit L1. Thanks Wesley Cheng
On 1/31/26 1:11 AM, Wesley Cheng wrote: > > > On 1/28/2026 1:53 AM, Konrad Dybcio wrote: >> On 1/27/26 11:26 PM, Wesley Cheng wrote: >>> >>> >>> On 1/27/2026 3:46 AM, Konrad Dybcio wrote: >>>> On 1/27/26 12:41 PM, Abel Vesa wrote: >>>>> On 26-01-13 14:13:32, Konrad Dybcio wrote: >>>>>> On 1/13/26 1:33 PM, Abel Vesa wrote: >>>>>>> From: Wesley Cheng <wesley.cheng@oss.qualcomm.com> >>>>>>> >>>>>>> The Glymur USB system contains 3 USB type C ports, 1 USB multiport >>>>>>> controller and a USB 2.0 only controller. This encompasses 5 SS USB QMP >>>>>>> PHYs (3 combo and 2 uni) and 6 M31 eUSB2 PHYs. All controllers are SNPS >>>>>>> DWC3 based, so describe them as flattened DWC3 QCOM nodes. >>>>>>> >>>>>>> Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com> >>>>>>> Co-developed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> >>>>>>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> >>>>>>> --- >>>>>> >>>>>> [...] >>>>>> >>>>>>> + snps,dis_u2_susphy_quirk; >>>>>>> + snps,dis_enblslpm_quirk; >>>>>>> + snps,dis_u3_susphy_quirk; >>>>>>> + snps,usb2-lpm-disable; >>>>>> >>>>>> Other SoCs have a list that's much longer, please consult Wesley if >>>>>> this list is enough >>>>> >>>>> Checked with Wesley. He confirmed that this trimmed list is fine. >>>>> He said he dropped the rest since they are related to the power saving >>>>> features like USB2/3 LPM (l1 or u1/u2) and we don't seem need those. >>>> >>>> Is that to say that those erratas were fixed in this hardware? >>>> >>>> Low-power states of the link are no less than desired is possible.. >>>> >>> >>> I think it was misunderstood. We should keep the same quirks as our previous targets to enable USB LPM support in certain cases. >>> >>> snps,hird-threshold = /bits/ 8 <0x0>; >>> snps,usb2-gadget-lpm-disable; >>> snps,dis-u1-entry-quirk; >>> snps,dis-u2-entry-quirk; >>> snps,is-utmi-l1-suspend; >>> snps,usb3_lpm_capable; >>> snps,has-lpm-erratum; >>> tx-fifo-resize; >>> snps,dis_u2_susphy_quirk; >>> snps,dis_enblslpm_quirk; >>> snps,usb2-lpm-disable; >>> >>> There are some questionable ones that I'm on the fence though, which we should consider removing: >>> snps,usb2-lpm-disable >>> snps,usb2-gadget-lpm-disable >>> >>> USB L1 support is routinely being verified on our devices (in host and device modes), so if its power over performance, we should consider removing the properties to disable USB L1. >> >> Does the fact that we allow L1 entry impact performance itself, or is >> there some room for improvement in the drivers? >> > > Hi Konrad, > > Its not exactly something USB drivers have control of, as USB L1 LPM is a feature handled within the controller. The only reason why we might see some performance hit is if we have to frequently enter/exit L1 states, but if the link never make transitions into L1, then we obviously won't take a hit. > >> >> (esp since we're defining the HIRD threshold as well...) >> >> Wouldn't HIRD threshold be related to *U*1(/2) though? >> I see in the list above you decalred >> > > U1/U2 are USB3 LPM states, which utilize the BESL, not HIRD. > >> snps,dis-u1-entry-quirk >> snps,dis-u2-entry-quirk >> >> which forbid them >> > > These disable them for when we are in gadget/peripheral mode, but u1/u2 while in host mode is still enabled. I'm not sure we are confident enough yet at this point to enable them (U1/U2) for device mode use cases. > >> and the threshold is set to 0, so IIUC that means entry is only allowed >> for devices that don't ""really"" suspend >> > > HIRD specifies the L1 exit latency that our device will require, and programming that to 0 will mean we'll require the minimum HIRD latency to exit L1. Seems I had a lot of misconceptions, thanks! Konrad
On 26-01-27 14:26:47, Wesley Cheng wrote: > > > On 1/27/2026 3:46 AM, Konrad Dybcio wrote: > > On 1/27/26 12:41 PM, Abel Vesa wrote: > > > On 26-01-13 14:13:32, Konrad Dybcio wrote: > > > > On 1/13/26 1:33 PM, Abel Vesa wrote: > > > > > From: Wesley Cheng <wesley.cheng@oss.qualcomm.com> > > > > > > > > > > The Glymur USB system contains 3 USB type C ports, 1 USB multiport > > > > > controller and a USB 2.0 only controller. This encompasses 5 SS USB QMP > > > > > PHYs (3 combo and 2 uni) and 6 M31 eUSB2 PHYs. All controllers are SNPS > > > > > DWC3 based, so describe them as flattened DWC3 QCOM nodes. > > > > > > > > > > Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com> > > > > > Co-developed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> > > > > > Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> > > > > > --- > > > > > > > > [...] > > > > > > > > > + snps,dis_u2_susphy_quirk; > > > > > + snps,dis_enblslpm_quirk; > > > > > + snps,dis_u3_susphy_quirk; > > > > > + snps,usb2-lpm-disable; > > > > > > > > Other SoCs have a list that's much longer, please consult Wesley if > > > > this list is enough > > > > > > Checked with Wesley. He confirmed that this trimmed list is fine. > > > He said he dropped the rest since they are related to the power saving > > > features like USB2/3 LPM (l1 or u1/u2) and we don't seem need those. > > > > Is that to say that those erratas were fixed in this hardware? > > > > Low-power states of the link are no less than desired is possible.. > > > > I think it was misunderstood. We should keep the same quirks as our > previous targets to enable USB LPM support in certain cases. > > snps,hird-threshold = /bits/ 8 <0x0>; > snps,usb2-gadget-lpm-disable; > snps,dis-u1-entry-quirk; > snps,dis-u2-entry-quirk; > snps,is-utmi-l1-suspend; > snps,usb3_lpm_capable; > snps,has-lpm-erratum; > tx-fifo-resize; > snps,dis_u2_susphy_quirk; > snps,dis_enblslpm_quirk; > snps,usb2-lpm-disable; > > There are some questionable ones that I'm on the fence though, which we > should consider removing: > snps,usb2-lpm-disable > snps,usb2-gadget-lpm-disable > > USB L1 support is routinely being verified on our devices (in host and > device modes), so if its power over performance, we should consider removing > the properties to disable USB L1. (esp since we're defining the HIRD > threshold as well...) This should've been sorted out months ago! As part of the initial bring-up or even the initial submission here: https://lore.kernel.org/all/20250925-v3_glymur_introduction-v1-23-24b601bbecc0@oss.qualcomm.com/ Anyway, is the following list the one we should use then? snps,hird-threshold = /bits/ 8 <0x0>; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; snps,is-utmi-l1-suspend; snps,usb3_lpm_capable; snps,has-lpm-erratum; tx-fifo-resize; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; Lets decide already ...
On 1/28/2026 1:38 AM, Abel Vesa wrote: > On 26-01-27 14:26:47, Wesley Cheng wrote: >> >> >> On 1/27/2026 3:46 AM, Konrad Dybcio wrote: >>> On 1/27/26 12:41 PM, Abel Vesa wrote: >>>> On 26-01-13 14:13:32, Konrad Dybcio wrote: >>>>> On 1/13/26 1:33 PM, Abel Vesa wrote: >>>>>> From: Wesley Cheng <wesley.cheng@oss.qualcomm.com> >>>>>> >>>>>> The Glymur USB system contains 3 USB type C ports, 1 USB multiport >>>>>> controller and a USB 2.0 only controller. This encompasses 5 SS USB QMP >>>>>> PHYs (3 combo and 2 uni) and 6 M31 eUSB2 PHYs. All controllers are SNPS >>>>>> DWC3 based, so describe them as flattened DWC3 QCOM nodes. >>>>>> >>>>>> Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com> >>>>>> Co-developed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> >>>>>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> >>>>>> --- >>>>> >>>>> [...] >>>>> >>>>>> + snps,dis_u2_susphy_quirk; >>>>>> + snps,dis_enblslpm_quirk; >>>>>> + snps,dis_u3_susphy_quirk; >>>>>> + snps,usb2-lpm-disable; >>>>> >>>>> Other SoCs have a list that's much longer, please consult Wesley if >>>>> this list is enough >>>> >>>> Checked with Wesley. He confirmed that this trimmed list is fine. >>>> He said he dropped the rest since they are related to the power saving >>>> features like USB2/3 LPM (l1 or u1/u2) and we don't seem need those. >>> >>> Is that to say that those erratas were fixed in this hardware? >>> >>> Low-power states of the link are no less than desired is possible.. >>> >> >> I think it was misunderstood. We should keep the same quirks as our >> previous targets to enable USB LPM support in certain cases. >> >> snps,hird-threshold = /bits/ 8 <0x0>; >> snps,usb2-gadget-lpm-disable; >> snps,dis-u1-entry-quirk; >> snps,dis-u2-entry-quirk; >> snps,is-utmi-l1-suspend; >> snps,usb3_lpm_capable; >> snps,has-lpm-erratum; >> tx-fifo-resize; >> snps,dis_u2_susphy_quirk; >> snps,dis_enblslpm_quirk; >> snps,usb2-lpm-disable; >> >> There are some questionable ones that I'm on the fence though, which we >> should consider removing: >> snps,usb2-lpm-disable >> snps,usb2-gadget-lpm-disable >> >> USB L1 support is routinely being verified on our devices (in host and >> device modes), so if its power over performance, we should consider removing >> the properties to disable USB L1. (esp since we're defining the HIRD >> threshold as well...) > > This should've been sorted out months ago! As part of the initial bring-up or > even the initial submission here: > https://lore.kernel.org/all/20250925-v3_glymur_introduction-v1-23-24b601bbecc0@oss.qualcomm.com/ > > Anyway, is the following list the one we should use then? > > snps,hird-threshold = /bits/ 8 <0x0>; > snps,dis-u1-entry-quirk; > snps,dis-u2-entry-quirk; > snps,is-utmi-l1-suspend; > snps,usb3_lpm_capable; > snps,has-lpm-erratum; > tx-fifo-resize; > snps,dis_u2_susphy_quirk; > snps,dis_enblslpm_quirk; > This list looks good. Thanks Wesley Cheng
On 26-01-13 14:13:32, Konrad Dybcio wrote:
> On 1/13/26 1:33 PM, Abel Vesa wrote:
> > From: Wesley Cheng <wesley.cheng@oss.qualcomm.com>
> >
> > The Glymur USB system contains 3 USB type C ports, 1 USB multiport
> > controller and a USB 2.0 only controller. This encompasses 5 SS USB QMP
> > PHYs (3 combo and 2 uni) and 6 M31 eUSB2 PHYs. All controllers are SNPS
> > DWC3 based, so describe them as flattened DWC3 QCOM nodes.
> >
> > Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com>
> > Co-developed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> > Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> > ---
>
> [...]
>
> >
> > + usb_mp_hsphy0: phy@fa1000 {
> > + compatible = "qcom,glymur-m31-eusb2-phy",
> > + "qcom,sm8750-m31-eusb2-phy";
> > +
> > + reg = <0 0x00fa1000 0 0x29c>;
> > + #phy-cells = <0>;
> > +
> > + clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
> > + clock-names = "ref";
> > +
> > + resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
> > +
> > + status = "disabled";
> > + };
> > +
> > + usb_mp_hsphy1: phy@fa2000 {
> > + compatible = "qcom,glymur-m31-eusb2-phy",
> > + "qcom,sm8750-m31-eusb2-phy";
> > +
> > + reg = <0 0x00fa2000 0 0x29c>;
> > + #phy-cells = <0>;
> > +
> > + clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>;
> > + clock-names = "ref";
> > +
> > + resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
> > +
> > + status = "disabled";
> > + };
>
>
> [...]
>
> > + usb1_ss0_hsphy: phy@fd3000 {
>
> Let's not repeat the mess introduced in hamoa..
>
> Perhaps let's fall back to usb_0 etc.?
Sure. So then:
USB SS[0-2] -> usb_[0-2]
USB MP -> usb_mp
USB 2.0 (USB20S in docs) -> ?
>
> [...]
>
>
> > + snps,dis_u2_susphy_quirk;
> > + snps,dis_enblslpm_quirk;
> > + snps,dis_u3_susphy_quirk;
> > + snps,usb2-lpm-disable;
>
> Other SoCs have a list that's much longer, please consult Wesley if
> this list is enough
Will do.
On 1/26/26 3:31 PM, Abel Vesa wrote:
> On 26-01-13 14:13:32, Konrad Dybcio wrote:
>> On 1/13/26 1:33 PM, Abel Vesa wrote:
>>> From: Wesley Cheng <wesley.cheng@oss.qualcomm.com>
>>>
>>> The Glymur USB system contains 3 USB type C ports, 1 USB multiport
>>> controller and a USB 2.0 only controller. This encompasses 5 SS USB QMP
>>> PHYs (3 combo and 2 uni) and 6 M31 eUSB2 PHYs. All controllers are SNPS
>>> DWC3 based, so describe them as flattened DWC3 QCOM nodes.
>>>
>>> Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com>
>>> Co-developed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
>>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
>>> ---
>>
>> [...]
>>
>>>
>>> + usb_mp_hsphy0: phy@fa1000 {
>>> + compatible = "qcom,glymur-m31-eusb2-phy",
>>> + "qcom,sm8750-m31-eusb2-phy";
>>> +
>>> + reg = <0 0x00fa1000 0 0x29c>;
>>> + #phy-cells = <0>;
>>> +
>>> + clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
>>> + clock-names = "ref";
>>> +
>>> + resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
>>> +
>>> + status = "disabled";
>>> + };
>>> +
>>> + usb_mp_hsphy1: phy@fa2000 {
>>> + compatible = "qcom,glymur-m31-eusb2-phy",
>>> + "qcom,sm8750-m31-eusb2-phy";
>>> +
>>> + reg = <0 0x00fa2000 0 0x29c>;
>>> + #phy-cells = <0>;
>>> +
>>> + clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>;
>>> + clock-names = "ref";
>>> +
>>> + resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
>>> +
>>> + status = "disabled";
>>> + };
>>
>>
>> [...]
>>
>>> + usb1_ss0_hsphy: phy@fd3000 {
>>
>> Let's not repeat the mess introduced in hamoa..
>>
>> Perhaps let's fall back to usb_0 etc.?
>
> Sure. So then:
>
> USB SS[0-2] -> usb_[0-2]
> USB MP -> usb_mp
> USB 2.0 (USB20S in docs) -> ?
usb_hs
Konrad
On 26-01-26 15:44:45, Konrad Dybcio wrote:
> On 1/26/26 3:31 PM, Abel Vesa wrote:
> > On 26-01-13 14:13:32, Konrad Dybcio wrote:
> >> On 1/13/26 1:33 PM, Abel Vesa wrote:
> >>> From: Wesley Cheng <wesley.cheng@oss.qualcomm.com>
> >>>
> >>> The Glymur USB system contains 3 USB type C ports, 1 USB multiport
> >>> controller and a USB 2.0 only controller. This encompasses 5 SS USB QMP
> >>> PHYs (3 combo and 2 uni) and 6 M31 eUSB2 PHYs. All controllers are SNPS
> >>> DWC3 based, so describe them as flattened DWC3 QCOM nodes.
> >>>
> >>> Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com>
> >>> Co-developed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> >>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> >>> ---
> >>
> >> [...]
> >>
> >>>
> >>> + usb_mp_hsphy0: phy@fa1000 {
> >>> + compatible = "qcom,glymur-m31-eusb2-phy",
> >>> + "qcom,sm8750-m31-eusb2-phy";
> >>> +
> >>> + reg = <0 0x00fa1000 0 0x29c>;
> >>> + #phy-cells = <0>;
> >>> +
> >>> + clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
> >>> + clock-names = "ref";
> >>> +
> >>> + resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
> >>> +
> >>> + status = "disabled";
> >>> + };
> >>> +
> >>> + usb_mp_hsphy1: phy@fa2000 {
> >>> + compatible = "qcom,glymur-m31-eusb2-phy",
> >>> + "qcom,sm8750-m31-eusb2-phy";
> >>> +
> >>> + reg = <0 0x00fa2000 0 0x29c>;
> >>> + #phy-cells = <0>;
> >>> +
> >>> + clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>;
> >>> + clock-names = "ref";
> >>> +
> >>> + resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
> >>> +
> >>> + status = "disabled";
> >>> + };
> >>
> >>
> >> [...]
> >>
> >>> + usb1_ss0_hsphy: phy@fd3000 {
> >>
> >> Let's not repeat the mess introduced in hamoa..
> >>
> >> Perhaps let's fall back to usb_0 etc.?
> >
> > Sure. So then:
> >
> > USB SS[0-2] -> usb_[0-2]
> > USB MP -> usb_mp
> > USB 2.0 (USB20S in docs) -> ?
>
> usb_hs
Fair enough.
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