From: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
LM block doesn't have a hardware buffer (unlike PINGPONG and DSC
encoders). As such, don't use ephemeral max_mixer_width and
MAX_HDISPLAY_SPLIT to validate requested modes. Instead use PP and DSC
buffer widths.
While on the DPU 8.x+ supports a max linewidth of 8960 for PINGPONG_0,
there is some additional logic that needs to be added to the resource
manager to specifically try and reserve PINGPONG_0 for modes that are
greater than 5k.
Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
Tested-by: Xilin Wu <sophon@radxa.com> # qcs6490-radxa-dragon-q6a
[DB: reworked to drop catalog changes, updated commit message]
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 44 ++++++++++++++++++++++----
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 7 ++++
2 files changed, 44 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 2d06c950e814..c0eca911ff11 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -762,6 +762,22 @@ void dpu_crtc_complete_commit(struct drm_crtc *crtc)
_dpu_crtc_complete_flip(crtc);
}
+static int msm_display_get_max_pingpong_width(struct dpu_kms *dpu_kms)
+{
+ /*
+ * Note: While, for DPU 8.x+, PINGPONG_0 can technically support up to
+ * 8k resolutions, this requires reworking the RM to try to reserve
+ * PINGPONG_0 for modes greater than 5k.
+ *
+ * Once this additional logic is implemented, we can probably drop this
+ * helper and use the reserved PINGPONG's max_linewidth
+ */
+ if (dpu_kms->catalog->mdss_ver->core_major_ver < 6)
+ return DPU_1_x_MAX_PINGPONG_WIDTH;
+ else
+ return DPU_6_x_MAX_PINGPONG_WIDTH;
+}
+
static int _dpu_crtc_check_and_setup_lm_bounds(struct drm_crtc *crtc,
struct drm_crtc_state *state)
{
@@ -769,13 +785,14 @@ static int _dpu_crtc_check_and_setup_lm_bounds(struct drm_crtc *crtc,
struct drm_display_mode *adj_mode = &state->adjusted_mode;
u32 crtc_split_width = adj_mode->hdisplay / cstate->num_mixers;
struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
+ int max_pingpong_width = msm_display_get_max_pingpong_width(dpu_kms);
int i;
/* if we cannot merge 2 LMs (no 3d mux) better to fail earlier
* before even checking the width after the split
*/
if (!dpu_kms->catalog->caps->has_3d_merge &&
- adj_mode->hdisplay > dpu_kms->catalog->caps->max_mixer_width)
+ adj_mode->hdisplay > max_pingpong_width)
return -E2BIG;
for (i = 0; i < cstate->num_mixers; i++) {
@@ -787,7 +804,7 @@ static int _dpu_crtc_check_and_setup_lm_bounds(struct drm_crtc *crtc,
trace_dpu_crtc_setup_lm_bounds(DRMID(crtc), i, r);
- if (drm_rect_width(r) > dpu_kms->catalog->caps->max_mixer_width)
+ if (drm_rect_width(r) > max_pingpong_width)
return -E2BIG;
}
@@ -1318,7 +1335,6 @@ static int dpu_crtc_reassign_planes(struct drm_crtc *crtc, struct drm_crtc_state
}
#define MAX_CHANNELS_PER_CRTC PIPES_PER_PLANE
-#define MAX_HDISPLAY_SPLIT 1080
static struct msm_display_topology dpu_crtc_get_topology(
struct drm_crtc *crtc,
@@ -1328,12 +1344,25 @@ static struct msm_display_topology dpu_crtc_get_topology(
struct drm_display_mode *mode = &crtc_state->adjusted_mode;
struct msm_display_topology topology = {0};
struct drm_encoder *drm_enc;
+ u32 max_hdisplay_split;
drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc_state->encoder_mask)
dpu_encoder_update_topology(drm_enc, &topology, crtc_state->state,
&crtc_state->adjusted_mode);
topology.cwb_enabled = drm_crtc_in_clone_mode(crtc_state);
+ max_hdisplay_split = msm_display_get_max_pingpong_width(dpu_kms);
+
+ if (topology.num_dsc > 0) {
+ u32 max_dsc_encoder_width;
+
+ if (dpu_kms->catalog->mdss_ver->core_major_ver < 6)
+ max_dsc_encoder_width = DPU_1_x_MAX_DSC_ENCODER_WIDTH;
+ else
+ max_dsc_encoder_width = DPU_8_x_MAX_DSC_ENCODER_WIDTH;
+
+ max_hdisplay_split = min(max_hdisplay_split, max_dsc_encoder_width);
+ }
/*
* Datapath topology selection
@@ -1354,7 +1383,7 @@ static struct msm_display_topology dpu_crtc_get_topology(
* count both the WB and real-time phys encoders.
*
* For non-DSC CWB usecases, have the num_lm be decided by the
- * (mode->hdisplay > MAX_HDISPLAY_SPLIT) check.
+ * (mode->hdisplay > max_hdisplay_split) check.
*/
if (topology.num_intf == 2 && !topology.cwb_enabled)
@@ -1362,7 +1391,7 @@ static struct msm_display_topology dpu_crtc_get_topology(
else if (topology.num_dsc == 2)
topology.num_lm = 2;
else if (dpu_kms->catalog->caps->has_3d_merge)
- topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
+ topology.num_lm = (mode->hdisplay > max_hdisplay_split) ? 2 : 1;
else
topology.num_lm = 1;
@@ -1540,13 +1569,14 @@ static enum drm_mode_status dpu_crtc_mode_valid(struct drm_crtc *crtc,
const struct drm_display_mode *mode)
{
struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
+ int max_pingpong_width = msm_display_get_max_pingpong_width(dpu_kms);
u64 adjusted_mode_clk;
/* if there is no 3d_mux block we cannot merge LMs so we cannot
* split the large layer into 2 LMs, filter out such modes
*/
if (!dpu_kms->catalog->caps->has_3d_merge &&
- mode->hdisplay > dpu_kms->catalog->caps->max_mixer_width)
+ mode->hdisplay > max_pingpong_width)
return MODE_BAD_HVALUE;
adjusted_mode_clk = dpu_core_perf_adjusted_mode_clk(mode->clock,
@@ -1566,7 +1596,7 @@ static enum drm_mode_status dpu_crtc_mode_valid(struct drm_crtc *crtc,
* max crtc width is equal to the max mixer width * 2 and max height is 4K
*/
return drm_mode_validate_size(mode,
- 2 * dpu_kms->catalog->caps->max_mixer_width,
+ 2 * max_pingpong_width,
4096);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 4964e70610d1..3d979e856b7c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -24,6 +24,13 @@
#define DPU_MAX_IMG_WIDTH 0x3fff
#define DPU_MAX_IMG_HEIGHT 0x3fff
+#define DPU_1_x_MAX_PINGPONG_WIDTH 4096
+#define DPU_6_x_MAX_PINGPONG_WIDTH 5120
+#define DPU_8_x_MAX_PINGPONG_0_WIDTH 8960
+
+#define DPU_1_x_MAX_DSC_ENCODER_WIDTH 2048
+#define DPU_8_x_MAX_DSC_ENCODER_WIDTH 2560
+
#define CRTC_DUAL_MIXERS 2
#define MAX_XIN_COUNT 16
--
2.47.3On 1/12/2026 11:11 AM, Dmitry Baryshkov wrote: > From: Jessica Zhang <jessica.zhang@oss.qualcomm.com> > > LM block doesn't have a hardware buffer (unlike PINGPONG and DSC > encoders). As such, don't use ephemeral max_mixer_width and > MAX_HDISPLAY_SPLIT to validate requested modes. Instead use PP and DSC > buffer widths. > > While on the DPU 8.x+ supports a max linewidth of 8960 for PINGPONG_0, > there is some additional logic that needs to be added to the resource > manager to specifically try and reserve PINGPONG_0 for modes that are > greater than 5k. > > Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com> > Tested-by: Xilin Wu <sophon@radxa.com> # qcs6490-radxa-dragon-q6a > [DB: reworked to drop catalog changes, updated commit message] > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Sorry for the late reply, my colleagues are still testing the new series on qcs6490. However, this completely breaks 4K 120Hz display on SC8280XP CRD, which was previously functional (albeit with the clock check bypassed [1]). The display now shows a solid blue screen. Kernel logs indicate that only one layer mixer is being used, instead of the two that were used previously. [1] https://lore.kernel.org/all/F4CDF36128041430+0d030e3b-054c-4910-a132-72273c541948@radxa.com/ -- Best regards, Xilin Wu <sophon@radxa.com>
On Mon, Jan 12, 2026 at 03:25:05PM +0800, Xilin Wu wrote: > On 1/12/2026 11:11 AM, Dmitry Baryshkov wrote: > > From: Jessica Zhang <jessica.zhang@oss.qualcomm.com> > > > > LM block doesn't have a hardware buffer (unlike PINGPONG and DSC > > encoders). As such, don't use ephemeral max_mixer_width and > > MAX_HDISPLAY_SPLIT to validate requested modes. Instead use PP and DSC > > buffer widths. > > > > While on the DPU 8.x+ supports a max linewidth of 8960 for PINGPONG_0, > > there is some additional logic that needs to be added to the resource > > manager to specifically try and reserve PINGPONG_0 for modes that are > > greater than 5k. > > > > Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com> > > Tested-by: Xilin Wu <sophon@radxa.com> # qcs6490-radxa-dragon-q6a > > [DB: reworked to drop catalog changes, updated commit message] > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> > > Sorry for the late reply, my colleagues are still testing the new series on > qcs6490. > > However, this completely breaks 4K 120Hz display on SC8280XP CRD, which was > previously functional (albeit with the clock check bypassed [1]). The > display now shows a solid blue screen. Kernel logs indicate that only one > layer mixer is being used, instead of the two that were used previously. Could you please post debugfs/dri/0/state and debugfs/dri/0/debug/core_perf/*? > > [1] https://lore.kernel.org/all/F4CDF36128041430+0d030e3b-054c-4910-a132-72273c541948@radxa.com/ > > -- > Best regards, > Xilin Wu <sophon@radxa.com> -- With best wishes Dmitry
On 1/12/2026 3:48 PM, Dmitry Baryshkov wrote:
> On Mon, Jan 12, 2026 at 03:25:05PM +0800, Xilin Wu wrote:
>> On 1/12/2026 11:11 AM, Dmitry Baryshkov wrote:
>>> From: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
>>>
>>> LM block doesn't have a hardware buffer (unlike PINGPONG and DSC
>>> encoders). As such, don't use ephemeral max_mixer_width and
>>> MAX_HDISPLAY_SPLIT to validate requested modes. Instead use PP and DSC
>>> buffer widths.
>>>
>>> While on the DPU 8.x+ supports a max linewidth of 8960 for PINGPONG_0,
>>> there is some additional logic that needs to be added to the resource
>>> manager to specifically try and reserve PINGPONG_0 for modes that are
>>> greater than 5k.
>>>
>>> Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
>>> Tested-by: Xilin Wu <sophon@radxa.com> # qcs6490-radxa-dragon-q6a
>>> [DB: reworked to drop catalog changes, updated commit message]
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
>>
>> Sorry for the late reply, my colleagues are still testing the new series on
>> qcs6490.
>>
>> However, this completely breaks 4K 120Hz display on SC8280XP CRD, which was
>> previously functional (albeit with the clock check bypassed [1]). The
>> display now shows a solid blue screen. Kernel logs indicate that only one
>> layer mixer is being used, instead of the two that were used previously.
>
> Could you please post debugfs/dri/0/state and debugfs/dri/0/debug/core_perf/*?
>
Sure, this is when the display is working:
$ cat /sys/kernel/debug/dri/ae01000.display-controller/state
plane[36]: plane-0
crtc=crtc-0
fb=89
allocated by = kwin_wayland
refcount=2
format=AR30 little-endian (0x30335241)
modifier=0x500000000000001
size=3840x2160
layers:
size[0]=3840x2160
pitch[0]=15360
offset[0]=0
obj[0]:
name=0
refcount=5
start=00105bee
size=33554432
imported=no
crtc-pos=3840x2160+0+0
src-pos=3840.000000x2160.000000+0.000000+0.000000
rotation=1
normalized-zpos=0
color-encoding=ITU-R BT.601 YCbCr
color-range=YCbCr limited range
color_mgmt_changed=0
stage=1
sspp[0]=sspp_8
multirect_mode[0]=parallel
multirect_index[0]=rect_0
src[0]=1920x2160+0+0
dst[0]=1920x2160+0+0
sspp[1]=sspp_8
multirect_mode[1]=parallel
multirect_index[1]=rect_1
src[1]=1920x2160+1920+0
dst[1]=1920x2160+1920+0
plane[42]: plane-1
crtc=(null)
fb=0
crtc-pos=0x0+0+0
src-pos=0.000000x0.000000+0.000000+0.000000
rotation=1
normalized-zpos=0
color-encoding=ITU-R BT.601 YCbCr
color-range=YCbCr limited range
color_mgmt_changed=0
stage=0
plane[48]: plane-2
crtc=(null)
fb=0
crtc-pos=0x0+0+0
src-pos=0.000000x0.000000+0.000000+0.000000
rotation=1
normalized-zpos=0
color-encoding=ITU-R BT.601 YCbCr
color-range=YCbCr limited range
color_mgmt_changed=0
stage=0
plane[54]: plane-3
crtc=(null)
fb=0
crtc-pos=0x0+0+0
src-pos=0.000000x0.000000+0.000000+0.000000
rotation=1
normalized-zpos=0
color-encoding=ITU-R BT.601 YCbCr
color-range=YCbCr limited range
color_mgmt_changed=0
stage=0
plane[60]: plane-4
crtc=(null)
fb=0
crtc-pos=0x0+0+0
src-pos=0.000000x0.000000+0.000000+0.000000
rotation=1
normalized-zpos=0
color-encoding=ITU-R BT.601 YCbCr
color-range=YCbCr limited range
color_mgmt_changed=0
stage=0
plane[66]: plane-5
crtc=(null)
fb=0
crtc-pos=0x0+0+0
src-pos=0.000000x0.000000+0.000000+0.000000
rotation=1
normalized-zpos=0
color-encoding=ITU-R BT.601 YCbCr
color-range=YCbCr limited range
color_mgmt_changed=0
stage=0
plane[72]: plane-6
crtc=crtc-0
fb=93
allocated by = kwin_wayland
refcount=2
format=AB24 little-endian (0x34324241)
modifier=0x500000000000001
size=512x512
layers:
size[0]=512x512
pitch[0]=2048
offset[0]=0
obj[0]:
name=0
refcount=5
start=0010f8ca
size=1310720
imported=no
crtc-pos=512x512+1913+1073
src-pos=512.000000x512.000000+0.000000+0.000000
rotation=1
normalized-zpos=1
color-encoding=ITU-R BT.601 YCbCr
color-range=YCbCr limited range
color_mgmt_changed=0
stage=2
sspp[0]=sspp_9
multirect_mode[0]=none
multirect_index[0]=solo
src[0]=512x512+0+0
dst[0]=512x512+1913+1073
plane[78]: plane-7
crtc=(null)
fb=0
crtc-pos=0x0+0+0
src-pos=0.000000x0.000000+0.000000+0.000000
rotation=1
normalized-zpos=0
color-encoding=ITU-R BT.601 YCbCr
color-range=YCbCr limited range
color_mgmt_changed=0
stage=0
crtc[84]: crtc-0
enable=1
active=1
self_refresh_active=0
planes_changed=1
mode_changed=0
active_changed=0
connectors_changed=0
color_mgmt_changed=0
plane_mask=41
connector_mask=1
encoder_mask=1
mode: "3840x2160": 120 1188000 3840 4016 4104 4400 2160 2168
2178 2250 0x40 0x5
lm[0]=0
ctl[0]=0
lm[1]=1
ctl[1]=0
connector[34]: DP-1
crtc=crtc-0
self_refresh_aware=0
interlace_allowed=0
ycbcr_420_allowed=1
max_requested_bpc=0
colorspace=Default
resource mapping:
pingpong=84 84 # # # # - - - - - - -
mixer=84 84 # # # # - -
ctl=84 # # # # #
dspp=# # # #
dsc=# # # # # # - -
cdm=#
sspp=# # # # - - - - 84 84 # # - - - -
cwb=- - - -
And this is when this series is applied:
$ cat /sys/kernel/debug/dri/ae01000.display-controller/state
plane[36]: plane-0
crtc=crtc-0
fb=89
allocated by = kwin_wayland
refcount=2
format=AR30 little-endian (0x30335241)
modifier=0x500000000000001
size=3840x2160
layers:
size[0]=3840x2160
pitch[0]=15360
offset[0]=0
obj[0]:
name=0
refcount=5
start=00105bee
size=33554432
imported=no
crtc-pos=3840x2160+0+0
src-pos=3840.000000x2160.000000+0.000000+0.000000
rotation=1
normalized-zpos=0
color-encoding=ITU-R BT.601 YCbCr
color-range=YCbCr limited range
color_mgmt_changed=0
stage=1
sspp[0]=sspp_8
multirect_mode[0]=parallel
multirect_index[0]=rect_0
src[0]=1920x2160+0+0
dst[0]=1920x2160+0+0
sspp[1]=sspp_8
multirect_mode[1]=parallel
multirect_index[1]=rect_1
src[1]=1920x2160+1920+0
dst[1]=1920x2160+1920+0
plane[42]: plane-1
crtc=(null)
fb=0
crtc-pos=0x0+0+0
src-pos=0.000000x0.000000+0.000000+0.000000
rotation=1
normalized-zpos=0
color-encoding=ITU-R BT.601 YCbCr
color-range=YCbCr limited range
color_mgmt_changed=0
stage=0
plane[48]: plane-2
crtc=(null)
fb=0
crtc-pos=0x0+0+0
src-pos=0.000000x0.000000+0.000000+0.000000
rotation=1
normalized-zpos=0
color-encoding=ITU-R BT.601 YCbCr
color-range=YCbCr limited range
color_mgmt_changed=0
stage=0
plane[54]: plane-3
crtc=(null)
fb=0
crtc-pos=0x0+0+0
src-pos=0.000000x0.000000+0.000000+0.000000
rotation=1
normalized-zpos=0
color-encoding=ITU-R BT.601 YCbCr
color-range=YCbCr limited range
color_mgmt_changed=0
stage=0
plane[60]: plane-4
crtc=(null)
fb=0
crtc-pos=0x0+0+0
src-pos=0.000000x0.000000+0.000000+0.000000
rotation=1
normalized-zpos=0
color-encoding=ITU-R BT.601 YCbCr
color-range=YCbCr limited range
color_mgmt_changed=0
stage=0
plane[66]: plane-5
crtc=(null)
fb=0
crtc-pos=0x0+0+0
src-pos=0.000000x0.000000+0.000000+0.000000
rotation=1
normalized-zpos=0
color-encoding=ITU-R BT.601 YCbCr
color-range=YCbCr limited range
color_mgmt_changed=0
stage=0
plane[72]: plane-6
crtc=crtc-0
fb=92
allocated by = kwin_wayland
refcount=2
format=AR24 little-endian (0x34325241)
modifier=0x500000000000001
size=512x512
layers:
size[0]=512x512
pitch[0]=2048
offset[0]=0
obj[0]:
name=0
refcount=5
start=0011cf86
size=1310720
imported=no
crtc-pos=512x512+3833+2107
src-pos=512.000000x512.000000+0.000000+0.000000
rotation=1
normalized-zpos=1
color-encoding=ITU-R BT.601 YCbCr
color-range=YCbCr limited range
color_mgmt_changed=0
stage=2
sspp[0]=sspp_9
multirect_mode[0]=none
multirect_index[0]=solo
src[0]=7x53+0+0
dst[0]=7x53+3833+2107
plane[78]: plane-7
crtc=(null)
fb=0
crtc-pos=0x0+0+0
src-pos=0.000000x0.000000+0.000000+0.000000
rotation=1
normalized-zpos=0
color-encoding=ITU-R BT.601 YCbCr
color-range=YCbCr limited range
color_mgmt_changed=0
stage=0
crtc[84]: crtc-0
enable=1
active=1
self_refresh_active=0
planes_changed=1
mode_changed=0
active_changed=0
connectors_changed=0
color_mgmt_changed=0
plane_mask=41
connector_mask=1
encoder_mask=1
mode: "3840x2160": 120 1188000 3840 4016 4104 4400 2160 2168
2178 2250 0x40 0x5
lm[0]=0
ctl[0]=0
connector[34]: DP-1
crtc=crtc-0
self_refresh_aware=0
interlace_allowed=0
ycbcr_420_allowed=1
max_requested_bpc=0
colorspace=Default
resource mapping:
pingpong=84 # # # # # - - - - - - -
mixer=84 # # # # # - -
ctl=84 # # # # #
dspp=# # # #
dsc=# # # # # # - -
cdm=#
sspp=# # # # - - - - 84 84 # # - - - -
cwb=- - - -
The values from core_perf are exactly the same:
$ cat /sys/kernel/debug/dri/ae01000.display-controller/debug/core_perf/*
600000000
0
0
0
0
13600000
18200000
600000000
2500000
800000
0
mode 0
>>
>> [1] https://lore.kernel.org/all/F4CDF36128041430+0d030e3b-054c-4910-a132-72273c541948@radxa.com/
>>
>> --
>> Best regards,
>> Xilin Wu <sophon@radxa.com>
>
--
Best regards,
Xilin Wu <sophon@radxa.com>
On Mon, 12 Jan 2026 at 09:25, Xilin Wu <sophon@radxa.com> wrote: > > On 1/12/2026 11:11 AM, Dmitry Baryshkov wrote: > > From: Jessica Zhang <jessica.zhang@oss.qualcomm.com> > > > > LM block doesn't have a hardware buffer (unlike PINGPONG and DSC > > encoders). As such, don't use ephemeral max_mixer_width and > > MAX_HDISPLAY_SPLIT to validate requested modes. Instead use PP and DSC > > buffer widths. > > > > While on the DPU 8.x+ supports a max linewidth of 8960 for PINGPONG_0, > > there is some additional logic that needs to be added to the resource > > manager to specifically try and reserve PINGPONG_0 for modes that are > > greater than 5k. > > > > Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com> > > Tested-by: Xilin Wu <sophon@radxa.com> # qcs6490-radxa-dragon-q6a > > [DB: reworked to drop catalog changes, updated commit message] > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> > > Sorry for the late reply, my colleagues are still testing the new series > on qcs6490. > > However, this completely breaks 4K 120Hz display on SC8280XP CRD, which > was previously functional (albeit with the clock check bypassed [1]). > The display now shows a solid blue screen. Kernel logs indicate that > only one layer mixer is being used, instead of the two that were used > previously. Interesting, thanks. > > [1] > https://lore.kernel.org/all/F4CDF36128041430+0d030e3b-054c-4910-a132-72273c541948@radxa.com/ > > -- > Best regards, > Xilin Wu <sophon@radxa.com> -- With best wishes Dmitry
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