Add pin control support for Low Power Audio SubSystem (LPASS)
of Qualcomm SA8775P SoC.
Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
---
drivers/pinctrl/qcom/Kconfig | 10 +
drivers/pinctrl/qcom/Makefile | 1 +
.../pinctrl/qcom/pinctrl-sa8775p-lpass-lpi.c | 216 ++++++++++++++++++
3 files changed, 227 insertions(+)
create mode 100644 drivers/pinctrl/qcom/pinctrl-sa8775p-lpass-lpi.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index c480e8b78503..bb1524243906 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -60,6 +60,16 @@ config PINCTRL_LPASS_LPI
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
(Low Power Island) found on the Qualcomm Technologies Inc SoCs.
+config PINCTRL_SA8775P_LPASS_LPI
+ tristate "Qualcomm Technologies Inc SA8775P LPASS LPI pin controller driver"
+ depends on ARM64 || COMPILE_TEST
+ depends on PINCTRL_LPASS_LPI
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
+ (Low Power Island) found on the Qualcomm Technologies Inc SA8775P
+ platform.
+
config PINCTRL_SC7280_LPASS_LPI
tristate "Qualcomm Technologies Inc SC7280 LPASS LPI pin controller driver"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 748b17a77b2c..b2a23a824846 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o
obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o
obj-$(CONFIG_PINCTRL_QDU1000) += pinctrl-qdu1000.o
obj-$(CONFIG_PINCTRL_SA8775P) += pinctrl-sa8775p.o
+obj-$(CONFIG_PINCTRL_SA8775P_LPASS_LPI) += pinctrl-sa8775p-lpass-lpi.o
obj-$(CONFIG_PINCTRL_SAR2130P) += pinctrl-sar2130p.o
obj-$(CONFIG_PINCTRL_SC7180) += pinctrl-sc7180.o
obj-$(CONFIG_PINCTRL_SC7280) += pinctrl-sc7280.o
diff --git a/drivers/pinctrl/qcom/pinctrl-sa8775p-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sa8775p-lpass-lpi.c
new file mode 100644
index 000000000000..4579a079f7c6
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sa8775p-lpass-lpi.c
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/gpio/driver.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-lpass-lpi.h"
+
+enum lpass_lpi_functions {
+ LPI_MUX_dmic1_clk,
+ LPI_MUX_dmic1_data,
+ LPI_MUX_dmic2_clk,
+ LPI_MUX_dmic2_data,
+ LPI_MUX_dmic3_clk,
+ LPI_MUX_dmic3_data,
+ LPI_MUX_dmic4_clk,
+ LPI_MUX_dmic4_data,
+ LPI_MUX_i2s1_clk,
+ LPI_MUX_i2s1_data,
+ LPI_MUX_i2s1_ws,
+ LPI_MUX_i2s2_clk,
+ LPI_MUX_i2s2_data,
+ LPI_MUX_i2s2_ws,
+ LPI_MUX_i2s3_clk,
+ LPI_MUX_i2s3_data,
+ LPI_MUX_i2s3_ws,
+ LPI_MUX_i2s4_clk,
+ LPI_MUX_i2s4_data,
+ LPI_MUX_i2s4_ws,
+ LPI_MUX_qua_mi2s_data,
+ LPI_MUX_qua_mi2s_sclk,
+ LPI_MUX_qua_mi2s_ws,
+ LPI_MUX_slimbus_clk,
+ LPI_MUX_slimbus_data,
+ LPI_MUX_swr_rx_clk,
+ LPI_MUX_swr_rx_data,
+ LPI_MUX_swr_tx_clk,
+ LPI_MUX_swr_tx_data,
+ LPI_MUX_wsa_swr_clk,
+ LPI_MUX_wsa_swr_data,
+ LPI_MUX_wsa2_swr_clk,
+ LPI_MUX_wsa2_swr_data,
+ LPI_MUX_ext_mclk1_a,
+ LPI_MUX_ext_mclk1_b,
+ LPI_MUX_ext_mclk1_c,
+ LPI_MUX_ext_mclk1_d,
+ LPI_MUX_ext_mclk1_e,
+ LPI_MUX_gpio,
+ LPI_MUX__,
+};
+
+static const struct pinctrl_pin_desc sa8775p_lpi_pins[] = {
+ PINCTRL_PIN(0, "gpio0"),
+ PINCTRL_PIN(1, "gpio1"),
+ PINCTRL_PIN(2, "gpio2"),
+ PINCTRL_PIN(3, "gpio3"),
+ PINCTRL_PIN(4, "gpio4"),
+ PINCTRL_PIN(5, "gpio5"),
+ PINCTRL_PIN(6, "gpio6"),
+ PINCTRL_PIN(7, "gpio7"),
+ PINCTRL_PIN(8, "gpio8"),
+ PINCTRL_PIN(9, "gpio9"),
+ PINCTRL_PIN(10, "gpio10"),
+ PINCTRL_PIN(11, "gpio11"),
+ PINCTRL_PIN(12, "gpio12"),
+ PINCTRL_PIN(13, "gpio13"),
+ PINCTRL_PIN(14, "gpio14"),
+ PINCTRL_PIN(15, "gpio15"),
+ PINCTRL_PIN(16, "gpio16"),
+ PINCTRL_PIN(17, "gpio17"),
+ PINCTRL_PIN(18, "gpio18"),
+ PINCTRL_PIN(19, "gpio19"),
+ PINCTRL_PIN(20, "gpio20"),
+ PINCTRL_PIN(21, "gpio21"),
+ PINCTRL_PIN(22, "gpio22"),
+};
+
+static const char * const dmic1_clk_groups[] = { "gpio6" };
+static const char * const dmic1_data_groups[] = { "gpio7" };
+static const char * const dmic2_clk_groups[] = { "gpio8" };
+static const char * const dmic2_data_groups[] = { "gpio9" };
+static const char * const dmic3_clk_groups[] = { "gpio12" };
+static const char * const dmic3_data_groups[] = { "gpio13" };
+static const char * const dmic4_clk_groups[] = { "gpio17" };
+static const char * const dmic4_data_groups[] = { "gpio18" };
+static const char * const i2s1_clk_groups[] = { "gpio6" };
+static const char * const i2s1_ws_groups[] = { "gpio7" };
+static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
+static const char * const i2s2_clk_groups[] = { "gpio10" };
+static const char * const i2s2_ws_groups[] = { "gpio11" };
+static const char * const i2s2_data_groups[] = { "gpio15", "gpio16" };
+static const char * const i2s3_clk_groups[] = { "gpio19" };
+static const char * const i2s3_ws_groups[] = { "gpio20" };
+static const char * const i2s3_data_groups[] = { "gpio21", "gpio22" };
+static const char * const i2s4_clk_groups[] = { "gpio12" };
+static const char * const i2s4_ws_groups[] = { "gpio13" };
+static const char * const i2s4_data_groups[] = { "gpio17", "gpio18" };
+static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
+static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
+static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4", "gpio5" };
+static const char * const slimbus_clk_groups[] = { "gpio19"};
+static const char * const slimbus_data_groups[] = { "gpio20"};
+static const char * const swr_tx_clk_groups[] = { "gpio0" };
+static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" };
+static const char * const swr_rx_clk_groups[] = { "gpio3" };
+static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
+static const char * const wsa_swr_clk_groups[] = { "gpio10" };
+static const char * const wsa_swr_data_groups[] = { "gpio11" };
+static const char * const wsa2_swr_clk_groups[] = { "gpio15" };
+static const char * const wsa2_swr_data_groups[] = { "gpio16" };
+static const char * const ext_mclk1_c_groups[] = { "gpio5" };
+static const char * const ext_mclk1_b_groups[] = { "gpio9" };
+static const char * const ext_mclk1_a_groups[] = { "gpio13" };
+static const char * const ext_mclk1_d_groups[] = { "gpio14" };
+static const char * const ext_mclk1_e_groups[] = { "gpio22" };
+
+static const struct lpi_pingroup sa8775p_groups[] = {
+ LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
+ LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
+ LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
+ LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
+ LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
+ LPI_PINGROUP(5, 12, swr_rx_data, ext_mclk1_c, qua_mi2s_data, _),
+ LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _),
+ LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _),
+ LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _),
+ LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, ext_mclk1_b, _),
+ LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
+ LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
+ LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s4_clk, _, _),
+ LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s4_ws, ext_mclk1_a, _),
+ LPI_PINGROUP(14, 6, swr_tx_data, ext_mclk1_d, _, _),
+ LPI_PINGROUP(15, 20, i2s2_data, wsa2_swr_clk, _, _),
+ LPI_PINGROUP(16, 22, i2s2_data, wsa2_swr_data, _, _),
+ LPI_PINGROUP(17, LPI_NO_SLEW, dmic4_clk, i2s4_data, _, _),
+ LPI_PINGROUP(18, LPI_NO_SLEW, dmic4_data, i2s4_data, _, _),
+ LPI_PINGROUP(19, LPI_NO_SLEW, i2s3_clk, slimbus_clk, _, _),
+ LPI_PINGROUP(20, LPI_NO_SLEW, i2s3_ws, slimbus_data, _, _),
+ LPI_PINGROUP(21, LPI_NO_SLEW, i2s3_data, _, _, _),
+ LPI_PINGROUP(22, LPI_NO_SLEW, i2s3_data, ext_mclk1_e, _, _),
+};
+
+static const struct lpi_function sa8775p_functions[] = {
+ LPI_FUNCTION(dmic1_clk),
+ LPI_FUNCTION(dmic1_data),
+ LPI_FUNCTION(dmic2_clk),
+ LPI_FUNCTION(dmic2_data),
+ LPI_FUNCTION(dmic3_clk),
+ LPI_FUNCTION(dmic3_data),
+ LPI_FUNCTION(dmic4_clk),
+ LPI_FUNCTION(dmic4_data),
+ LPI_FUNCTION(i2s1_clk),
+ LPI_FUNCTION(i2s1_data),
+ LPI_FUNCTION(i2s1_ws),
+ LPI_FUNCTION(i2s2_clk),
+ LPI_FUNCTION(i2s2_data),
+ LPI_FUNCTION(i2s2_ws),
+ LPI_FUNCTION(i2s3_clk),
+ LPI_FUNCTION(i2s3_data),
+ LPI_FUNCTION(i2s3_ws),
+ LPI_FUNCTION(i2s4_clk),
+ LPI_FUNCTION(i2s4_data),
+ LPI_FUNCTION(i2s4_ws),
+ LPI_FUNCTION(qua_mi2s_data),
+ LPI_FUNCTION(qua_mi2s_sclk),
+ LPI_FUNCTION(qua_mi2s_ws),
+ LPI_FUNCTION(slimbus_clk),
+ LPI_FUNCTION(slimbus_data),
+ LPI_FUNCTION(swr_rx_clk),
+ LPI_FUNCTION(swr_rx_data),
+ LPI_FUNCTION(swr_tx_clk),
+ LPI_FUNCTION(swr_tx_data),
+ LPI_FUNCTION(wsa_swr_clk),
+ LPI_FUNCTION(wsa_swr_data),
+ LPI_FUNCTION(wsa2_swr_clk),
+ LPI_FUNCTION(wsa2_swr_data),
+ LPI_FUNCTION(ext_mclk1_a),
+ LPI_FUNCTION(ext_mclk1_b),
+ LPI_FUNCTION(ext_mclk1_c),
+ LPI_FUNCTION(ext_mclk1_d),
+ LPI_FUNCTION(ext_mclk1_e),
+};
+
+static const struct lpi_pinctrl_variant_data sa8775p_lpi_data = {
+ .pins = sa8775p_lpi_pins,
+ .npins = ARRAY_SIZE(sa8775p_lpi_pins),
+ .groups = sa8775p_groups,
+ .ngroups = ARRAY_SIZE(sa8775p_groups),
+ .functions = sa8775p_functions,
+ .nfunctions = ARRAY_SIZE(sa8775p_functions),
+};
+
+static const struct of_device_id lpi_pinctrl_of_match[] = {
+ {
+ .compatible = "qcom,sa8775p-lpass-lpi-pinctrl",
+ .data = &sa8775p_lpi_data,
+ },
+ { }
+};
+MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
+
+static struct platform_driver lpi_pinctrl_driver = {
+ .driver = {
+ .name = "qcom-sa8775p-lpass-lpi-pinctrl",
+ .of_match_table = lpi_pinctrl_of_match,
+ },
+ .probe = lpi_pinctrl_probe,
+ .remove = lpi_pinctrl_remove,
+};
+
+module_platform_driver(lpi_pinctrl_driver);
+MODULE_DESCRIPTION("Qualcomm SA8775P LPI GPIO pin control driver");
+MODULE_LICENSE("GPL");
--
2.34.1On 1/7/26 8:20 PM, Mohammad Rafi Shaik wrote: > Add pin control support for Low Power Audio SubSystem (LPASS) > of Qualcomm SA8775P SoC. > > Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Konrad
On Thu, Jan 08, 2026 at 12:50:07AM +0530, Mohammad Rafi Shaik wrote:
> Add pin control support for Low Power Audio SubSystem (LPASS)
> of Qualcomm SA8775P SoC.
>
> Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
> ---
> drivers/pinctrl/qcom/Kconfig | 10 +
> drivers/pinctrl/qcom/Makefile | 1 +
> .../pinctrl/qcom/pinctrl-sa8775p-lpass-lpi.c | 216 ++++++++++++++++++
> 3 files changed, 227 insertions(+)
> create mode 100644 drivers/pinctrl/qcom/pinctrl-sa8775p-lpass-lpi.c
>
> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
> index c480e8b78503..bb1524243906 100644
> --- a/drivers/pinctrl/qcom/Kconfig
> +++ b/drivers/pinctrl/qcom/Kconfig
> @@ -60,6 +60,16 @@ config PINCTRL_LPASS_LPI
> Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
> (Low Power Island) found on the Qualcomm Technologies Inc SoCs.
>
> +config PINCTRL_SA8775P_LPASS_LPI
> + tristate "Qualcomm Technologies Inc SA8775P LPASS LPI pin controller driver"
> + depends on ARM64 || COMPILE_TEST
> + depends on PINCTRL_LPASS_LPI
> + help
> + This is the pinctrl, pinmux, pinconf and gpiolib driver for the
> + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
> + (Low Power Island) found on the Qualcomm Technologies Inc SA8775P
> + platform.
> +
> config PINCTRL_SC7280_LPASS_LPI
> tristate "Qualcomm Technologies Inc SC7280 LPASS LPI pin controller driver"
> depends on ARM64 || COMPILE_TEST
> diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
> index 748b17a77b2c..b2a23a824846 100644
> --- a/drivers/pinctrl/qcom/Makefile
> +++ b/drivers/pinctrl/qcom/Makefile
> @@ -39,6 +39,7 @@ obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o
> obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o
> obj-$(CONFIG_PINCTRL_QDU1000) += pinctrl-qdu1000.o
> obj-$(CONFIG_PINCTRL_SA8775P) += pinctrl-sa8775p.o
> +obj-$(CONFIG_PINCTRL_SA8775P_LPASS_LPI) += pinctrl-sa8775p-lpass-lpi.o
> obj-$(CONFIG_PINCTRL_SAR2130P) += pinctrl-sar2130p.o
> obj-$(CONFIG_PINCTRL_SC7180) += pinctrl-sc7180.o
> obj-$(CONFIG_PINCTRL_SC7280) += pinctrl-sc7280.o
> diff --git a/drivers/pinctrl/qcom/pinctrl-sa8775p-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sa8775p-lpass-lpi.c
> new file mode 100644
> index 000000000000..4579a079f7c6
> --- /dev/null
> +++ b/drivers/pinctrl/qcom/pinctrl-sa8775p-lpass-lpi.c
> @@ -0,0 +1,216 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#include <linux/gpio/driver.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +
> +#include "pinctrl-lpass-lpi.h"
> +
> +enum lpass_lpi_functions {
> + LPI_MUX_dmic1_clk,
> + LPI_MUX_dmic1_data,
> + LPI_MUX_dmic2_clk,
> + LPI_MUX_dmic2_data,
> + LPI_MUX_dmic3_clk,
> + LPI_MUX_dmic3_data,
> + LPI_MUX_dmic4_clk,
> + LPI_MUX_dmic4_data,
> + LPI_MUX_i2s1_clk,
> + LPI_MUX_i2s1_data,
> + LPI_MUX_i2s1_ws,
> + LPI_MUX_i2s2_clk,
> + LPI_MUX_i2s2_data,
> + LPI_MUX_i2s2_ws,
> + LPI_MUX_i2s3_clk,
> + LPI_MUX_i2s3_data,
> + LPI_MUX_i2s3_ws,
> + LPI_MUX_i2s4_clk,
> + LPI_MUX_i2s4_data,
> + LPI_MUX_i2s4_ws,
> + LPI_MUX_qua_mi2s_data,
> + LPI_MUX_qua_mi2s_sclk,
> + LPI_MUX_qua_mi2s_ws,
> + LPI_MUX_slimbus_clk,
> + LPI_MUX_slimbus_data,
> + LPI_MUX_swr_rx_clk,
> + LPI_MUX_swr_rx_data,
> + LPI_MUX_swr_tx_clk,
> + LPI_MUX_swr_tx_data,
> + LPI_MUX_wsa_swr_clk,
> + LPI_MUX_wsa_swr_data,
> + LPI_MUX_wsa2_swr_clk,
> + LPI_MUX_wsa2_swr_data,
> + LPI_MUX_ext_mclk1_a,
> + LPI_MUX_ext_mclk1_b,
> + LPI_MUX_ext_mclk1_c,
> + LPI_MUX_ext_mclk1_d,
> + LPI_MUX_ext_mclk1_e,
> + LPI_MUX_gpio,
> + LPI_MUX__,
> +};
Isn't this entire driver exactly the same as sm8450?
Best regards,
Krzysztof
On 1/8/2026 2:34 PM, Krzysztof Kozlowski wrote:
> On Thu, Jan 08, 2026 at 12:50:07AM +0530, Mohammad Rafi Shaik wrote:
>> Add pin control support for Low Power Audio SubSystem (LPASS)
>> of Qualcomm SA8775P SoC.
>>
>> Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
>> ---
>> drivers/pinctrl/qcom/Kconfig | 10 +
>> drivers/pinctrl/qcom/Makefile | 1 +
>> .../pinctrl/qcom/pinctrl-sa8775p-lpass-lpi.c | 216 ++++++++++++++++++
>> 3 files changed, 227 insertions(+)
>> create mode 100644 drivers/pinctrl/qcom/pinctrl-sa8775p-lpass-lpi.c
>>
>> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
>> index c480e8b78503..bb1524243906 100644
>> --- a/drivers/pinctrl/qcom/Kconfig
>> +++ b/drivers/pinctrl/qcom/Kconfig
>> @@ -60,6 +60,16 @@ config PINCTRL_LPASS_LPI
>> Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
>> (Low Power Island) found on the Qualcomm Technologies Inc SoCs.
>>
>> +config PINCTRL_SA8775P_LPASS_LPI
>> + tristate "Qualcomm Technologies Inc SA8775P LPASS LPI pin controller driver"
>> + depends on ARM64 || COMPILE_TEST
>> + depends on PINCTRL_LPASS_LPI
>> + help
>> + This is the pinctrl, pinmux, pinconf and gpiolib driver for the
>> + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
>> + (Low Power Island) found on the Qualcomm Technologies Inc SA8775P
>> + platform.
>> +
>> config PINCTRL_SC7280_LPASS_LPI
>> tristate "Qualcomm Technologies Inc SC7280 LPASS LPI pin controller driver"
>> depends on ARM64 || COMPILE_TEST
>> diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
>> index 748b17a77b2c..b2a23a824846 100644
>> --- a/drivers/pinctrl/qcom/Makefile
>> +++ b/drivers/pinctrl/qcom/Makefile
>> @@ -39,6 +39,7 @@ obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o
>> obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o
>> obj-$(CONFIG_PINCTRL_QDU1000) += pinctrl-qdu1000.o
>> obj-$(CONFIG_PINCTRL_SA8775P) += pinctrl-sa8775p.o
>> +obj-$(CONFIG_PINCTRL_SA8775P_LPASS_LPI) += pinctrl-sa8775p-lpass-lpi.o
>> obj-$(CONFIG_PINCTRL_SAR2130P) += pinctrl-sar2130p.o
>> obj-$(CONFIG_PINCTRL_SC7180) += pinctrl-sc7180.o
>> obj-$(CONFIG_PINCTRL_SC7280) += pinctrl-sc7280.o
>> diff --git a/drivers/pinctrl/qcom/pinctrl-sa8775p-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sa8775p-lpass-lpi.c
>> new file mode 100644
>> index 000000000000..4579a079f7c6
>> --- /dev/null
>> +++ b/drivers/pinctrl/qcom/pinctrl-sa8775p-lpass-lpi.c
>> @@ -0,0 +1,216 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
>> + */
>> +
>> +#include <linux/gpio/driver.h>
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +
>> +#include "pinctrl-lpass-lpi.h"
>> +
>> +enum lpass_lpi_functions {
>> + LPI_MUX_dmic1_clk,
>> + LPI_MUX_dmic1_data,
>> + LPI_MUX_dmic2_clk,
>> + LPI_MUX_dmic2_data,
>> + LPI_MUX_dmic3_clk,
>> + LPI_MUX_dmic3_data,
>> + LPI_MUX_dmic4_clk,
>> + LPI_MUX_dmic4_data,
>> + LPI_MUX_i2s1_clk,
>> + LPI_MUX_i2s1_data,
>> + LPI_MUX_i2s1_ws,
>> + LPI_MUX_i2s2_clk,
>> + LPI_MUX_i2s2_data,
>> + LPI_MUX_i2s2_ws,
>> + LPI_MUX_i2s3_clk,
>> + LPI_MUX_i2s3_data,
>> + LPI_MUX_i2s3_ws,
>> + LPI_MUX_i2s4_clk,
>> + LPI_MUX_i2s4_data,
>> + LPI_MUX_i2s4_ws,
>> + LPI_MUX_qua_mi2s_data,
>> + LPI_MUX_qua_mi2s_sclk,
>> + LPI_MUX_qua_mi2s_ws,
>> + LPI_MUX_slimbus_clk,
>> + LPI_MUX_slimbus_data,
>> + LPI_MUX_swr_rx_clk,
>> + LPI_MUX_swr_rx_data,
>> + LPI_MUX_swr_tx_clk,
>> + LPI_MUX_swr_tx_data,
>> + LPI_MUX_wsa_swr_clk,
>> + LPI_MUX_wsa_swr_data,
>> + LPI_MUX_wsa2_swr_clk,
>> + LPI_MUX_wsa2_swr_data,
>> + LPI_MUX_ext_mclk1_a,
>> + LPI_MUX_ext_mclk1_b,
>> + LPI_MUX_ext_mclk1_c,
>> + LPI_MUX_ext_mclk1_d,
>> + LPI_MUX_ext_mclk1_e,
>> + LPI_MUX_gpio,
>> + LPI_MUX__,
>> +};
>
> Isn't this entire driver exactly the same as sm8450?
>
ACK, thanks for pointing this out.
Yes you are right, the GPIO pin mapping is identical to SM8490.
I checked SM8550 and SM8650 earlier, but missed comparing against
SM8450. Sorry about that.
I will re-check against SM8450 and use the existing driver instead
of introducing a duplicate.
Thanks & Regards,
Rafi.
> Best regards,
> Krzysztof
>
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