Convert TI PIPE3 PHY binding to DT schema.
Changes during conversion:
- Define a new pattern 'pciephy' to match nodes defined in DT.
- Drop obsolete "id" property from the schema.
Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
---
.../devicetree/bindings/phy/ti,phy-usb3.yaml | 127 +++++++++++++++++++++
1 file changed, 127 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml b/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml
new file mode 100644
index 000000000000..41b3828723ae
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml
@@ -0,0 +1,127 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/ti,phy-usb3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI PIPE3 PHY Module
+
+maintainers:
+ - Kishon Vijay Abraham I <kishon@ti.com>
+
+description:
+ The TI PIPE3 PHY is a high-speed SerDes (Serializer/Deserializer)
+ transceiver integrated in OMAP5, DRA7xx/AM57xx, and similar SoCs.
+ It supports multiple protocols (USB3, SATA, PCIe) using the PIPE3
+ interface standard, which defines a common physical layer for
+ high-speed serial interfaces.
+
+properties:
+ $nodename:
+ pattern: "^(pciephy|usb3phy|phy)(@[0-9a-f]+)?$"
+
+ compatible:
+ enum:
+ - ti,phy-usb3
+ - ti,phy-pipe3-sata
+ - ti,phy-pipe3-pcie
+ - ti,omap-usb3
+
+ reg:
+ minItems: 2
+ maxItems: 3
+
+ reg-names:
+ minItems: 2
+ maxItems: 3
+ items:
+ enum:
+ - phy_rx
+ - phy_tx
+ - pll_ctrl
+
+ "#phy-cells":
+ const: 0
+
+ clocks:
+ minItems: 2
+ maxItems: 7
+
+ clock-names:
+ minItems: 2
+ maxItems: 7
+ items:
+ enum: [wkupclk, sysclk, refclk, dpll_ref,
+ dpll_ref_m2, phy-div, div-clk]
+
+ syscon-phy-power:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description:
+ Phandle/offset pair to system control module register for PHY
+ power on/off.
+
+ syscon-pllreset:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description:
+ Phandle/offset pair to CTRL_CORE_SMA_SW_0 register containing
+ SATA_PLL_SOFT_RESET bit (SATA PHY only).
+
+ syscon-pcs:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description:
+ Phandle/offset pair to system control module for writing PCS delay value.
+
+ ctrl-module:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle of control module for PHY power on.
+ deprecated: true
+
+dependencies:
+ syscon-pllreset:
+ properties:
+ compatible:
+ contains:
+ const: ti,phy-pipe3-sata
+
+required:
+ - reg
+ - compatible
+ - reg-names
+ - "#phy-cells"
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ /* TI PIPE3 USB3 PHY */
+ usb3phy@4a084400 {
+ compatible = "ti,phy-usb3";
+ reg = <0x4a084400 0x80>,
+ <0x4a084800 0x64>,
+ <0x4a084c00 0x40>;
+ reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+ #phy-cells = <0>;
+ clocks = <&usb_phy_cm_clk32k>,
+ <&sys_clkin>,
+ <&usb_otg_ss_refclk960m>;
+ clock-names = "wkupclk", "sysclk", "refclk";
+ ctrl-module = <&omap_control_usb>;
+ };
+
+ - |
+ /* TI PIPE3 SATA PHY */
+ phy@4a096000 {
+ compatible = "ti,phy-pipe3-sata";
+ reg = <0x4A096000 0x80>, /* phy_rx */
+ <0x4A096400 0x64>, /* phy_tx */
+ <0x4A096800 0x40>; /* pll_ctrl */
+ reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+ clocks = <&sys_clkin1>, <&sata_ref_clk>;
+ clock-names = "sysclk", "refclk";
+ syscon-pllreset = <&scm_conf 0x3fc>;
+ #phy-cells = <0>;
+ };
+...
--
2.52.0On Wed, Jan 07, 2026 at 04:11:15PM +0000, Charan Pedumuru wrote:
> Convert TI PIPE3 PHY binding to DT schema.
> Changes during conversion:
> - Define a new pattern 'pciephy' to match nodes defined in DT.
> - Drop obsolete "id" property from the schema.
>
> Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
> ---
> .../devicetree/bindings/phy/ti,phy-usb3.yaml | 127 +++++++++++++++++++++
> 1 file changed, 127 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml b/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml
> new file mode 100644
> index 000000000000..41b3828723ae
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml
> @@ -0,0 +1,127 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/ti,phy-usb3.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: TI PIPE3 PHY Module
> +
> +maintainers:
> + - Kishon Vijay Abraham I <kishon@ti.com>
> +
> +description:
> + The TI PIPE3 PHY is a high-speed SerDes (Serializer/Deserializer)
> + transceiver integrated in OMAP5, DRA7xx/AM57xx, and similar SoCs.
> + It supports multiple protocols (USB3, SATA, PCIe) using the PIPE3
> + interface standard, which defines a common physical layer for
> + high-speed serial interfaces.
> +
> +properties:
> + $nodename:
> + pattern: "^(pciephy|usb3phy|phy)(@[0-9a-f]+)?$"
Again, don't define your own patterns. Either update the .dts files to
use the established patterns (pcie-phy, usb3-phy, phy) or leave it
undefined here.
Plus the unit-address is not optional as 'reg' is not optional...
> +
> + compatible:
> + enum:
> + - ti,phy-usb3
> + - ti,phy-pipe3-sata
> + - ti,phy-pipe3-pcie
> + - ti,omap-usb3
Alphabetical order please.
> +
> + reg:
> + minItems: 2
> + maxItems: 3
> +
> + reg-names:
> + minItems: 2
> + maxItems: 3
> + items:
> + enum:
> + - phy_rx
> + - phy_tx
> + - pll_ctrl
Do this really need to be any order? Looks to me like this works for all
users in tree:
minItems: 2
items:
- const: phy_rx
- const: phy_tx
- const: pll_ctrl
> +
> + "#phy-cells":
> + const: 0
> +
> + clocks:
> + minItems: 2
> + maxItems: 7
> +
> + clock-names:
> + minItems: 2
> + maxItems: 7
> + items:
> + enum: [wkupclk, sysclk, refclk, dpll_ref,
> + dpll_ref_m2, phy-div, div-clk]
> +
> + syscon-phy-power:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description:
> + Phandle/offset pair to system control module register for PHY
> + power on/off.
Needs constrants on the size:
items:
- items:
- description: phandle to ...
- description: offset of ...
> +
> + syscon-pllreset:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description:
> + Phandle/offset pair to CTRL_CORE_SMA_SW_0 register containing
> + SATA_PLL_SOFT_RESET bit (SATA PHY only).
Same here.
> +
> + syscon-pcs:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description:
> + Phandle/offset pair to system control module for writing PCS delay value.
Same here.
> +
> + ctrl-module:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + Phandle of control module for PHY power on.
> + deprecated: true
> +
> +dependencies:
> + syscon-pllreset:
> + properties:
> + compatible:
> + contains:
> + const: ti,phy-pipe3-sata
Usually we express this the other way around:
if:
properties:
compatible:
contains:
const: ti,phy-pipe3-sata
then:
required:
- syscon-pllreset
else:
properties:
syscon-pllreset: false
But that's slightly different as syscon-pllreset is optional for
ti,phy-pipe3-sata in your case. Seems like it should be required if
ti,phy-pipe3-sata?
> +
> +required:
> + - reg
> + - compatible
> + - reg-names
> + - "#phy-cells"
> + - clocks
> + - clock-names
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + /* TI PIPE3 USB3 PHY */
> + usb3phy@4a084400 {
> + compatible = "ti,phy-usb3";
> + reg = <0x4a084400 0x80>,
> + <0x4a084800 0x64>,
> + <0x4a084c00 0x40>;
> + reg-names = "phy_rx", "phy_tx", "pll_ctrl";
> + #phy-cells = <0>;
> + clocks = <&usb_phy_cm_clk32k>,
> + <&sys_clkin>,
> + <&usb_otg_ss_refclk960m>;
> + clock-names = "wkupclk", "sysclk", "refclk";
> + ctrl-module = <&omap_control_usb>;
> + };
> +
> + - |
> + /* TI PIPE3 SATA PHY */
> + phy@4a096000 {
> + compatible = "ti,phy-pipe3-sata";
> + reg = <0x4A096000 0x80>, /* phy_rx */
> + <0x4A096400 0x64>, /* phy_tx */
> + <0x4A096800 0x40>; /* pll_ctrl */
> + reg-names = "phy_rx", "phy_tx", "pll_ctrl";
> + clocks = <&sys_clkin1>, <&sata_ref_clk>;
> + clock-names = "sysclk", "refclk";
> + syscon-pllreset = <&scm_conf 0x3fc>;
> + #phy-cells = <0>;
> + };
> +...
>
> --
> 2.52.0
>
On 15-01-2026 20:15, Rob Herring wrote:
> On Wed, Jan 07, 2026 at 04:11:15PM +0000, Charan Pedumuru wrote:
>> Convert TI PIPE3 PHY binding to DT schema.
>> Changes during conversion:
>> - Define a new pattern 'pciephy' to match nodes defined in DT.
>> - Drop obsolete "id" property from the schema.
>>
>> Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
>> ---
>> .../devicetree/bindings/phy/ti,phy-usb3.yaml | 127 +++++++++++++++++++++
>> 1 file changed, 127 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml b/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml
>> new file mode 100644
>> index 000000000000..41b3828723ae
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml
>> @@ -0,0 +1,127 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/phy/ti,phy-usb3.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: TI PIPE3 PHY Module
>> +
>> +maintainers:
>> + - Kishon Vijay Abraham I <kishon@ti.com>
>> +
>> +description:
>> + The TI PIPE3 PHY is a high-speed SerDes (Serializer/Deserializer)
>> + transceiver integrated in OMAP5, DRA7xx/AM57xx, and similar SoCs.
>> + It supports multiple protocols (USB3, SATA, PCIe) using the PIPE3
>> + interface standard, which defines a common physical layer for
>> + high-speed serial interfaces.
>> +
>> +properties:
>> + $nodename:
>> + pattern: "^(pciephy|usb3phy|phy)(@[0-9a-f]+)?$"
>
> Again, don't define your own patterns. Either update the .dts files to
> use the established patterns (pcie-phy, usb3-phy, phy) or leave it
> undefined here.
Sure, I will try to update them in dts.
>
> Plus the unit-address is not optional as 'reg' is not optional...
Okay.
>
>> +
>> + compatible:
>> + enum:
>> + - ti,phy-usb3
>> + - ti,phy-pipe3-sata
>> + - ti,phy-pipe3-pcie
>> + - ti,omap-usb3
>
> Alphabetical order please.
Sure.
>
>> +
>> + reg:
>> + minItems: 2
>> + maxItems: 3
>> +
>> + reg-names:
>> + minItems: 2
>> + maxItems: 3
>> + items:
>> + enum:
>> + - phy_rx
>> + - phy_tx
>> + - pll_ctrl
>
> Do this really need to be any order? Looks to me like this works for all
> users in tree:
>
> minItems: 2
> items:
> - const: phy_rx
> - const: phy_tx
> - const: pll_ctrl
This will work, I tested it now.
>
>> +
>> + "#phy-cells":
>> + const: 0
>> +
>> + clocks:
>> + minItems: 2
>> + maxItems: 7
>> +
>> + clock-names:
>> + minItems: 2
>> + maxItems: 7
>> + items:
>> + enum: [wkupclk, sysclk, refclk, dpll_ref,
>> + dpll_ref_m2, phy-div, div-clk]
>> +
>> + syscon-phy-power:
>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>> + description:
>> + Phandle/offset pair to system control module register for PHY
>> + power on/off.
>
> Needs constrants on the size:
>
> items:
> - items:
> - description: phandle to ...
> - description: offset of ...
Sure, I will change for the other properties too.
>
>> +
>> + syscon-pllreset:
>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>> + description:
>> + Phandle/offset pair to CTRL_CORE_SMA_SW_0 register containing
>> + SATA_PLL_SOFT_RESET bit (SATA PHY only).
>
> Same here.
>
>> +
>> + syscon-pcs:
>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>> + description:
>> + Phandle/offset pair to system control module for writing PCS delay value.
>
> Same here.
>
>> +
>> + ctrl-module:
>> + $ref: /schemas/types.yaml#/definitions/phandle
>> + description:
>> + Phandle of control module for PHY power on.
>> + deprecated: true
>> +
>> +dependencies:
>> + syscon-pllreset:
>> + properties:
>> + compatible:
>> + contains:
>> + const: ti,phy-pipe3-sata
>
> Usually we express this the other way around:
>
> if:
> properties:
> compatible:
> contains:
> const: ti,phy-pipe3-sata
> then:
> required:
> - syscon-pllreset
> else:
> properties:
> syscon-pllreset: false
>
> But that's slightly different as syscon-pllreset is optional for
> ti,phy-pipe3-sata in your case. Seems like it should be required if
> ti,phy-pipe3-sata?
I checked the DTS, it is not a required property. So, I will not change the format.
>
>
>> +
>> +required:
>> + - reg
>> + - compatible
>> + - reg-names
>> + - "#phy-cells"
>> + - clocks
>> + - clock-names
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> + - |
>> + /* TI PIPE3 USB3 PHY */
>> + usb3phy@4a084400 {
>> + compatible = "ti,phy-usb3";
>> + reg = <0x4a084400 0x80>,
>> + <0x4a084800 0x64>,
>> + <0x4a084c00 0x40>;
>> + reg-names = "phy_rx", "phy_tx", "pll_ctrl";
>> + #phy-cells = <0>;
>> + clocks = <&usb_phy_cm_clk32k>,
>> + <&sys_clkin>,
>> + <&usb_otg_ss_refclk960m>;
>> + clock-names = "wkupclk", "sysclk", "refclk";
>> + ctrl-module = <&omap_control_usb>;
>> + };
>> +
>> + - |
>> + /* TI PIPE3 SATA PHY */
>> + phy@4a096000 {
>> + compatible = "ti,phy-pipe3-sata";
>> + reg = <0x4A096000 0x80>, /* phy_rx */
>> + <0x4A096400 0x64>, /* phy_tx */
>> + <0x4A096800 0x40>; /* pll_ctrl */
>> + reg-names = "phy_rx", "phy_tx", "pll_ctrl";
>> + clocks = <&sys_clkin1>, <&sata_ref_clk>;
>> + clock-names = "sysclk", "refclk";
>> + syscon-pllreset = <&scm_conf 0x3fc>;
>> + #phy-cells = <0>;
>> + };
>> +...
>>
>> --
>> 2.52.0
>>
--
Best Regards,
Charan.
On 07-01-26, 16:11, Charan Pedumuru wrote:
> Convert TI PIPE3 PHY binding to DT schema.
> Changes during conversion:
> - Define a new pattern 'pciephy' to match nodes defined in DT.
> - Drop obsolete "id" property from the schema.
>
> Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
> ---
> .../devicetree/bindings/phy/ti,phy-usb3.yaml | 127 +++++++++++++++++++++
> 1 file changed, 127 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml b/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml
> new file mode 100644
> index 000000000000..41b3828723ae
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml
> @@ -0,0 +1,127 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/ti,phy-usb3.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: TI PIPE3 PHY Module
> +
> +maintainers:
> + - Kishon Vijay Abraham I <kishon@ti.com>
That is not correct, please check the current people on TI for this.
> +
> +description:
> + The TI PIPE3 PHY is a high-speed SerDes (Serializer/Deserializer)
> + transceiver integrated in OMAP5, DRA7xx/AM57xx, and similar SoCs.
> + It supports multiple protocols (USB3, SATA, PCIe) using the PIPE3
> + interface standard, which defines a common physical layer for
> + high-speed serial interfaces.
> +
> +properties:
> + $nodename:
> + pattern: "^(pciephy|usb3phy|phy)(@[0-9a-f]+)?$"
> +
> + compatible:
> + enum:
> + - ti,phy-usb3
> + - ti,phy-pipe3-sata
> + - ti,phy-pipe3-pcie
> + - ti,omap-usb3
> +
> + reg:
> + minItems: 2
> + maxItems: 3
> +
> + reg-names:
> + minItems: 2
> + maxItems: 3
> + items:
> + enum:
> + - phy_rx
> + - phy_tx
> + - pll_ctrl
> +
> + "#phy-cells":
> + const: 0
> +
> + clocks:
> + minItems: 2
> + maxItems: 7
> +
> + clock-names:
> + minItems: 2
> + maxItems: 7
> + items:
> + enum: [wkupclk, sysclk, refclk, dpll_ref,
> + dpll_ref_m2, phy-div, div-clk]
> +
> + syscon-phy-power:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description:
> + Phandle/offset pair to system control module register for PHY
> + power on/off.
> +
> + syscon-pllreset:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description:
> + Phandle/offset pair to CTRL_CORE_SMA_SW_0 register containing
> + SATA_PLL_SOFT_RESET bit (SATA PHY only).
> +
> + syscon-pcs:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description:
> + Phandle/offset pair to system control module for writing PCS delay value.
> +
> + ctrl-module:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + Phandle of control module for PHY power on.
> + deprecated: true
> +
> +dependencies:
> + syscon-pllreset:
> + properties:
> + compatible:
> + contains:
> + const: ti,phy-pipe3-sata
> +
> +required:
> + - reg
> + - compatible
> + - reg-names
> + - "#phy-cells"
> + - clocks
> + - clock-names
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + /* TI PIPE3 USB3 PHY */
> + usb3phy@4a084400 {
> + compatible = "ti,phy-usb3";
> + reg = <0x4a084400 0x80>,
> + <0x4a084800 0x64>,
> + <0x4a084c00 0x40>;
> + reg-names = "phy_rx", "phy_tx", "pll_ctrl";
> + #phy-cells = <0>;
> + clocks = <&usb_phy_cm_clk32k>,
> + <&sys_clkin>,
> + <&usb_otg_ss_refclk960m>;
> + clock-names = "wkupclk", "sysclk", "refclk";
> + ctrl-module = <&omap_control_usb>;
> + };
> +
> + - |
> + /* TI PIPE3 SATA PHY */
> + phy@4a096000 {
> + compatible = "ti,phy-pipe3-sata";
> + reg = <0x4A096000 0x80>, /* phy_rx */
> + <0x4A096400 0x64>, /* phy_tx */
> + <0x4A096800 0x40>; /* pll_ctrl */
> + reg-names = "phy_rx", "phy_tx", "pll_ctrl";
> + clocks = <&sys_clkin1>, <&sata_ref_clk>;
> + clock-names = "sysclk", "refclk";
> + syscon-pllreset = <&scm_conf 0x3fc>;
> + #phy-cells = <0>;
> + };
> +...
>
> --
> 2.52.0
--
~Vinod
On 14-01-2026 19:46, Vinod Koul wrote:
> On 07-01-26, 16:11, Charan Pedumuru wrote:
>> Convert TI PIPE3 PHY binding to DT schema.
>> Changes during conversion:
>> - Define a new pattern 'pciephy' to match nodes defined in DT.
>> - Drop obsolete "id" property from the schema.
>>
>> Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
>> ---
>> .../devicetree/bindings/phy/ti,phy-usb3.yaml | 127 +++++++++++++++++++++
>> 1 file changed, 127 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml b/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml
>> new file mode 100644
>> index 000000000000..41b3828723ae
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml
>> @@ -0,0 +1,127 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/phy/ti,phy-usb3.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: TI PIPE3 PHY Module
>> +
>> +maintainers:
>> + - Kishon Vijay Abraham I <kishon@ti.com>
>
> That is not correct, please check the current people on TI for this.
I checked the driver author and MAINTAINERS, I couldn't find anyone. No one seems to have updated the MAINTAINER.
>
>> +
>> +description:
>> + The TI PIPE3 PHY is a high-speed SerDes (Serializer/Deserializer)
>> + transceiver integrated in OMAP5, DRA7xx/AM57xx, and similar SoCs.
>> + It supports multiple protocols (USB3, SATA, PCIe) using the PIPE3
>> + interface standard, which defines a common physical layer for
>> + high-speed serial interfaces.
>> +
>> +properties:
>> + $nodename:
>> + pattern: "^(pciephy|usb3phy|phy)(@[0-9a-f]+)?$"
>> +
>> + compatible:
>> + enum:
>> + - ti,phy-usb3
>> + - ti,phy-pipe3-sata
>> + - ti,phy-pipe3-pcie
>> + - ti,omap-usb3
>> +
>> + reg:
>> + minItems: 2
>> + maxItems: 3
>> +
>> + reg-names:
>> + minItems: 2
>> + maxItems: 3
>> + items:
>> + enum:
>> + - phy_rx
>> + - phy_tx
>> + - pll_ctrl
>> +
>> + "#phy-cells":
>> + const: 0
>> +
>> + clocks:
>> + minItems: 2
>> + maxItems: 7
>> +
>> + clock-names:
>> + minItems: 2
>> + maxItems: 7
>> + items:
>> + enum: [wkupclk, sysclk, refclk, dpll_ref,
>> + dpll_ref_m2, phy-div, div-clk]
>> +
>> + syscon-phy-power:
>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>> + description:
>> + Phandle/offset pair to system control module register for PHY
>> + power on/off.
>> +
>> + syscon-pllreset:
>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>> + description:
>> + Phandle/offset pair to CTRL_CORE_SMA_SW_0 register containing
>> + SATA_PLL_SOFT_RESET bit (SATA PHY only).
>> +
>> + syscon-pcs:
>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>> + description:
>> + Phandle/offset pair to system control module for writing PCS delay value.
>> +
>> + ctrl-module:
>> + $ref: /schemas/types.yaml#/definitions/phandle
>> + description:
>> + Phandle of control module for PHY power on.
>> + deprecated: true
>> +
>> +dependencies:
>> + syscon-pllreset:
>> + properties:
>> + compatible:
>> + contains:
>> + const: ti,phy-pipe3-sata
>> +
>> +required:
>> + - reg
>> + - compatible
>> + - reg-names
>> + - "#phy-cells"
>> + - clocks
>> + - clock-names
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> + - |
>> + /* TI PIPE3 USB3 PHY */
>> + usb3phy@4a084400 {
>> + compatible = "ti,phy-usb3";
>> + reg = <0x4a084400 0x80>,
>> + <0x4a084800 0x64>,
>> + <0x4a084c00 0x40>;
>> + reg-names = "phy_rx", "phy_tx", "pll_ctrl";
>> + #phy-cells = <0>;
>> + clocks = <&usb_phy_cm_clk32k>,
>> + <&sys_clkin>,
>> + <&usb_otg_ss_refclk960m>;
>> + clock-names = "wkupclk", "sysclk", "refclk";
>> + ctrl-module = <&omap_control_usb>;
>> + };
>> +
>> + - |
>> + /* TI PIPE3 SATA PHY */
>> + phy@4a096000 {
>> + compatible = "ti,phy-pipe3-sata";
>> + reg = <0x4A096000 0x80>, /* phy_rx */
>> + <0x4A096400 0x64>, /* phy_tx */
>> + <0x4A096800 0x40>; /* pll_ctrl */
>> + reg-names = "phy_rx", "phy_tx", "pll_ctrl";
>> + clocks = <&sys_clkin1>, <&sata_ref_clk>;
>> + clock-names = "sysclk", "refclk";
>> + syscon-pllreset = <&scm_conf 0x3fc>;
>> + #phy-cells = <0>;
>> + };
>> +...
>>
>> --
>> 2.52.0
>
--
Best Regards,
Charan.
On 14-01-26, 20:16, Charan Pedumuru wrote: > > > On 14-01-2026 19:46, Vinod Koul wrote: > > On 07-01-26, 16:11, Charan Pedumuru wrote: > >> Convert TI PIPE3 PHY binding to DT schema. > >> Changes during conversion: > >> - Define a new pattern 'pciephy' to match nodes defined in DT. > >> - Drop obsolete "id" property from the schema. > >> > >> Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com> > >> --- > >> .../devicetree/bindings/phy/ti,phy-usb3.yaml | 127 +++++++++++++++++++++ > >> 1 file changed, 127 insertions(+) > >> > >> diff --git a/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml b/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml > >> new file mode 100644 > >> index 000000000000..41b3828723ae > >> --- /dev/null > >> +++ b/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml > >> @@ -0,0 +1,127 @@ > >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > >> +%YAML 1.2 > >> +--- > >> +$id: http://devicetree.org/schemas/phy/ti,phy-usb3.yaml# > >> +$schema: http://devicetree.org/meta-schemas/core.yaml# > >> + > >> +title: TI PIPE3 PHY Module > >> + > >> +maintainers: > >> + - Kishon Vijay Abraham I <kishon@ti.com> > > > > That is not correct, please check the current people on TI for this. > > I checked the driver author and MAINTAINERS, I couldn't find anyone. > No one seems to have updated the MAINTAINER. Please chekc in git log about recent contributions from TI people -- ~Vinod
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