Add the nodes for the UFS PHY and UFS host controller, along with the
ICE used for UFS.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
arch/arm64/boot/dts/qcom/milos.dtsi | 127 +++++++++++++++++++++++++++++++++++-
1 file changed, 124 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
index e1a51d43943f..0f69deabb60c 100644
--- a/arch/arm64/boot/dts/qcom/milos.dtsi
+++ b/arch/arm64/boot/dts/qcom/milos.dtsi
@@ -797,9 +797,9 @@ gcc: clock-controller@100000 {
<&sleep_clk>,
<0>, /* pcie_0_pipe_clk */
<0>, /* pcie_1_pipe_clk */
- <0>, /* ufs_phy_rx_symbol_0_clk */
- <0>, /* ufs_phy_rx_symbol_1_clk */
- <0>, /* ufs_phy_tx_symbol_0_clk */
+ <&ufs_mem_phy 0>,
+ <&ufs_mem_phy 1>,
+ <&ufs_mem_phy 2>,
<0>; /* usb3_phy_wrapper_gcc_usb30_pipe_clk */
#clock-cells = <1>;
@@ -1151,6 +1151,127 @@ aggre2_noc: interconnect@1700000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ ufs_mem_phy: phy@1d80000 {
+ compatible = "qcom,milos-qmp-ufs-phy";
+ reg = <0x0 0x01d80000 0x0 0x2000>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+ <&tcsr TCSR_UFS_CLKREF_EN>;
+ clock-names = "ref",
+ "ref_aux",
+ "qref";
+
+ resets = <&ufs_mem_hc 0>;
+ reset-names = "ufsphy";
+
+ power-domains = <&gcc UFS_MEM_PHY_GDSC>;
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ ufs_mem_hc: ufshc@1d84000 {
+ compatible = "qcom,milos-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
+ reg = <0x0 0x01d84000 0x0 0x3000>;
+
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>,
+ <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+ <&tcsr TCSR_UFS_PAD_CLKREF_EN>,
+ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+ clock-names = "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk",
+ "rx_lane1_sync_clk";
+
+ resets = <&gcc GCC_UFS_PHY_BCR>;
+ reset-names = "rst";
+
+ interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc_cfg SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "ufs-ddr",
+ "cpu-ufs";
+
+ power-domains = <&gcc UFS_PHY_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ operating-points-v2 = <&ufs_opp_table>;
+
+ iommus = <&apps_smmu 0x60 0>;
+
+ lanes-per-direction = <2>;
+ qcom,ice = <&ice>;
+
+ phys = <&ufs_mem_phy>;
+ phy-names = "ufsphy";
+
+ #reset-cells = <1>;
+
+ status = "disabled";
+
+ ufs_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-75000000 {
+ opp-hz = /bits/ 64 <75000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <75000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-150000000 {
+ opp-hz = /bits/ 64 <150000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <150000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <300000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ ice: crypto@1d88000 {
+ compatible = "qcom,milos-inline-crypto-engine",
+ "qcom,inline-crypto-engine";
+ reg = <0x0 0x01d88000 0x0 0x18000>;
+
+ clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x20000>;
--
2.52.0Hi Luca! > Add the nodes for the UFS PHY and UFS host controller, along with the > ICE used for UFS. arch/arm64/boot/dts/qcom/milos.dtsi isn't present in v6.19-rc1 so I am unable to apply this. -- Martin K. Petersen
Hi Martin, On Mon Jan 12, 2026 at 3:52 AM CET, Martin K. Petersen wrote: > > Hi Luca! > >> Add the nodes for the UFS PHY and UFS host controller, along with the >> ICE used for UFS. > > arch/arm64/boot/dts/qcom/milos.dtsi isn't present in v6.19-rc1 so I am > unable to apply this. This patch is based on linux-next where milos.dtsi exists, but any arm64 qcom dts is for Bjorn to pick up, so please ignore this patch. Regards Luca
Hi,
On 1/7/26 09:05, Luca Weiss wrote:
> Add the nodes for the UFS PHY and UFS host controller, along with the
> ICE used for UFS.
>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> arch/arm64/boot/dts/qcom/milos.dtsi | 127 +++++++++++++++++++++++++++++++++++-
> 1 file changed, 124 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
> index e1a51d43943f..0f69deabb60c 100644
> --- a/arch/arm64/boot/dts/qcom/milos.dtsi
> +++ b/arch/arm64/boot/dts/qcom/milos.dtsi
> @@ -797,9 +797,9 @@ gcc: clock-controller@100000 {
> <&sleep_clk>,
> <0>, /* pcie_0_pipe_clk */
> <0>, /* pcie_1_pipe_clk */
> - <0>, /* ufs_phy_rx_symbol_0_clk */
> - <0>, /* ufs_phy_rx_symbol_1_clk */
> - <0>, /* ufs_phy_tx_symbol_0_clk */
> + <&ufs_mem_phy 0>,
> + <&ufs_mem_phy 1>,
> + <&ufs_mem_phy 2>,
> <0>; /* usb3_phy_wrapper_gcc_usb30_pipe_clk */
>
> #clock-cells = <1>;
> @@ -1151,6 +1151,127 @@ aggre2_noc: interconnect@1700000 {
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
>
> + ufs_mem_phy: phy@1d80000 {
> + compatible = "qcom,milos-qmp-ufs-phy";
> + reg = <0x0 0x01d80000 0x0 0x2000>;
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
> + <&tcsr TCSR_UFS_CLKREF_EN>;
> + clock-names = "ref",
> + "ref_aux",
> + "qref";
> +
> + resets = <&ufs_mem_hc 0>;
> + reset-names = "ufsphy";
> +
> + power-domains = <&gcc UFS_MEM_PHY_GDSC>;
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> + ufs_mem_hc: ufshc@1d84000 {
> + compatible = "qcom,milos-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
> + reg = <0x0 0x01d84000 0x0 0x3000>;
> +
> + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
> +
> + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
> + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> + <&gcc GCC_UFS_PHY_AHB_CLK>,
> + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
> + <&tcsr TCSR_UFS_PAD_CLKREF_EN>,
> + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
> + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
> + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
> + clock-names = "core_clk",
> + "bus_aggr_clk",
> + "iface_clk",
> + "core_clk_unipro",
> + "ref_clk",
> + "tx_lane0_sync_clk",
> + "rx_lane0_sync_clk",
> + "rx_lane1_sync_clk";
> +
> + resets = <&gcc GCC_UFS_PHY_BCR>;
> + reset-names = "rst";
> +
> + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &cnoc_cfg SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
> + interconnect-names = "ufs-ddr",
> + "cpu-ufs";
> +
> + power-domains = <&gcc UFS_PHY_GDSC>;
> + required-opps = <&rpmhpd_opp_nom>;
> +
> + operating-points-v2 = <&ufs_opp_table>;
> +
> + iommus = <&apps_smmu 0x60 0>;
dma-coherent ?
and no MCQ support ?
<snip>
Thanks,
Neil
On 1/7/26 14:53, Neil Armstrong wrote:
> Hi,
>
> On 1/7/26 09:05, Luca Weiss wrote:
>> Add the nodes for the UFS PHY and UFS host controller, along with the
>> ICE used for UFS.
>>
>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
>> ---
>> arch/arm64/boot/dts/qcom/milos.dtsi | 127 +++++++++++++++++++++++++++++++++++-
>> 1 file changed, 124 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
>> index e1a51d43943f..0f69deabb60c 100644
>> --- a/arch/arm64/boot/dts/qcom/milos.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/milos.dtsi
>> @@ -797,9 +797,9 @@ gcc: clock-controller@100000 {
>> <&sleep_clk>,
>> <0>, /* pcie_0_pipe_clk */
>> <0>, /* pcie_1_pipe_clk */
>> - <0>, /* ufs_phy_rx_symbol_0_clk */
>> - <0>, /* ufs_phy_rx_symbol_1_clk */
>> - <0>, /* ufs_phy_tx_symbol_0_clk */
>> + <&ufs_mem_phy 0>,
>> + <&ufs_mem_phy 1>,
>> + <&ufs_mem_phy 2>,
>> <0>; /* usb3_phy_wrapper_gcc_usb30_pipe_clk */
>> #clock-cells = <1>;
>> @@ -1151,6 +1151,127 @@ aggre2_noc: interconnect@1700000 {
>> qcom,bcm-voters = <&apps_bcm_voter>;
>> };
>> + ufs_mem_phy: phy@1d80000 {
>> + compatible = "qcom,milos-qmp-ufs-phy";
>> + reg = <0x0 0x01d80000 0x0 0x2000>;
>> +
>> + clocks = <&rpmhcc RPMH_CXO_CLK>,
>> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
>> + <&tcsr TCSR_UFS_CLKREF_EN>;
>> + clock-names = "ref",
>> + "ref_aux",
>> + "qref";
>> +
>> + resets = <&ufs_mem_hc 0>;
>> + reset-names = "ufsphy";
>> +
>> + power-domains = <&gcc UFS_MEM_PHY_GDSC>;
>> +
>> + #clock-cells = <1>;
>> + #phy-cells = <0>;
>> +
>> + status = "disabled";
>> + };
>> +
>> + ufs_mem_hc: ufshc@1d84000 {
>> + compatible = "qcom,milos-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
>> + reg = <0x0 0x01d84000 0x0 0x3000>;
>> +
>> + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
>> +
>> + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
>> + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
>> + <&gcc GCC_UFS_PHY_AHB_CLK>,
>> + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
>> + <&tcsr TCSR_UFS_PAD_CLKREF_EN>,
>> + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
>> + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
>> + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
>> + clock-names = "core_clk",
>> + "bus_aggr_clk",
>> + "iface_clk",
>> + "core_clk_unipro",
>> + "ref_clk",
>> + "tx_lane0_sync_clk",
>> + "rx_lane0_sync_clk",
>> + "rx_lane1_sync_clk";
>> +
>> + resets = <&gcc GCC_UFS_PHY_BCR>;
>> + reset-names = "rst";
>> +
>> + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
>> + &cnoc_cfg SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
>> + interconnect-names = "ufs-ddr",
>> + "cpu-ufs";
>> +
>> + power-domains = <&gcc UFS_PHY_GDSC>;
>> + required-opps = <&rpmhpd_opp_nom>;
>> +
>> + operating-points-v2 = <&ufs_opp_table>;
>> +
>> + iommus = <&apps_smmu 0x60 0>;
>
> dma-coherent ?
>
> and no MCQ support ?
So, people just ignore my comment ?
Milos is based on SM8550, so it should have dma-coherent, for the MCQ
I hope they used the fixed added to the SM8650 UFS controller for MCQ.
Neil
>
> <snip>
>
> Thanks,
> Neil
Hi Neil,
On Mon Jan 12, 2026 at 9:26 AM CET, Neil Armstrong wrote:
> On 1/7/26 14:53, Neil Armstrong wrote:
>> Hi,
>>
>> On 1/7/26 09:05, Luca Weiss wrote:
>>> Add the nodes for the UFS PHY and UFS host controller, along with the
>>> ICE used for UFS.
>>>
>>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
>>> ---
>>> arch/arm64/boot/dts/qcom/milos.dtsi | 127 +++++++++++++++++++++++++++++++++++-
>>> 1 file changed, 124 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
>>> index e1a51d43943f..0f69deabb60c 100644
>>> --- a/arch/arm64/boot/dts/qcom/milos.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/milos.dtsi
>>> @@ -797,9 +797,9 @@ gcc: clock-controller@100000 {
>>> <&sleep_clk>,
>>> <0>, /* pcie_0_pipe_clk */
>>> <0>, /* pcie_1_pipe_clk */
>>> - <0>, /* ufs_phy_rx_symbol_0_clk */
>>> - <0>, /* ufs_phy_rx_symbol_1_clk */
>>> - <0>, /* ufs_phy_tx_symbol_0_clk */
>>> + <&ufs_mem_phy 0>,
>>> + <&ufs_mem_phy 1>,
>>> + <&ufs_mem_phy 2>,
>>> <0>; /* usb3_phy_wrapper_gcc_usb30_pipe_clk */
>>> #clock-cells = <1>;
>>> @@ -1151,6 +1151,127 @@ aggre2_noc: interconnect@1700000 {
>>> qcom,bcm-voters = <&apps_bcm_voter>;
>>> };
>>> + ufs_mem_phy: phy@1d80000 {
>>> + compatible = "qcom,milos-qmp-ufs-phy";
>>> + reg = <0x0 0x01d80000 0x0 0x2000>;
>>> +
>>> + clocks = <&rpmhcc RPMH_CXO_CLK>,
>>> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
>>> + <&tcsr TCSR_UFS_CLKREF_EN>;
>>> + clock-names = "ref",
>>> + "ref_aux",
>>> + "qref";
>>> +
>>> + resets = <&ufs_mem_hc 0>;
>>> + reset-names = "ufsphy";
>>> +
>>> + power-domains = <&gcc UFS_MEM_PHY_GDSC>;
>>> +
>>> + #clock-cells = <1>;
>>> + #phy-cells = <0>;
>>> +
>>> + status = "disabled";
>>> + };
>>> +
>>> + ufs_mem_hc: ufshc@1d84000 {
>>> + compatible = "qcom,milos-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
>>> + reg = <0x0 0x01d84000 0x0 0x3000>;
>>> +
>>> + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
>>> +
>>> + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
>>> + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
>>> + <&gcc GCC_UFS_PHY_AHB_CLK>,
>>> + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
>>> + <&tcsr TCSR_UFS_PAD_CLKREF_EN>,
>>> + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
>>> + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
>>> + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
>>> + clock-names = "core_clk",
>>> + "bus_aggr_clk",
>>> + "iface_clk",
>>> + "core_clk_unipro",
>>> + "ref_clk",
>>> + "tx_lane0_sync_clk",
>>> + "rx_lane0_sync_clk",
>>> + "rx_lane1_sync_clk";
>>> +
>>> + resets = <&gcc GCC_UFS_PHY_BCR>;
>>> + reset-names = "rst";
>>> +
>>> + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
>>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>>> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
>>> + &cnoc_cfg SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
>>> + interconnect-names = "ufs-ddr",
>>> + "cpu-ufs";
>>> +
>>> + power-domains = <&gcc UFS_PHY_GDSC>;
>>> + required-opps = <&rpmhpd_opp_nom>;
>>> +
>>> + operating-points-v2 = <&ufs_opp_table>;
>>> +
>>> + iommus = <&apps_smmu 0x60 0>;
>>
>> dma-coherent ?
Given that downstream volcano.dtsi has dma-coherent in the ufshc@1d84000
node, looks like this is missing in my patch.
>>
>> and no MCQ support ?
Not sure, I could only find one reference to MCQ on createpoint for
milos, but given there's no mcq_sqd/mcq_vs reg defined downstream, and I
couldn't find anything for the same register values in the .FLAT file, I
don't think Milos has MCQ? Feel free to prove me wrong though.
>
> So, people just ignore my comment ?
>
> Milos is based on SM8550, so it should have dma-coherent, for the MCQ
> I hope they used the fixed added to the SM8650 UFS controller for MCQ.
Not sure what this should mean regarding MCQ...
Regards
Luca
>
> Neil
>
>>
>> <snip>
>>
>> Thanks,
>> Neil
On 1/12/26 9:45 AM, Luca Weiss wrote:
> Hi Neil,
>
> On Mon Jan 12, 2026 at 9:26 AM CET, Neil Armstrong wrote:
>> On 1/7/26 14:53, Neil Armstrong wrote:
>>> Hi,
>>>
>>> On 1/7/26 09:05, Luca Weiss wrote:
>>>> Add the nodes for the UFS PHY and UFS host controller, along with the
>>>> ICE used for UFS.
>>>>
>>>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
>>>> ---
>>>> arch/arm64/boot/dts/qcom/milos.dtsi | 127 +++++++++++++++++++++++++++++++++++-
>>>> 1 file changed, 124 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
>>>> index e1a51d43943f..0f69deabb60c 100644
>>>> --- a/arch/arm64/boot/dts/qcom/milos.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/milos.dtsi
>>>> @@ -797,9 +797,9 @@ gcc: clock-controller@100000 {
>>>> <&sleep_clk>,
>>>> <0>, /* pcie_0_pipe_clk */
>>>> <0>, /* pcie_1_pipe_clk */
>>>> - <0>, /* ufs_phy_rx_symbol_0_clk */
>>>> - <0>, /* ufs_phy_rx_symbol_1_clk */
>>>> - <0>, /* ufs_phy_tx_symbol_0_clk */
>>>> + <&ufs_mem_phy 0>,
>>>> + <&ufs_mem_phy 1>,
>>>> + <&ufs_mem_phy 2>,
>>>> <0>; /* usb3_phy_wrapper_gcc_usb30_pipe_clk */
>>>> #clock-cells = <1>;
>>>> @@ -1151,6 +1151,127 @@ aggre2_noc: interconnect@1700000 {
>>>> qcom,bcm-voters = <&apps_bcm_voter>;
>>>> };
>>>> + ufs_mem_phy: phy@1d80000 {
>>>> + compatible = "qcom,milos-qmp-ufs-phy";
>>>> + reg = <0x0 0x01d80000 0x0 0x2000>;
>>>> +
>>>> + clocks = <&rpmhcc RPMH_CXO_CLK>,
>>>> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
>>>> + <&tcsr TCSR_UFS_CLKREF_EN>;
>>>> + clock-names = "ref",
>>>> + "ref_aux",
>>>> + "qref";
>>>> +
>>>> + resets = <&ufs_mem_hc 0>;
>>>> + reset-names = "ufsphy";
>>>> +
>>>> + power-domains = <&gcc UFS_MEM_PHY_GDSC>;
>>>> +
>>>> + #clock-cells = <1>;
>>>> + #phy-cells = <0>;
>>>> +
>>>> + status = "disabled";
>>>> + };
>>>> +
>>>> + ufs_mem_hc: ufshc@1d84000 {
>>>> + compatible = "qcom,milos-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
>>>> + reg = <0x0 0x01d84000 0x0 0x3000>;
>>>> +
>>>> + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
>>>> +
>>>> + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
>>>> + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
>>>> + <&gcc GCC_UFS_PHY_AHB_CLK>,
>>>> + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
>>>> + <&tcsr TCSR_UFS_PAD_CLKREF_EN>,
>>>> + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
>>>> + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
>>>> + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
>>>> + clock-names = "core_clk",
>>>> + "bus_aggr_clk",
>>>> + "iface_clk",
>>>> + "core_clk_unipro",
>>>> + "ref_clk",
>>>> + "tx_lane0_sync_clk",
>>>> + "rx_lane0_sync_clk",
>>>> + "rx_lane1_sync_clk";
>>>> +
>>>> + resets = <&gcc GCC_UFS_PHY_BCR>;
>>>> + reset-names = "rst";
>>>> +
>>>> + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
>>>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>>>> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
>>>> + &cnoc_cfg SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
>>>> + interconnect-names = "ufs-ddr",
>>>> + "cpu-ufs";
>>>> +
>>>> + power-domains = <&gcc UFS_PHY_GDSC>;
>>>> + required-opps = <&rpmhpd_opp_nom>;
>>>> +
>>>> + operating-points-v2 = <&ufs_opp_table>;
>>>> +
>>>> + iommus = <&apps_smmu 0x60 0>;
>>>
>>> dma-coherent ?
>
>
> Given that downstream volcano.dtsi has dma-coherent in the ufshc@1d84000
> node, looks like this is missing in my patch.
Seems that way
>>>
>>> and no MCQ support ?
>
> Not sure, I could only find one reference to MCQ on createpoint for
> milos, but given there's no mcq_sqd/mcq_vs reg defined downstream, and I
> couldn't find anything for the same register values in the .FLAT file, I
> don't think Milos has MCQ? Feel free to prove me wrong though.
>
>>
>> So, people just ignore my comment ?
>>
>> Milos is based on SM8550, so it should have dma-coherent, for the MCQ
>> I hope they used the fixed added to the SM8650 UFS controller for MCQ.
>
> Not sure what this should mean regarding MCQ...
This platform doesn't support MCQ
Konrad
On 1/12/26 11:29, Konrad Dybcio wrote:
> On 1/12/26 9:45 AM, Luca Weiss wrote:
>> Hi Neil,
>>
>> On Mon Jan 12, 2026 at 9:26 AM CET, Neil Armstrong wrote:
>>> On 1/7/26 14:53, Neil Armstrong wrote:
>>>> Hi,
>>>>
>>>> On 1/7/26 09:05, Luca Weiss wrote:
>>>>> Add the nodes for the UFS PHY and UFS host controller, along with the
>>>>> ICE used for UFS.
>>>>>
>>>>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
>>>>> ---
>>>>> arch/arm64/boot/dts/qcom/milos.dtsi | 127 +++++++++++++++++++++++++++++++++++-
>>>>> 1 file changed, 124 insertions(+), 3 deletions(-)
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
>>>>> index e1a51d43943f..0f69deabb60c 100644
>>>>> --- a/arch/arm64/boot/dts/qcom/milos.dtsi
>>>>> +++ b/arch/arm64/boot/dts/qcom/milos.dtsi
>>>>> @@ -797,9 +797,9 @@ gcc: clock-controller@100000 {
>>>>> <&sleep_clk>,
>>>>> <0>, /* pcie_0_pipe_clk */
>>>>> <0>, /* pcie_1_pipe_clk */
>>>>> - <0>, /* ufs_phy_rx_symbol_0_clk */
>>>>> - <0>, /* ufs_phy_rx_symbol_1_clk */
>>>>> - <0>, /* ufs_phy_tx_symbol_0_clk */
>>>>> + <&ufs_mem_phy 0>,
>>>>> + <&ufs_mem_phy 1>,
>>>>> + <&ufs_mem_phy 2>,
>>>>> <0>; /* usb3_phy_wrapper_gcc_usb30_pipe_clk */
>>>>> #clock-cells = <1>;
>>>>> @@ -1151,6 +1151,127 @@ aggre2_noc: interconnect@1700000 {
>>>>> qcom,bcm-voters = <&apps_bcm_voter>;
>>>>> };
>>>>> + ufs_mem_phy: phy@1d80000 {
>>>>> + compatible = "qcom,milos-qmp-ufs-phy";
>>>>> + reg = <0x0 0x01d80000 0x0 0x2000>;
>>>>> +
>>>>> + clocks = <&rpmhcc RPMH_CXO_CLK>,
>>>>> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
>>>>> + <&tcsr TCSR_UFS_CLKREF_EN>;
>>>>> + clock-names = "ref",
>>>>> + "ref_aux",
>>>>> + "qref";
>>>>> +
>>>>> + resets = <&ufs_mem_hc 0>;
>>>>> + reset-names = "ufsphy";
>>>>> +
>>>>> + power-domains = <&gcc UFS_MEM_PHY_GDSC>;
>>>>> +
>>>>> + #clock-cells = <1>;
>>>>> + #phy-cells = <0>;
>>>>> +
>>>>> + status = "disabled";
>>>>> + };
>>>>> +
>>>>> + ufs_mem_hc: ufshc@1d84000 {
>>>>> + compatible = "qcom,milos-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
>>>>> + reg = <0x0 0x01d84000 0x0 0x3000>;
>>>>> +
>>>>> + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
>>>>> +
>>>>> + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
>>>>> + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
>>>>> + <&gcc GCC_UFS_PHY_AHB_CLK>,
>>>>> + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
>>>>> + <&tcsr TCSR_UFS_PAD_CLKREF_EN>,
>>>>> + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
>>>>> + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
>>>>> + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
>>>>> + clock-names = "core_clk",
>>>>> + "bus_aggr_clk",
>>>>> + "iface_clk",
>>>>> + "core_clk_unipro",
>>>>> + "ref_clk",
>>>>> + "tx_lane0_sync_clk",
>>>>> + "rx_lane0_sync_clk",
>>>>> + "rx_lane1_sync_clk";
>>>>> +
>>>>> + resets = <&gcc GCC_UFS_PHY_BCR>;
>>>>> + reset-names = "rst";
>>>>> +
>>>>> + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
>>>>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>>>>> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
>>>>> + &cnoc_cfg SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
>>>>> + interconnect-names = "ufs-ddr",
>>>>> + "cpu-ufs";
>>>>> +
>>>>> + power-domains = <&gcc UFS_PHY_GDSC>;
>>>>> + required-opps = <&rpmhpd_opp_nom>;
>>>>> +
>>>>> + operating-points-v2 = <&ufs_opp_table>;
>>>>> +
>>>>> + iommus = <&apps_smmu 0x60 0>;
>>>>
>>>> dma-coherent ?
>>
>>
>> Given that downstream volcano.dtsi has dma-coherent in the ufshc@1d84000
>> node, looks like this is missing in my patch.
>
> Seems that way
>
>>>>
>>>> and no MCQ support ?
>>
>> Not sure, I could only find one reference to MCQ on createpoint for
>> milos, but given there's no mcq_sqd/mcq_vs reg defined downstream, and I
>> couldn't find anything for the same register values in the .FLAT file, I
>> don't think Milos has MCQ? Feel free to prove me wrong though.
>>
>>>
>>> So, people just ignore my comment ?
>>>
>>> Milos is based on SM8550, so it should have dma-coherent, for the MCQ
>>> I hope they used the fixed added to the SM8650 UFS controller for MCQ.
>>
>> Not sure what this should mean regarding MCQ...
>
> This platform doesn't support MCQ
Ack, it must be same situation as Kailua then,
Thanks
Neil
>
> Konrad
On 1/7/26 9:05 AM, Luca Weiss wrote: > Add the nodes for the UFS PHY and UFS host controller, along with the > ICE used for UFS. > > Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Konrad
On Wed, Jan 07, 2026 at 09:05:55AM +0100, Luca Weiss wrote: > Add the nodes for the UFS PHY and UFS host controller, along with the > ICE used for UFS. > > Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> > --- > arch/arm64/boot/dts/qcom/milos.dtsi | 127 +++++++++++++++++++++++++++++++++++- > 1 file changed, 124 insertions(+), 3 deletions(-) > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> -- With best wishes Dmitry
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