arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 36 ++++++++++++++++----------------- 1 file changed, 18 insertions(+), 18 deletions(-)
Remove Schmitt Trigger from mmc pins. With Schmitt Trigger enabled
u-boot SPL is not able to read u-boot from mmc:
Trying to boot from MMC2
Error reading cluster
spl_load_image_fat: error reading image u-boot.img, err - -22
Error: -22
SPL: Unsupported Boot Device!
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
I bisected this issue between u-boot v2025.10 and v2026.01 and found the
devicetree merge to be the problem. At a closer look I found the
k3-pinctrl.h changes. Disabling the Schmitt Trigger fixes the u-boot SPL
failure to read from mmc.
Fixes: 5b272127884b ("arm64: dts: ti: k3-pinctrl: Enable Schmitt Trigger by default")
Signed-off-by: Markus Schneider-Pargmann (TI.com) <msp@baylibre.com>
---
arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 36 ++++++++++++++++-----------------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
index e99bdbc2e0cbdf858f1631096f9c2a086191bab3..9129045c8bbd3a83dba6ff6f2148a3624b91b546 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
@@ -315,30 +315,30 @@ AM62AX_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
main_mmc0_pins_default: main-mmc0-default-pins {
pinctrl-single,pins = <
- AM62AX_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
- AM62AX_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLKLB */
- AM62AX_IOPAD(0x21c, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
- AM62AX_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */
- AM62AX_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */
- AM62AX_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */
- AM62AX_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */
- AM62AX_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */
- AM62AX_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */
- AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */
- AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */
+ AM62AX_IOPAD(0x220, PIN_INPUT_NOST, 0) /* (Y3) MMC0_CMD */
+ AM62AX_IOPAD(0x218, PIN_INPUT_NOST, 0) /* (AB1) MMC0_CLKLB */
+ AM62AX_IOPAD(0x21c, PIN_INPUT_NOST, 0) /* (AB1) MMC0_CLK */
+ AM62AX_IOPAD(0x214, PIN_INPUT_NOST, 0) /* (AA2) MMC0_DAT0 */
+ AM62AX_IOPAD(0x210, PIN_INPUT_PULLUP_NOST, 0) /* (AA1) MMC0_DAT1 */
+ AM62AX_IOPAD(0x20c, PIN_INPUT_PULLUP_NOST, 0) /* (AA3) MMC0_DAT2 */
+ AM62AX_IOPAD(0x208, PIN_INPUT_PULLUP_NOST, 0) /* (Y4) MMC0_DAT3 */
+ AM62AX_IOPAD(0x204, PIN_INPUT_PULLUP_NOST, 0) /* (AB2) MMC0_DAT4 */
+ AM62AX_IOPAD(0x200, PIN_INPUT_PULLUP_NOST, 0) /* (AC1) MMC0_DAT5 */
+ AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP_NOST, 0) /* (AD2) MMC0_DAT6 */
+ AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP_NOST, 0) /* (AC2) MMC0_DAT7 */
>;
bootph-all;
};
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
- AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
- AM62AX_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
- AM62AX_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */
- AM62AX_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */
- AM62AX_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */
- AM62AX_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */
- AM62AX_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */
+ AM62AX_IOPAD(0x23c, PIN_INPUT_NOST, 0) /* (A21) MMC1_CMD */
+ AM62AX_IOPAD(0x234, PIN_INPUT_NOST, 0) /* (B22) MMC1_CLK */
+ AM62AX_IOPAD(0x230, PIN_INPUT_NOST, 0) /* (A22) MMC1_DAT0 */
+ AM62AX_IOPAD(0x22c, PIN_INPUT_NOST, 0) /* (B21) MMC1_DAT1 */
+ AM62AX_IOPAD(0x228, PIN_INPUT_NOST, 0) /* (C21) MMC1_DAT2 */
+ AM62AX_IOPAD(0x224, PIN_INPUT_NOST, 0) /* (D22) MMC1_DAT3 */
+ AM62AX_IOPAD(0x240, PIN_INPUT_NOST, 0) /* (D17) MMC1_SDCD */
>;
bootph-all;
};
---
base-commit: 6cd6c12031130a349a098dbeb19d8c3070d2dfbe
change-id: 20260106-topic-am62a-mmc-pinctrl-v6-19-next-2f3e5563fbb5
Best regards,
--
Markus Schneider-Pargmann (TI.com) <msp@baylibre.com>On 1/6/26 10:22 AM, Markus Schneider-Pargmann (TI.com) wrote: > Remove Schmitt Trigger from mmc pins. With Schmitt Trigger enabled > u-boot SPL is not able to read u-boot from mmc: > > Trying to boot from MMC2 > Error reading cluster > spl_load_image_fat: error reading image u-boot.img, err - -22 > Error: -22 > SPL: Unsupported Boot Device! > SPL: failed to boot from all boot devices > ### ERROR ### Please RESET the board ### > > I bisected this issue between u-boot v2025.10 and v2026.01 and found the > devicetree merge to be the problem. At a closer look I found the > k3-pinctrl.h changes. Disabling the Schmitt Trigger fixes the u-boot SPL > failure to read from mmc. I have tested 4 AM62A SK boards and I cannot replicate the issue you are seeing. I do not see an issue with Schmitt Trigger in U-boot nor Linux /: Can you please run a quick tap sweep on MMC1 and MMC0 interfaces like so? https://gist.github.com/jmenti/f4a73a8323e44bf717c6d2c528c499ca This will give me an idea if whether we should be talking about revisiting characterization with ST_ENA=1. Also, are you able to replicate the issue on more than one board? Or is this the only board you see the issue on? ~ Judith
Hi Judith, On Tue Jan 13, 2026 at 1:29 AM CET, Judith Mendez wrote: > On 1/6/26 10:22 AM, Markus Schneider-Pargmann (TI.com) wrote: >> Remove Schmitt Trigger from mmc pins. With Schmitt Trigger enabled >> u-boot SPL is not able to read u-boot from mmc: >> >> Trying to boot from MMC2 >> Error reading cluster >> spl_load_image_fat: error reading image u-boot.img, err - -22 >> Error: -22 >> SPL: Unsupported Boot Device! >> SPL: failed to boot from all boot devices >> ### ERROR ### Please RESET the board ### >> >> I bisected this issue between u-boot v2025.10 and v2026.01 and found the >> devicetree merge to be the problem. At a closer look I found the >> k3-pinctrl.h changes. Disabling the Schmitt Trigger fixes the u-boot SPL >> failure to read from mmc. > > I have tested 4 AM62A SK boards and I cannot replicate the issue > you are seeing. I do not see an issue with Schmitt Trigger in U-boot > nor Linux /: Thanks for testing. > Can you please run a quick tap sweep on MMC1 and MMC0 interfaces like > so? https://gist.github.com/jmenti/f4a73a8323e44bf717c6d2c528c499ca > > This will give me an idea if whether we should be talking about > revisiting characterization with ST_ENA=1. The patch was a bit broken, but I think I managed to apply it to v2026.01 as it was supposed to be. (master currently doesn't boot even SPL, I don't have time right now to debug that). I attached the boot log. It does boot with your patch. Also can this be an issue with different SD cards? > Also, are you able to replicate the issue on more than one board? Or is > this the only board you see the issue on? I only have one am62a board here. Best Markus
Hi Markus, On 1/14/26 3:16 AM, Markus Schneider-Pargmann wrote: > Hi Judith, > > On Tue Jan 13, 2026 at 1:29 AM CET, Judith Mendez wrote: >> On 1/6/26 10:22 AM, Markus Schneider-Pargmann (TI.com) wrote: >>> Remove Schmitt Trigger from mmc pins. With Schmitt Trigger enabled >>> u-boot SPL is not able to read u-boot from mmc: >>> >>> Trying to boot from MMC2 >>> Error reading cluster >>> spl_load_image_fat: error reading image u-boot.img, err - -22 >>> Error: -22 >>> SPL: Unsupported Boot Device! >>> SPL: failed to boot from all boot devices >>> ### ERROR ### Please RESET the board ### >>> >>> I bisected this issue between u-boot v2025.10 and v2026.01 and found the >>> devicetree merge to be the problem. At a closer look I found the >>> k3-pinctrl.h changes. Disabling the Schmitt Trigger fixes the u-boot SPL >>> failure to read from mmc. >> >> I have tested 4 AM62A SK boards and I cannot replicate the issue >> you are seeing. I do not see an issue with Schmitt Trigger in U-boot >> nor Linux /: > > Thanks for testing. > >> Can you please run a quick tap sweep on MMC1 and MMC0 interfaces like >> so? https://gist.github.com/jmenti/f4a73a8323e44bf717c6d2c528c499ca >> >> This will give me an idea if whether we should be talking about >> revisiting characterization with ST_ENA=1. > > The patch was a bit broken, but I think I managed to apply it to > v2026.01 as it was supposed to be. (master currently doesn't boot even > SPL, I don't have time right now to debug that). as Nishanth, mentioned, master is missing two patches [0][1] > > I attached the boot log. It does boot with your patch. Also can this be > an issue with different SD cards? Something does not quite add up, Can you try the following 2 commands? # mmc dev 1 # md.w 0xfa0810c [0] https://gist.github.com/jmenti/92da6526e366e3f5cf41911724886471 [1] https://gist.github.com/jmenti/8cf589d0302248ad26da37128f622e98 ~ Judith
Hi Judith, On Wed Jan 14, 2026 at 11:04 PM CET, Judith Mendez wrote: > Hi Markus, > > On 1/14/26 3:16 AM, Markus Schneider-Pargmann wrote: >> Hi Judith, >> >> On Tue Jan 13, 2026 at 1:29 AM CET, Judith Mendez wrote: >>> On 1/6/26 10:22 AM, Markus Schneider-Pargmann (TI.com) wrote: >>>> Remove Schmitt Trigger from mmc pins. With Schmitt Trigger enabled >>>> u-boot SPL is not able to read u-boot from mmc: >>>> >>>> Trying to boot from MMC2 >>>> Error reading cluster >>>> spl_load_image_fat: error reading image u-boot.img, err - -22 >>>> Error: -22 >>>> SPL: Unsupported Boot Device! >>>> SPL: failed to boot from all boot devices >>>> ### ERROR ### Please RESET the board ### >>>> >>>> I bisected this issue between u-boot v2025.10 and v2026.01 and found the >>>> devicetree merge to be the problem. At a closer look I found the >>>> k3-pinctrl.h changes. Disabling the Schmitt Trigger fixes the u-boot SPL >>>> failure to read from mmc. >>> >>> I have tested 4 AM62A SK boards and I cannot replicate the issue >>> you are seeing. I do not see an issue with Schmitt Trigger in U-boot >>> nor Linux /: >> >> Thanks for testing. >> >>> Can you please run a quick tap sweep on MMC1 and MMC0 interfaces like >>> so? https://gist.github.com/jmenti/f4a73a8323e44bf717c6d2c528c499ca >>> >>> This will give me an idea if whether we should be talking about >>> revisiting characterization with ST_ENA=1. >> >> The patch was a bit broken, but I think I managed to apply it to >> v2026.01 as it was supposed to be. (master currently doesn't boot even >> SPL, I don't have time right now to debug that). > > as Nishanth, mentioned, master is missing two patches [0][1] > >> >> I attached the boot log. It does boot with your patch. Also can this be >> an issue with different SD cards? > > Something does not quite add up, > > Can you try the following 2 commands? > > # mmc dev 1 > # md.w 0xfa0810c Finally here is the output from boot and executing these commands. I am now on v2026.04-rc1 with your sweep patch. Best Markus U-Boot SPL 2026.04-rc1-00079-gcabaaffd0a79 (Feb 03 2026 - 11:12:52 +0100) SYSFW ABI: 4.0 (firmware rev 0x000b '11.2.5--v11.02.05 (Fancy Rat)') DM ABI: 3.0 (firmware ver 0x000b 'MSDK.11.02.00.11--v11.02.05' patch_ver: 5) Trying to boot from MMC2 j721e_4bit_sdhci_set_ios_post, mode=0, otap=0, itap=0 j721e_4bit_sdhci_set_ios_post, mode=0, otap=0, itap=0 j721e_4bit_sdhci_set_ios_post, mode=0, otap=0, itap=0 j721e_4bit_sdhci_set_ios_post, mode=0, otap=0, itap=0 j721e_4bit_sdhci_set_ios_post, mode=0, otap=0, itap=0 j721e_4bit_sdhci_set_ios_post, mode=0, otap=0, itap=0 j721e_4bit_sdhci_set_ios_post, mode=0, otap=0, itap=0 j721e_4bit_sdhci_set_ios_post, mode=0, otap=0, itap=0 j721e_4bit_sdhci_set_ios_post, mode=0, otap=0, itap=0 j721e_4bit_sdhci_set_ios_post, mode=0, otap=0, itap=0 j721e_4bit_sdhci_set_ios_post, mode=9, otap=6, itap=0 Begin Tuning am654_sdhci_write_itapdly, write itapdly=0 For otap=0, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=0, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=0, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=0, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=0, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=0, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=0, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=0, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=0, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=0, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=0, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=0, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=0, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=0, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=0, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=0, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=0, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=0, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=0, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=0, itap=19 :FAIL Failed otap=0, itap=19 am654_sdhci_write_itapdly, write itapdly=20 For otap=0, itap=20 :FAIL Failed otap=0, itap=20 am654_sdhci_write_itapdly, write itapdly=21 For otap=0, itap=21 :FAIL Failed otap=0, itap=21 am654_sdhci_write_itapdly, write itapdly=22 For otap=0, itap=22 :FAIL Failed otap=0, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=0, itap=23 :PASS am654_sdhci_write_itapdly, write itapdly=24 For otap=0, itap=24 :PASS am654_sdhci_write_itapdly, write itapdly=25 For otap=0, itap=25 :PASS am654_sdhci_write_itapdly, write itapdly=26 For otap=0, itap=26 :PASS am654_sdhci_write_itapdly, write itapdly=27 For otap=0, itap=27 :PASS am654_sdhci_write_itapdly, write itapdly=28 For otap=0, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=0, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=0, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=0, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=1, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=1, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=1, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=1, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=1, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=1, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=1, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=1, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=1, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=1, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=1, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=1, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=1, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=1, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=1, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=1, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=1, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=1, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=1, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=1, itap=19 :FAIL Failed otap=1, itap=19 am654_sdhci_write_itapdly, write itapdly=20 For otap=1, itap=20 :FAIL Failed otap=1, itap=20 am654_sdhci_write_itapdly, write itapdly=21 For otap=1, itap=21 :FAIL Failed otap=1, itap=21 am654_sdhci_write_itapdly, write itapdly=22 For otap=1, itap=22 :FAIL Failed otap=1, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=1, itap=23 :PASS am654_sdhci_write_itapdly, write itapdly=24 For otap=1, itap=24 :PASS am654_sdhci_write_itapdly, write itapdly=25 For otap=1, itap=25 :PASS am654_sdhci_write_itapdly, write itapdly=26 For otap=1, itap=26 :PASS am654_sdhci_write_itapdly, write itapdly=27 For otap=1, itap=27 :PASS am654_sdhci_write_itapdly, write itapdly=28 For otap=1, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=1, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=1, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=1, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=2, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=2, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=2, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=2, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=2, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=2, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=2, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=2, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=2, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=2, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=2, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=2, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=2, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=2, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=2, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=2, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=2, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=2, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=2, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=2, itap=19 :FAIL Failed otap=2, itap=19 am654_sdhci_write_itapdly, write itapdly=20 For otap=2, itap=20 :FAIL Failed otap=2, itap=20 am654_sdhci_write_itapdly, write itapdly=21 For otap=2, itap=21 :FAIL Failed otap=2, itap=21 am654_sdhci_write_itapdly, write itapdly=22 For otap=2, itap=22 :FAIL Failed otap=2, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=2, itap=23 :PASS am654_sdhci_write_itapdly, write itapdly=24 For otap=2, itap=24 :PASS am654_sdhci_write_itapdly, write itapdly=25 For otap=2, itap=25 :PASS am654_sdhci_write_itapdly, write itapdly=26 For otap=2, itap=26 :PASS am654_sdhci_write_itapdly, write itapdly=27 For otap=2, itap=27 :PASS am654_sdhci_write_itapdly, write itapdly=28 For otap=2, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=2, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=2, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=2, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=3, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=3, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=3, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=3, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=3, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=3, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=3, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=3, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=3, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=3, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=3, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=3, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=3, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=3, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=3, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=3, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=3, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=3, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=3, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=3, itap=19 :FAIL Failed otap=3, itap=19 am654_sdhci_write_itapdly, write itapdly=20 For otap=3, itap=20 :FAIL Failed otap=3, itap=20 am654_sdhci_write_itapdly, write itapdly=21 For otap=3, itap=21 :FAIL Failed otap=3, itap=21 am654_sdhci_write_itapdly, write itapdly=22 For otap=3, itap=22 :FAIL Failed otap=3, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=3, itap=23 :PASS am654_sdhci_write_itapdly, write itapdly=24 For otap=3, itap=24 :PASS am654_sdhci_write_itapdly, write itapdly=25 For otap=3, itap=25 :PASS am654_sdhci_write_itapdly, write itapdly=26 For otap=3, itap=26 :PASS am654_sdhci_write_itapdly, write itapdly=27 For otap=3, itap=27 :PASS am654_sdhci_write_itapdly, write itapdly=28 For otap=3, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=3, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=3, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=3, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=4, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=4, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=4, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=4, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=4, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=4, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=4, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=4, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=4, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=4, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=4, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=4, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=4, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=4, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=4, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=4, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=4, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=4, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=4, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=4, itap=19 :FAIL Failed otap=4, itap=19 am654_sdhci_write_itapdly, write itapdly=20 For otap=4, itap=20 :FAIL Failed otap=4, itap=20 am654_sdhci_write_itapdly, write itapdly=21 For otap=4, itap=21 :FAIL Failed otap=4, itap=21 am654_sdhci_write_itapdly, write itapdly=22 For otap=4, itap=22 :FAIL Failed otap=4, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=4, itap=23 :PASS am654_sdhci_write_itapdly, write itapdly=24 For otap=4, itap=24 :PASS am654_sdhci_write_itapdly, write itapdly=25 For otap=4, itap=25 :PASS am654_sdhci_write_itapdly, write itapdly=26 For otap=4, itap=26 :PASS am654_sdhci_write_itapdly, write itapdly=27 For otap=4, itap=27 :PASS am654_sdhci_write_itapdly, write itapdly=28 For otap=4, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=4, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=4, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=4, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=5, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=5, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=5, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=5, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=5, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=5, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=5, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=5, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=5, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=5, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=5, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=5, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=5, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=5, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=5, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=5, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=5, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=5, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=5, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=5, itap=19 :FAIL Failed otap=5, itap=19 am654_sdhci_write_itapdly, write itapdly=20 For otap=5, itap=20 :FAIL Failed otap=5, itap=20 am654_sdhci_write_itapdly, write itapdly=21 For otap=5, itap=21 :FAIL Failed otap=5, itap=21 am654_sdhci_write_itapdly, write itapdly=22 For otap=5, itap=22 :FAIL Failed otap=5, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=5, itap=23 :PASS am654_sdhci_write_itapdly, write itapdly=24 For otap=5, itap=24 :PASS am654_sdhci_write_itapdly, write itapdly=25 For otap=5, itap=25 :PASS am654_sdhci_write_itapdly, write itapdly=26 For otap=5, itap=26 :PASS am654_sdhci_write_itapdly, write itapdly=27 For otap=5, itap=27 :PASS am654_sdhci_write_itapdly, write itapdly=28 For otap=5, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=5, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=5, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=5, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=6, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=6, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=6, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=6, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=6, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=6, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=6, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=6, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=6, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=6, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=6, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=6, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=6, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=6, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=6, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=6, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=6, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=6, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=6, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=6, itap=19 :FAIL Failed otap=6, itap=19 am654_sdhci_write_itapdly, write itapdly=20 For otap=6, itap=20 :FAIL Failed otap=6, itap=20 am654_sdhci_write_itapdly, write itapdly=21 For otap=6, itap=21 :FAIL Failed otap=6, itap=21 am654_sdhci_write_itapdly, write itapdly=22 For otap=6, itap=22 :FAIL Failed otap=6, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=6, itap=23 :PASS am654_sdhci_write_itapdly, write itapdly=24 For otap=6, itap=24 :PASS am654_sdhci_write_itapdly, write itapdly=25 For otap=6, itap=25 :PASS am654_sdhci_write_itapdly, write itapdly=26 For otap=6, itap=26 :PASS am654_sdhci_write_itapdly, write itapdly=27 For otap=6, itap=27 :PASS am654_sdhci_write_itapdly, write itapdly=28 For otap=6, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=6, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=6, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=6, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=7, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=7, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=7, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=7, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=7, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=7, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=7, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=7, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=7, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=7, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=7, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=7, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=7, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=7, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=7, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=7, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=7, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=7, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=7, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=7, itap=19 :FAIL Failed otap=7, itap=19 am654_sdhci_write_itapdly, write itapdly=20 For otap=7, itap=20 :FAIL Failed otap=7, itap=20 am654_sdhci_write_itapdly, write itapdly=21 For otap=7, itap=21 :FAIL Failed otap=7, itap=21 am654_sdhci_write_itapdly, write itapdly=22 For otap=7, itap=22 :FAIL Failed otap=7, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=7, itap=23 :PASS am654_sdhci_write_itapdly, write itapdly=24 For otap=7, itap=24 :PASS am654_sdhci_write_itapdly, write itapdly=25 For otap=7, itap=25 :PASS am654_sdhci_write_itapdly, write itapdly=26 For otap=7, itap=26 :PASS am654_sdhci_write_itapdly, write itapdly=27 For otap=7, itap=27 :PASS am654_sdhci_write_itapdly, write itapdly=28 For otap=7, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=7, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=7, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=7, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=8, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=8, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=8, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=8, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=8, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=8, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=8, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=8, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=8, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=8, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=8, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=8, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=8, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=8, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=8, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=8, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=8, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=8, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=8, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=8, itap=19 :FAIL Failed otap=8, itap=19 am654_sdhci_write_itapdly, write itapdly=20 For otap=8, itap=20 :FAIL Failed otap=8, itap=20 am654_sdhci_write_itapdly, write itapdly=21 For otap=8, itap=21 :FAIL Failed otap=8, itap=21 am654_sdhci_write_itapdly, write itapdly=22 For otap=8, itap=22 :FAIL Failed otap=8, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=8, itap=23 :PASS am654_sdhci_write_itapdly, write itapdly=24 For otap=8, itap=24 :PASS am654_sdhci_write_itapdly, write itapdly=25 For otap=8, itap=25 :PASS am654_sdhci_write_itapdly, write itapdly=26 For otap=8, itap=26 :PASS am654_sdhci_write_itapdly, write itapdly=27 For otap=8, itap=27 :PASS am654_sdhci_write_itapdly, write itapdly=28 For otap=8, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=8, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=8, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=8, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=9, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=9, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=9, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=9, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=9, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=9, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=9, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=9, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=9, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=9, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=9, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=9, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=9, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=9, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=9, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=9, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=9, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=9, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=9, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=9, itap=19 :FAIL Failed otap=9, itap=19 am654_sdhci_write_itapdly, write itapdly=20 For otap=9, itap=20 :FAIL Failed otap=9, itap=20 am654_sdhci_write_itapdly, write itapdly=21 For otap=9, itap=21 :FAIL Failed otap=9, itap=21 am654_sdhci_write_itapdly, write itapdly=22 For otap=9, itap=22 :FAIL Failed otap=9, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=9, itap=23 :PASS am654_sdhci_write_itapdly, write itapdly=24 For otap=9, itap=24 :PASS am654_sdhci_write_itapdly, write itapdly=25 For otap=9, itap=25 :PASS am654_sdhci_write_itapdly, write itapdly=26 For otap=9, itap=26 :PASS am654_sdhci_write_itapdly, write itapdly=27 For otap=9, itap=27 :PASS am654_sdhci_write_itapdly, write itapdly=28 For otap=9, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=9, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=9, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=9, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=10, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=10, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=10, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=10, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=10, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=10, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=10, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=10, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=10, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=10, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=10, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=10, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=10, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=10, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=10, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=10, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=10, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=10, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=10, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=10, itap=19 :FAIL Failed otap=10, itap=19 am654_sdhci_write_itapdly, write itapdly=20 For otap=10, itap=20 :FAIL Failed otap=10, itap=20 am654_sdhci_write_itapdly, write itapdly=21 For otap=10, itap=21 :FAIL Failed otap=10, itap=21 am654_sdhci_write_itapdly, write itapdly=22 For otap=10, itap=22 :FAIL Failed otap=10, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=10, itap=23 :PASS am654_sdhci_write_itapdly, write itapdly=24 For otap=10, itap=24 :PASS am654_sdhci_write_itapdly, write itapdly=25 For otap=10, itap=25 :PASS am654_sdhci_write_itapdly, write itapdly=26 For otap=10, itap=26 :PASS am654_sdhci_write_itapdly, write itapdly=27 For otap=10, itap=27 :PASS am654_sdhci_write_itapdly, write itapdly=28 For otap=10, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=10, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=10, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=10, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=11, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=11, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=11, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=11, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=11, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=11, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=11, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=11, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=11, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=11, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=11, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=11, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=11, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=11, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=11, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=11, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=11, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=11, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=11, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=11, itap=19 :FAIL Failed otap=11, itap=19 am654_sdhci_write_itapdly, write itapdly=20 For otap=11, itap=20 :FAIL Failed otap=11, itap=20 am654_sdhci_write_itapdly, write itapdly=21 For otap=11, itap=21 :FAIL Failed otap=11, itap=21 am654_sdhci_write_itapdly, write itapdly=22 For otap=11, itap=22 :FAIL Failed otap=11, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=11, itap=23 :PASS am654_sdhci_write_itapdly, write itapdly=24 For otap=11, itap=24 :PASS am654_sdhci_write_itapdly, write itapdly=25 For otap=11, itap=25 :PASS am654_sdhci_write_itapdly, write itapdly=26 For otap=11, itap=26 :PASS am654_sdhci_write_itapdly, write itapdly=27 For otap=11, itap=27 :PASS am654_sdhci_write_itapdly, write itapdly=28 For otap=11, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=11, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=11, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=11, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=12, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=12, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=12, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=12, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=12, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=12, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=12, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=12, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=12, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=12, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=12, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=12, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=12, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=12, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=12, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=12, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=12, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=12, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=12, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=12, itap=19 :FAIL Failed otap=12, itap=19 am654_sdhci_write_itapdly, write itapdly=20 For otap=12, itap=20 :FAIL Failed otap=12, itap=20 am654_sdhci_write_itapdly, write itapdly=21 For otap=12, itap=21 :FAIL Failed otap=12, itap=21 am654_sdhci_write_itapdly, write itapdly=22 For otap=12, itap=22 :FAIL Failed otap=12, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=12, itap=23 :PASS am654_sdhci_write_itapdly, write itapdly=24 For otap=12, itap=24 :PASS am654_sdhci_write_itapdly, write itapdly=25 For otap=12, itap=25 :PASS am654_sdhci_write_itapdly, write itapdly=26 For otap=12, itap=26 :PASS am654_sdhci_write_itapdly, write itapdly=27 For otap=12, itap=27 :PASS am654_sdhci_write_itapdly, write itapdly=28 For otap=12, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=12, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=12, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=12, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=13, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=13, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=13, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=13, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=13, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=13, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=13, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=13, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=13, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=13, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=13, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=13, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=13, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=13, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=13, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=13, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=13, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=13, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=13, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=13, itap=19 :FAIL Failed otap=13, itap=19 am654_sdhci_write_itapdly, write itapdly=20 For otap=13, itap=20 :FAIL Failed otap=13, itap=20 am654_sdhci_write_itapdly, write itapdly=21 For otap=13, itap=21 :FAIL Failed otap=13, itap=21 am654_sdhci_write_itapdly, write itapdly=22 For otap=13, itap=22 :FAIL Failed otap=13, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=13, itap=23 :PASS am654_sdhci_write_itapdly, write itapdly=24 For otap=13, itap=24 :PASS am654_sdhci_write_itapdly, write itapdly=25 For otap=13, itap=25 :PASS am654_sdhci_write_itapdly, write itapdly=26 For otap=13, itap=26 :PASS am654_sdhci_write_itapdly, write itapdly=27 For otap=13, itap=27 :PASS am654_sdhci_write_itapdly, write itapdly=28 For otap=13, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=13, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=13, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=13, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=14, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=14, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=14, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=14, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=14, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=14, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=14, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=14, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=14, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=14, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=14, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=14, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=14, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=14, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=14, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=14, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=14, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=14, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=14, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=14, itap=19 :FAIL Failed otap=14, itap=19 am654_sdhci_write_itapdly, write itapdly=20 For otap=14, itap=20 :FAIL Failed otap=14, itap=20 am654_sdhci_write_itapdly, write itapdly=21 For otap=14, itap=21 :FAIL Failed otap=14, itap=21 am654_sdhci_write_itapdly, write itapdly=22 For otap=14, itap=22 :FAIL Failed otap=14, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=14, itap=23 :PASS am654_sdhci_write_itapdly, write itapdly=24 For otap=14, itap=24 :PASS am654_sdhci_write_itapdly, write itapdly=25 For otap=14, itap=25 :PASS am654_sdhci_write_itapdly, write itapdly=26 For otap=14, itap=26 :PASS am654_sdhci_write_itapdly, write itapdly=27 For otap=14, itap=27 :PASS am654_sdhci_write_itapdly, write itapdly=28 For otap=14, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=14, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=14, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=14, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=15, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=15, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=15, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=15, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=15, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=15, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=15, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=15, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=15, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=15, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=15, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=15, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=15, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=15, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=15, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=15, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=15, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=15, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=15, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=15, itap=19 :FAIL Failed otap=15, itap=19 am654_sdhci_write_itapdly, write itapdly=20 For otap=15, itap=20 :FAIL Failed otap=15, itap=20 am654_sdhci_write_itapdly, write itapdly=21 For otap=15, itap=21 :FAIL Failed otap=15, itap=21 am654_sdhci_write_itapdly, write itapdly=22 For otap=15, itap=22 :FAIL Failed otap=15, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=15, itap=23 :PASS am654_sdhci_write_itapdly, write itapdly=24 For otap=15, itap=24 :PASS am654_sdhci_write_itapdly, write itapdly=25 For otap=15, itap=25 :PASS am654_sdhci_write_itapdly, write itapdly=26 For otap=15, itap=26 :PASS am654_sdhci_write_itapdly, write itapdly=27 For otap=15, itap=27 :PASS am654_sdhci_write_itapdly, write itapdly=28 For otap=15, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=15, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=15, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=15, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=16, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=16, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=16, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=16, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=16, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=16, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=16, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=16, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=16, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=16, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=16, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=16, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=16, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=16, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=16, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=16, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=16, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=16, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=16, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=16, itap=19 :FAIL Failed otap=16, itap=19 am654_sdhci_write_itapdly, write itapdly=20 For otap=16, itap=20 :FAIL Failed otap=16, itap=20 am654_sdhci_write_itapdly, write itapdly=21 For otap=16, itap=21 :FAIL Failed otap=16, itap=21 am654_sdhci_write_itapdly, write itapdly=22 For otap=16, itap=22 :FAIL Failed otap=16, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=16, itap=23 :PASS am654_sdhci_write_itapdly, write itapdly=24 For otap=16, itap=24 :PASS am654_sdhci_write_itapdly, write itapdly=25 For otap=16, itap=25 :PASS am654_sdhci_write_itapdly, write itapdly=26 For otap=16, itap=26 :PASS am654_sdhci_write_itapdly, write itapdly=27 For otap=16, itap=27 :PASS am654_sdhci_write_itapdly, write itapdly=28 For otap=16, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=16, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=16, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=16, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=17, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=17, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=17, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=17, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=17, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=17, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=17, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=17, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=17, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=17, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=17, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=17, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=17, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=17, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=17, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=17, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=17, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=17, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=17, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=17, itap=19 :FAIL Failed otap=17, itap=19 am654_sdhci_write_itapdly, write itapdly=20 For otap=17, itap=20 :FAIL Failed otap=17, itap=20 am654_sdhci_write_itapdly, write itapdly=21 For otap=17, itap=21 :FAIL Failed otap=17, itap=21 am654_sdhci_write_itapdly, write itapdly=22 For otap=17, itap=22 :FAIL Failed otap=17, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=17, itap=23 :PASS am654_sdhci_write_itapdly, write itapdly=24 For otap=17, itap=24 :PASS am654_sdhci_write_itapdly, write itapdly=25 For otap=17, itap=25 :PASS am654_sdhci_write_itapdly, write itapdly=26 For otap=17, itap=26 :PASS am654_sdhci_write_itapdly, write itapdly=27 For otap=17, itap=27 :PASS am654_sdhci_write_itapdly, write itapdly=28 For otap=17, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=17, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=17, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=17, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=18, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=18, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=18, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=18, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=18, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=18, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=18, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=18, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=18, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=18, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=18, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=18, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=18, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=18, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=18, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=18, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=18, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=18, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=18, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=18, itap=19 :FAIL Failed otap=18, itap=19 am654_sdhci_write_itapdly, write itapdly=20 For otap=18, itap=20 :FAIL Failed otap=18, itap=20 am654_sdhci_write_itapdly, write itapdly=21 For otap=18, itap=21 :FAIL Failed otap=18, itap=21 am654_sdhci_write_itapdly, write itapdly=22 For otap=18, itap=22 :FAIL Failed otap=18, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=18, itap=23 :PASS am654_sdhci_write_itapdly, write itapdly=24 For otap=18, itap=24 :PASS am654_sdhci_write_itapdly, write itapdly=25 For otap=18, itap=25 :PASS am654_sdhci_write_itapdly, write itapdly=26 For otap=18, itap=26 :PASS am654_sdhci_write_itapdly, write itapdly=27 For otap=18, itap=27 :PASS am654_sdhci_write_itapdly, write itapdly=28 For otap=18, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=18, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=18, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=18, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=19, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=19, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=19, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=19, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=19, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=19, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=19, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=19, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=19, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=19, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=19, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=19, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=19, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=19, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=19, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=19, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=19, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=19, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=19, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=19, itap=19 :FAIL Failed otap=19, itap=19 am654_sdhci_write_itapdly, write itapdly=20 For otap=19, itap=20 :FAIL Failed otap=19, itap=20 am654_sdhci_write_itapdly, write itapdly=21 For otap=19, itap=21 :FAIL Failed otap=19, itap=21 am654_sdhci_write_itapdly, write itapdly=22 For otap=19, itap=22 :FAIL Failed otap=19, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=19, itap=23 :PASS am654_sdhci_write_itapdly, write itapdly=24 For otap=19, itap=24 :PASS am654_sdhci_write_itapdly, write itapdly=25 For otap=19, itap=25 :PASS am654_sdhci_write_itapdly, write itapdly=26 For otap=19, itap=26 :PASS am654_sdhci_write_itapdly, write itapdly=27 For otap=19, itap=27 :PASS am654_sdhci_write_itapdly, write itapdly=28 For otap=19, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=19, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=19, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=19, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=20, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=20, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=20, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=20, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=20, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=20, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=20, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=20, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=20, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=20, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=20, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=20, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=20, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=20, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=20, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=20, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=20, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=20, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=20, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=20, itap=19 :FAIL Failed otap=20, itap=19 am654_sdhci_write_itapdly, write itapdly=20 For otap=20, itap=20 :FAIL Failed otap=20, itap=20 am654_sdhci_write_itapdly, write itapdly=21 For otap=20, itap=21 :FAIL Failed otap=20, itap=21 am654_sdhci_write_itapdly, write itapdly=22 For otap=20, itap=22 :FAIL Failed otap=20, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=20, itap=23 :PASS am654_sdhci_write_itapdly, write itapdly=24 For otap=20, itap=24 :PASS am654_sdhci_write_itapdly, write itapdly=25 For otap=20, itap=25 :PASS am654_sdhci_write_itapdly, write itapdly=26 For otap=20, itap=26 :PASS am654_sdhci_write_itapdly, write itapdly=27 For otap=20, itap=27 :PASS am654_sdhci_write_itapdly, write itapdly=28 For otap=20, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=20, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=20, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=20, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=21, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=21, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=21, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=21, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=21, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=21, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=21, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=21, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=21, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=21, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=21, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=21, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=21, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=21, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=21, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=21, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=21, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=21, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=21, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=21, itap=19 :FAIL Failed otap=21, itap=19 am654_sdhci_write_itapdly, write itapdly=20 For otap=21, itap=20 :FAIL Failed otap=21, itap=20 am654_sdhci_write_itapdly, write itapdly=21 For otap=21, itap=21 :FAIL Failed otap=21, itap=21 am654_sdhci_write_itapdly, write itapdly=22 For otap=21, itap=22 :FAIL Failed otap=21, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=21, itap=23 :PASS am654_sdhci_write_itapdly, write itapdly=24 For otap=21, itap=24 :PASS am654_sdhci_write_itapdly, write itapdly=25 For otap=21, itap=25 :PASS am654_sdhci_write_itapdly, write itapdly=26 For otap=21, itap=26 :PASS am654_sdhci_write_itapdly, write itapdly=27 For otap=21, itap=27 :PASS am654_sdhci_write_itapdly, write itapdly=28 For otap=21, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=21, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=21, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=21, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=22, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=22, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=22, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=22, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=22, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=22, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=22, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=22, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=22, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=22, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=22, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=22, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=22, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=22, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=22, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=22, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=22, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=22, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=22, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=22, itap=19 :FAIL Failed otap=22, itap=19 am654_sdhci_write_itapdly, write itapdly=20 For otap=22, itap=20 :FAIL Failed otap=22, itap=20 am654_sdhci_write_itapdly, write itapdly=21 For otap=22, itap=21 :FAIL Failed otap=22, itap=21 am654_sdhci_write_itapdly, write itapdly=22 For otap=22, itap=22 :FAIL Failed otap=22, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=22, itap=23 :PASS am654_sdhci_write_itapdly, write itapdly=24 For otap=22, itap=24 :PASS am654_sdhci_write_itapdly, write itapdly=25 For otap=22, itap=25 :PASS am654_sdhci_write_itapdly, write itapdly=26 For otap=22, itap=26 :PASS am654_sdhci_write_itapdly, write itapdly=27 For otap=22, itap=27 :PASS am654_sdhci_write_itapdly, write itapdly=28 For otap=22, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=22, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=22, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=22, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=23, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=23, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=23, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=23, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=23, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=23, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=23, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=23, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=23, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=23, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=23, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=23, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=23, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=23, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=23, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=23, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=23, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=23, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=23, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=23, itap=19 :FAIL Failed otap=23, itap=19 am654_sdhci_write_itapdly, write itapdly=20 For otap=23, itap=20 :FAIL Failed otap=23, itap=20 am654_sdhci_write_itapdly, write itapdly=21 For otap=23, itap=21 :FAIL Failed otap=23, itap=21 am654_sdhci_write_itapdly, write itapdly=22 For otap=23, itap=22 :FAIL Failed otap=23, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=23, itap=23 :PASS am654_sdhci_write_itapdly, write itapdly=24 For otap=23, itap=24 :PASS am654_sdhci_write_itapdly, write itapdly=25 For otap=23, itap=25 :PASS am654_sdhci_write_itapdly, write itapdly=26 For otap=23, itap=26 :PASS am654_sdhci_write_itapdly, write itapdly=27 For otap=23, itap=27 :PASS am654_sdhci_write_itapdly, write itapdly=28 For otap=23, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=23, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=23, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=23, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=24, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=24, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=24, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=24, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=24, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=24, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=24, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=24, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=24, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=24, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=24, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=24, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=24, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=24, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=24, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=24, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=24, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=24, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=24, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=24, itap=19 :FAIL Failed otap=24, itap=19 am654_sdhci_write_itapdly, write itapdly=20 For otap=24, itap=20 :FAIL Failed otap=24, itap=20 am654_sdhci_write_itapdly, write itapdly=21 For otap=24, itap=21 :FAIL Failed otap=24, itap=21 am654_sdhci_write_itapdly, write itapdly=22 For otap=24, itap=22 :FAIL Failed otap=24, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=24, itap=23 :PASS am654_sdhci_write_itapdly, write itapdly=24 For otap=24, itap=24 :PASS am654_sdhci_write_itapdly, write itapdly=25 For otap=24, itap=25 :PASS am654_sdhci_write_itapdly, write itapdly=26 For otap=24, itap=26 :PASS am654_sdhci_write_itapdly, write itapdly=27 For otap=24, itap=27 :PASS am654_sdhci_write_itapdly, write itapdly=28 For otap=24, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=24, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=24, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=24, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=25, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=25, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=25, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=25, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=25, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=25, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=25, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=25, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=25, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=25, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=25, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=25, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=25, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=25, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=25, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=25, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=25, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=25, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=25, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=25, itap=19 :FAIL Failed otap=25, itap=19 am654_sdhci_write_itapdly, write itapdly=20 For otap=25, itap=20 :FAIL Failed otap=25, itap=20 am654_sdhci_write_itapdly, write itapdly=21 For otap=25, itap=21 :FAIL Failed otap=25, itap=21 am654_sdhci_write_itapdly, write itapdly=22 For otap=25, itap=22 :FAIL Failed otap=25, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=25, itap=23 :PASS am654_sdhci_write_itapdly, write itapdly=24 For otap=25, itap=24 :PASS am654_sdhci_write_itapdly, write itapdly=25 For otap=25, itap=25 :PASS am654_sdhci_write_itapdly, write itapdly=26 For otap=25, itap=26 :PASS am654_sdhci_write_itapdly, write itapdly=27 For otap=25, itap=27 :PASS am654_sdhci_write_itapdly, write itapdly=28 For otap=25, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=25, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=25, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=25, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=26, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=26, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=26, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=26, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=26, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=26, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=26, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=26, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=26, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=26, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=26, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=26, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=26, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=26, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=26, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=26, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=26, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=26, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=26, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=26, itap=19 :FAIL Failed otap=26, itap=19 am654_sdhci_write_itapdly, write itapdly=20 For otap=26, itap=20 :FAIL Failed otap=26, itap=20 am654_sdhci_write_itapdly, write itapdly=21 For otap=26, itap=21 :FAIL Failed otap=26, itap=21 am654_sdhci_write_itapdly, write itapdly=22 For otap=26, itap=22 :FAIL Failed otap=26, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=26, itap=23 :PASS am654_sdhci_write_itapdly, write itapdly=24 For otap=26, itap=24 :PASS am654_sdhci_write_itapdly, write itapdly=25 For otap=26, itap=25 :PASS am654_sdhci_write_itapdly, write itapdly=26 For otap=26, itap=26 :PASS am654_sdhci_write_itapdly, write itapdly=27 For otap=26, itap=27 :PASS am654_sdhci_write_itapdly, write itapdly=28 For otap=26, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=26, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=26, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=26, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=27, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=27, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=27, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=27, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=27, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=27, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=27, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=27, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=27, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=27, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=27, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=27, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=27, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=27, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=27, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=27, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=27, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=27, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=27, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=27, itap=19 :FAIL Failed otap=27, itap=19 am654_sdhci_write_itapdly, write itapdly=20 For otap=27, itap=20 :FAIL Failed otap=27, itap=20 am654_sdhci_write_itapdly, write itapdly=21 For otap=27, itap=21 :FAIL Failed otap=27, itap=21 am654_sdhci_write_itapdly, write itapdly=22 For otap=27, itap=22 :FAIL Failed otap=27, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=27, itap=23 :PASS am654_sdhci_write_itapdly, write itapdly=24 For otap=27, itap=24 :PASS am654_sdhci_write_itapdly, write itapdly=25 For otap=27, itap=25 :PASS am654_sdhci_write_itapdly, write itapdly=26 For otap=27, itap=26 :PASS am654_sdhci_write_itapdly, write itapdly=27 For otap=27, itap=27 :PASS am654_sdhci_write_itapdly, write itapdly=28 For otap=27, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=27, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=27, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=27, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=28, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=28, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=28, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=28, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=28, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=28, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=28, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=28, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=28, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=28, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=28, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=28, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=28, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=28, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=28, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=28, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=28, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=28, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=28, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=28, itap=19 :FAIL Failed otap=28, itap=19 am654_sdhci_write_itapdly, write itapdly=20 For otap=28, itap=20 :FAIL Failed otap=28, itap=20 am654_sdhci_write_itapdly, write itapdly=21 For otap=28, itap=21 :FAIL Failed otap=28, itap=21 am654_sdhci_write_itapdly, write itapdly=22 For otap=28, itap=22 :FAIL Failed otap=28, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=28, itap=23 :PASS am654_sdhci_write_itapdly, write itapdly=24 For otap=28, itap=24 :PASS am654_sdhci_write_itapdly, write itapdly=25 For otap=28, itap=25 :PASS am654_sdhci_write_itapdly, write itapdly=26 For otap=28, itap=26 :PASS am654_sdhci_write_itapdly, write itapdly=27 For otap=28, itap=27 :PASS am654_sdhci_write_itapdly, write itapdly=28 For otap=28, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=28, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=28, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=28, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=29, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=29, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=29, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=29, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=29, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=29, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=29, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=29, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=29, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=29, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=29, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=29, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=29, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=29, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=29, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=29, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=29, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=29, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=29, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=29, itap=19 :FAIL Failed otap=29, itap=19 am654_sdhci_write_itapdly, write itapdly=20 For otap=29, itap=20 :FAIL Failed otap=29, itap=20 am654_sdhci_write_itapdly, write itapdly=21 For otap=29, itap=21 :FAIL Failed otap=29, itap=21 am654_sdhci_write_itapdly, write itapdly=22 For otap=29, itap=22 :FAIL Failed otap=29, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=29, itap=23 :PASS am654_sdhci_write_itapdly, write itapdly=24 For otap=29, itap=24 :PASS am654_sdhci_write_itapdly, write itapdly=25 For otap=29, itap=25 :PASS am654_sdhci_write_itapdly, write itapdly=26 For otap=29, itap=26 :PASS am654_sdhci_write_itapdly, write itapdly=27 For otap=29, itap=27 :PASS am654_sdhci_write_itapdly, write itapdly=28 For otap=29, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=29, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=29, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=29, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=30, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=30, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=30, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=30, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=30, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=30, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=30, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=30, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=30, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=30, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=30, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=30, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=30, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=30, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=30, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=30, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=30, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=30, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=30, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=30, itap=19 :FAIL Failed otap=30, itap=19 am654_sdhci_write_itapdly, write itapdly=20 For otap=30, itap=20 :FAIL Failed otap=30, itap=20 am654_sdhci_write_itapdly, write itapdly=21 For otap=30, itap=21 :FAIL Failed otap=30, itap=21 am654_sdhci_write_itapdly, write itapdly=22 For otap=30, itap=22 :FAIL Failed otap=30, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=30, itap=23 :PASS am654_sdhci_write_itapdly, write itapdly=24 For otap=30, itap=24 :PASS am654_sdhci_write_itapdly, write itapdly=25 For otap=30, itap=25 :PASS am654_sdhci_write_itapdly, write itapdly=26 For otap=30, itap=26 :PASS am654_sdhci_write_itapdly, write itapdly=27 For otap=30, itap=27 :PASS am654_sdhci_write_itapdly, write itapdly=28 For otap=30, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=30, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=30, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=30, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=31, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=31, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=31, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=31, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=31, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=31, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=31, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=31, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=31, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=31, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=31, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=31, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=31, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=31, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=31, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=31, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=31, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=31, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=31, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=31, itap=19 :FAIL Failed otap=31, itap=19 am654_sdhci_write_itapdly, write itapdly=20 For otap=31, itap=20 :FAIL Failed otap=31, itap=20 am654_sdhci_write_itapdly, write itapdly=21 For otap=31, itap=21 :FAIL Failed otap=31, itap=21 am654_sdhci_write_itapdly, write itapdly=22 For otap=31, itap=22 :FAIL Failed otap=31, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=31, itap=23 :PASS am654_sdhci_write_itapdly, write itapdly=24 For otap=31, itap=24 :PASS am654_sdhci_write_itapdly, write itapdly=25 For otap=31, itap=25 :PASS am654_sdhci_write_itapdly, write itapdly=26 For otap=31, itap=26 :PASS am654_sdhci_write_itapdly, write itapdly=27 For otap=31, itap=27 :PASS am654_sdhci_write_itapdly, write itapdly=28 For otap=31, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=31, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=31, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=31, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=15 Authentication passed Authentication passed U-Boot 2026.04-rc1-00079-gcabaaffd0a79 (Feb 03 2026 - 11:12:52 +0100) SoC: AM62AX SR1.0 HS-FS Model: Texas Instruments AM62A7 SK DRAM: 2 GiB (total 4 GiB) optee optee: OP-TEE api uid mismatch Core: 90 devices, 30 uclasses, devicetree: separate MMC: mmc@fa10000: 0, mmc@fa00000: 1 Loading Environment from nowhere... OK In: serial@2800000 Out: serial@2800000 Err: serial@2800000 Net: eth0: ethernet@8000000port@1 [2K Hit any key to stop autoboot: 2[2K Hit any key to stop autoboot: 0 => => => mmc dev 1 j721e_4bit_sdhci_set_ios_post, mode=0, otap=0, itap=0 j721e_4bit_sdhci_set_ios_post, mode=0, otap=0, itap=0 j721e_4bit_sdhci_set_ios_post, mode=0, otap=0, itap=0 j721e_4bit_sdhci_set_ios_post, mode=0, otap=0, itap=0 j721e_4bit_sdhci_set_ios_post, mode=0, otap=0, itap=0 j721e_4bit_sdhci_set_ios_post, mode=0, otap=0, itap=0 j721e_4bit_sdhci_set_ios_post, mode=0, otap=0, itap=0 j721e_4bit_sdhci_set_ios_post, mode=0, otap=0, itap=0 j721e_4bit_sdhci_set_ios_post, mode=0, otap=0, itap=0 j721e_4bit_sdhci_set_ios_post, mode=0, otap=0, itap=0 j721e_4bit_sdhci_set_ios_post, mode=9, otap=6, itap=0 Begin Tuning am654_sdhci_write_itapdly, write itapdly=0 For otap=0, itap=0 :FAIL Failed otap=0, itap=0 am654_sdhci_write_itapdly, write itapdly=1 For otap=0, itap=1 :FAIL Failed otap=0, itap=1 am654_sdhci_write_itapdly, write itapdly=2 For otap=0, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=0, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=0, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=0, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=0, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=0, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=0, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=0, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=0, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=0, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=0, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=0, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=0, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=0, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=0, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=0, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=0, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=0, itap=19 :PASS am654_sdhci_write_itapdly, write itapdly=20 For otap=0, itap=20 :PASS am654_sdhci_write_itapdly, write itapdly=21 For otap=0, itap=21 :PASS am654_sdhci_write_itapdly, write itapdly=22 For otap=0, itap=22 :FAIL Failed otap=0, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=0, itap=23 :FAIL Failed otap=0, itap=23 am654_sdhci_write_itapdly, write itapdly=24 For otap=0, itap=24 :FAIL Failed otap=0, itap=24 am654_sdhci_write_itapdly, write itapdly=25 For otap=0, itap=25 :FAIL Failed otap=0, itap=25 am654_sdhci_write_itapdly, write itapdly=26 For otap=0, itap=26 :FAIL Failed otap=0, itap=26 am654_sdhci_write_itapdly, write itapdly=27 For otap=0, itap=27 :FAIL Failed otap=0, itap=27 am654_sdhci_write_itapdly, write itapdly=28 For otap=0, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=0, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=0, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=0, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=1, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=1, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=1, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=1, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=1, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=1, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=1, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=1, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=1, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=1, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=1, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=1, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=1, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=1, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=1, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=1, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=1, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=1, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=1, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=1, itap=19 :PASS am654_sdhci_write_itapdly, write itapdly=20 For otap=1, itap=20 :PASS am654_sdhci_write_itapdly, write itapdly=21 For otap=1, itap=21 :PASS am654_sdhci_write_itapdly, write itapdly=22 For otap=1, itap=22 :FAIL Failed otap=1, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=1, itap=23 :FAIL Failed otap=1, itap=23 am654_sdhci_write_itapdly, write itapdly=24 For otap=1, itap=24 :FAIL Failed otap=1, itap=24 am654_sdhci_write_itapdly, write itapdly=25 For otap=1, itap=25 :FAIL Failed otap=1, itap=25 am654_sdhci_write_itapdly, write itapdly=26 For otap=1, itap=26 :FAIL Failed otap=1, itap=26 am654_sdhci_write_itapdly, write itapdly=27 For otap=1, itap=27 :FAIL Failed otap=1, itap=27 am654_sdhci_write_itapdly, write itapdly=28 For otap=1, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=1, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=1, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=1, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=2, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=2, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=2, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=2, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=2, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=2, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=2, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=2, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=2, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=2, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=2, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=2, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=2, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=2, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=2, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=2, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=2, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=2, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=2, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=2, itap=19 :PASS am654_sdhci_write_itapdly, write itapdly=20 For otap=2, itap=20 :PASS am654_sdhci_write_itapdly, write itapdly=21 For otap=2, itap=21 :PASS am654_sdhci_write_itapdly, write itapdly=22 For otap=2, itap=22 :PASS am654_sdhci_write_itapdly, write itapdly=23 For otap=2, itap=23 :FAIL Failed otap=2, itap=23 am654_sdhci_write_itapdly, write itapdly=24 For otap=2, itap=24 :FAIL Failed otap=2, itap=24 am654_sdhci_write_itapdly, write itapdly=25 For otap=2, itap=25 :FAIL Failed otap=2, itap=25 am654_sdhci_write_itapdly, write itapdly=26 For otap=2, itap=26 :FAIL Failed otap=2, itap=26 am654_sdhci_write_itapdly, write itapdly=27 For otap=2, itap=27 :FAIL Failed otap=2, itap=27 am654_sdhci_write_itapdly, write itapdly=28 For otap=2, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=2, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=2, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=2, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=3, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=3, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=3, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=3, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=3, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=3, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=3, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=3, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=3, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=3, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=3, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=3, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=3, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=3, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=3, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=3, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=3, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=3, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=3, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=3, itap=19 :PASS am654_sdhci_write_itapdly, write itapdly=20 For otap=3, itap=20 :PASS am654_sdhci_write_itapdly, write itapdly=21 For otap=3, itap=21 :PASS am654_sdhci_write_itapdly, write itapdly=22 For otap=3, itap=22 :PASS am654_sdhci_write_itapdly, write itapdly=23 For otap=3, itap=23 :FAIL Failed otap=3, itap=23 am654_sdhci_write_itapdly, write itapdly=24 For otap=3, itap=24 :FAIL Failed otap=3, itap=24 am654_sdhci_write_itapdly, write itapdly=25 For otap=3, itap=25 :FAIL Failed otap=3, itap=25 am654_sdhci_write_itapdly, write itapdly=26 For otap=3, itap=26 :FAIL Failed otap=3, itap=26 am654_sdhci_write_itapdly, write itapdly=27 For otap=3, itap=27 :FAIL Failed otap=3, itap=27 am654_sdhci_write_itapdly, write itapdly=28 For otap=3, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=3, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=3, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=3, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=4, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=4, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=4, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=4, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=4, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=4, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=4, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=4, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=4, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=4, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=4, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=4, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=4, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=4, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=4, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=4, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=4, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=4, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=4, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=4, itap=19 :PASS am654_sdhci_write_itapdly, write itapdly=20 For otap=4, itap=20 :PASS am654_sdhci_write_itapdly, write itapdly=21 For otap=4, itap=21 :PASS am654_sdhci_write_itapdly, write itapdly=22 For otap=4, itap=22 :PASS am654_sdhci_write_itapdly, write itapdly=23 For otap=4, itap=23 :FAIL Failed otap=4, itap=23 am654_sdhci_write_itapdly, write itapdly=24 For otap=4, itap=24 :FAIL Failed otap=4, itap=24 am654_sdhci_write_itapdly, write itapdly=25 For otap=4, itap=25 :FAIL Failed otap=4, itap=25 am654_sdhci_write_itapdly, write itapdly=26 For otap=4, itap=26 :FAIL Failed otap=4, itap=26 am654_sdhci_write_itapdly, write itapdly=27 For otap=4, itap=27 :FAIL Failed otap=4, itap=27 am654_sdhci_write_itapdly, write itapdly=28 For otap=4, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=4, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=4, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=4, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=5, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=5, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=5, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=5, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=5, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=5, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=5, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=5, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=5, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=5, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=5, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=5, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=5, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=5, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=5, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=5, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=5, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=5, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=5, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=5, itap=19 :PASS am654_sdhci_write_itapdly, write itapdly=20 For otap=5, itap=20 :PASS am654_sdhci_write_itapdly, write itapdly=21 For otap=5, itap=21 :PASS am654_sdhci_write_itapdly, write itapdly=22 For otap=5, itap=22 :FAIL Failed otap=5, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=5, itap=23 :FAIL Failed otap=5, itap=23 am654_sdhci_write_itapdly, write itapdly=24 For otap=5, itap=24 :FAIL Failed otap=5, itap=24 am654_sdhci_write_itapdly, write itapdly=25 For otap=5, itap=25 :FAIL Failed otap=5, itap=25 am654_sdhci_write_itapdly, write itapdly=26 For otap=5, itap=26 :FAIL Failed otap=5, itap=26 am654_sdhci_write_itapdly, write itapdly=27 For otap=5, itap=27 :FAIL Failed otap=5, itap=27 am654_sdhci_write_itapdly, write itapdly=28 For otap=5, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=5, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=5, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=5, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=6, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=6, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=6, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=6, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=6, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=6, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=6, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=6, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=6, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=6, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=6, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=6, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=6, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=6, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=6, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=6, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=6, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=6, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=6, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=6, itap=19 :PASS am654_sdhci_write_itapdly, write itapdly=20 For otap=6, itap=20 :PASS am654_sdhci_write_itapdly, write itapdly=21 For otap=6, itap=21 :PASS am654_sdhci_write_itapdly, write itapdly=22 For otap=6, itap=22 :PASS am654_sdhci_write_itapdly, write itapdly=23 For otap=6, itap=23 :FAIL Failed otap=6, itap=23 am654_sdhci_write_itapdly, write itapdly=24 For otap=6, itap=24 :FAIL Failed otap=6, itap=24 am654_sdhci_write_itapdly, write itapdly=25 For otap=6, itap=25 :FAIL Failed otap=6, itap=25 am654_sdhci_write_itapdly, write itapdly=26 For otap=6, itap=26 :FAIL Failed otap=6, itap=26 am654_sdhci_write_itapdly, write itapdly=27 For otap=6, itap=27 :FAIL Failed otap=6, itap=27 am654_sdhci_write_itapdly, write itapdly=28 For otap=6, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=6, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=6, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=6, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=7, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=7, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=7, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=7, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=7, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=7, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=7, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=7, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=7, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=7, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=7, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=7, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=7, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=7, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=7, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=7, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=7, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=7, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=7, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=7, itap=19 :PASS am654_sdhci_write_itapdly, write itapdly=20 For otap=7, itap=20 :PASS am654_sdhci_write_itapdly, write itapdly=21 For otap=7, itap=21 :PASS am654_sdhci_write_itapdly, write itapdly=22 For otap=7, itap=22 :PASS am654_sdhci_write_itapdly, write itapdly=23 For otap=7, itap=23 :FAIL Failed otap=7, itap=23 am654_sdhci_write_itapdly, write itapdly=24 For otap=7, itap=24 :FAIL Failed otap=7, itap=24 am654_sdhci_write_itapdly, write itapdly=25 For otap=7, itap=25 :FAIL Failed otap=7, itap=25 am654_sdhci_write_itapdly, write itapdly=26 For otap=7, itap=26 :FAIL Failed otap=7, itap=26 am654_sdhci_write_itapdly, write itapdly=27 For otap=7, itap=27 :FAIL Failed otap=7, itap=27 am654_sdhci_write_itapdly, write itapdly=28 For otap=7, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=7, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=7, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=7, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=8, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=8, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=8, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=8, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=8, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=8, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=8, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=8, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=8, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=8, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=8, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=8, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=8, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=8, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=8, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=8, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=8, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=8, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=8, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=8, itap=19 :PASS am654_sdhci_write_itapdly, write itapdly=20 For otap=8, itap=20 :PASS am654_sdhci_write_itapdly, write itapdly=21 For otap=8, itap=21 :PASS am654_sdhci_write_itapdly, write itapdly=22 For otap=8, itap=22 :PASS am654_sdhci_write_itapdly, write itapdly=23 For otap=8, itap=23 :FAIL Failed otap=8, itap=23 am654_sdhci_write_itapdly, write itapdly=24 For otap=8, itap=24 :FAIL Failed otap=8, itap=24 am654_sdhci_write_itapdly, write itapdly=25 For otap=8, itap=25 :FAIL Failed otap=8, itap=25 am654_sdhci_write_itapdly, write itapdly=26 For otap=8, itap=26 :FAIL Failed otap=8, itap=26 am654_sdhci_write_itapdly, write itapdly=27 For otap=8, itap=27 :FAIL Failed otap=8, itap=27 am654_sdhci_write_itapdly, write itapdly=28 For otap=8, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=8, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=8, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=8, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=9, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=9, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=9, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=9, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=9, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=9, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=9, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=9, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=9, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=9, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=9, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=9, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=9, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=9, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=9, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=9, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=9, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=9, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=9, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=9, itap=19 :PASS am654_sdhci_write_itapdly, write itapdly=20 For otap=9, itap=20 :PASS am654_sdhci_write_itapdly, write itapdly=21 For otap=9, itap=21 :PASS am654_sdhci_write_itapdly, write itapdly=22 For otap=9, itap=22 :PASS am654_sdhci_write_itapdly, write itapdly=23 For otap=9, itap=23 :FAIL Failed otap=9, itap=23 am654_sdhci_write_itapdly, write itapdly=24 For otap=9, itap=24 :FAIL Failed otap=9, itap=24 am654_sdhci_write_itapdly, write itapdly=25 For otap=9, itap=25 :FAIL Failed otap=9, itap=25 am654_sdhci_write_itapdly, write itapdly=26 For otap=9, itap=26 :FAIL Failed otap=9, itap=26 am654_sdhci_write_itapdly, write itapdly=27 For otap=9, itap=27 :FAIL Failed otap=9, itap=27 am654_sdhci_write_itapdly, write itapdly=28 For otap=9, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=9, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=9, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=9, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=10, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=10, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=10, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=10, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=10, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=10, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=10, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=10, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=10, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=10, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=10, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=10, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=10, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=10, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=10, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=10, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=10, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=10, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=10, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=10, itap=19 :PASS am654_sdhci_write_itapdly, write itapdly=20 For otap=10, itap=20 :PASS am654_sdhci_write_itapdly, write itapdly=21 For otap=10, itap=21 :PASS am654_sdhci_write_itapdly, write itapdly=22 For otap=10, itap=22 :FAIL Failed otap=10, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=10, itap=23 :FAIL Failed otap=10, itap=23 am654_sdhci_write_itapdly, write itapdly=24 For otap=10, itap=24 :FAIL Failed otap=10, itap=24 am654_sdhci_write_itapdly, write itapdly=25 For otap=10, itap=25 :FAIL Failed otap=10, itap=25 am654_sdhci_write_itapdly, write itapdly=26 For otap=10, itap=26 :FAIL Failed otap=10, itap=26 am654_sdhci_write_itapdly, write itapdly=27 For otap=10, itap=27 :FAIL Failed otap=10, itap=27 am654_sdhci_write_itapdly, write itapdly=28 For otap=10, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=10, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=10, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=10, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=11, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=11, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=11, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=11, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=11, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=11, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=11, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=11, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=11, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=11, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=11, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=11, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=11, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=11, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=11, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=11, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=11, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=11, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=11, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=11, itap=19 :PASS am654_sdhci_write_itapdly, write itapdly=20 For otap=11, itap=20 :PASS am654_sdhci_write_itapdly, write itapdly=21 For otap=11, itap=21 :PASS am654_sdhci_write_itapdly, write itapdly=22 For otap=11, itap=22 :PASS am654_sdhci_write_itapdly, write itapdly=23 For otap=11, itap=23 :FAIL Failed otap=11, itap=23 am654_sdhci_write_itapdly, write itapdly=24 For otap=11, itap=24 :FAIL Failed otap=11, itap=24 am654_sdhci_write_itapdly, write itapdly=25 For otap=11, itap=25 :FAIL Failed otap=11, itap=25 am654_sdhci_write_itapdly, write itapdly=26 For otap=11, itap=26 :FAIL Failed otap=11, itap=26 am654_sdhci_write_itapdly, write itapdly=27 For otap=11, itap=27 :FAIL Failed otap=11, itap=27 am654_sdhci_write_itapdly, write itapdly=28 For otap=11, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=11, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=11, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=11, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=12, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=12, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=12, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=12, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=12, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=12, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=12, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=12, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=12, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=12, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=12, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=12, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=12, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=12, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=12, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=12, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=12, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=12, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=12, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=12, itap=19 :PASS am654_sdhci_write_itapdly, write itapdly=20 For otap=12, itap=20 :PASS am654_sdhci_write_itapdly, write itapdly=21 For otap=12, itap=21 :PASS am654_sdhci_write_itapdly, write itapdly=22 For otap=12, itap=22 :PASS am654_sdhci_write_itapdly, write itapdly=23 For otap=12, itap=23 :FAIL Failed otap=12, itap=23 am654_sdhci_write_itapdly, write itapdly=24 For otap=12, itap=24 :FAIL Failed otap=12, itap=24 am654_sdhci_write_itapdly, write itapdly=25 For otap=12, itap=25 :FAIL Failed otap=12, itap=25 am654_sdhci_write_itapdly, write itapdly=26 For otap=12, itap=26 :FAIL Failed otap=12, itap=26 am654_sdhci_write_itapdly, write itapdly=27 For otap=12, itap=27 :FAIL Failed otap=12, itap=27 am654_sdhci_write_itapdly, write itapdly=28 For otap=12, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=12, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=12, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=12, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=13, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=13, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=13, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=13, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=13, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=13, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=13, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=13, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=13, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=13, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=13, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=13, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=13, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=13, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=13, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=13, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=13, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=13, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=13, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=13, itap=19 :PASS am654_sdhci_write_itapdly, write itapdly=20 For otap=13, itap=20 :PASS am654_sdhci_write_itapdly, write itapdly=21 For otap=13, itap=21 :PASS am654_sdhci_write_itapdly, write itapdly=22 For otap=13, itap=22 :PASS am654_sdhci_write_itapdly, write itapdly=23 For otap=13, itap=23 :FAIL Failed otap=13, itap=23 am654_sdhci_write_itapdly, write itapdly=24 For otap=13, itap=24 :FAIL Failed otap=13, itap=24 am654_sdhci_write_itapdly, write itapdly=25 For otap=13, itap=25 :FAIL Failed otap=13, itap=25 am654_sdhci_write_itapdly, write itapdly=26 For otap=13, itap=26 :FAIL Failed otap=13, itap=26 am654_sdhci_write_itapdly, write itapdly=27 For otap=13, itap=27 :FAIL Failed otap=13, itap=27 am654_sdhci_write_itapdly, write itapdly=28 For otap=13, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=13, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=13, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=13, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=14, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=14, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=14, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=14, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=14, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=14, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=14, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=14, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=14, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=14, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=14, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=14, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=14, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=14, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=14, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=14, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=14, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=14, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=14, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=14, itap=19 :PASS am654_sdhci_write_itapdly, write itapdly=20 For otap=14, itap=20 :PASS am654_sdhci_write_itapdly, write itapdly=21 For otap=14, itap=21 :PASS am654_sdhci_write_itapdly, write itapdly=22 For otap=14, itap=22 :PASS am654_sdhci_write_itapdly, write itapdly=23 For otap=14, itap=23 :FAIL Failed otap=14, itap=23 am654_sdhci_write_itapdly, write itapdly=24 For otap=14, itap=24 :FAIL Failed otap=14, itap=24 am654_sdhci_write_itapdly, write itapdly=25 For otap=14, itap=25 :FAIL Failed otap=14, itap=25 am654_sdhci_write_itapdly, write itapdly=26 For otap=14, itap=26 :FAIL Failed otap=14, itap=26 am654_sdhci_write_itapdly, write itapdly=27 For otap=14, itap=27 :FAIL Failed otap=14, itap=27 am654_sdhci_write_itapdly, write itapdly=28 For otap=14, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=14, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=14, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=14, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=15, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=15, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=15, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=15, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=15, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=15, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=15, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=15, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=15, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=15, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=15, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=15, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=15, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=15, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=15, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=15, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=15, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=15, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=15, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=15, itap=19 :PASS am654_sdhci_write_itapdly, write itapdly=20 For otap=15, itap=20 :PASS am654_sdhci_write_itapdly, write itapdly=21 For otap=15, itap=21 :PASS am654_sdhci_write_itapdly, write itapdly=22 For otap=15, itap=22 :FAIL Failed otap=15, itap=22 am654_sdhci_write_itapdly, write itapdly=23 For otap=15, itap=23 :FAIL Failed otap=15, itap=23 am654_sdhci_write_itapdly, write itapdly=24 For otap=15, itap=24 :FAIL Failed otap=15, itap=24 am654_sdhci_write_itapdly, write itapdly=25 For otap=15, itap=25 :FAIL Failed otap=15, itap=25 am654_sdhci_write_itapdly, write itapdly=26 For otap=15, itap=26 :FAIL Failed otap=15, itap=26 am654_sdhci_write_itapdly, write itapdly=27 For otap=15, itap=27 :FAIL Failed otap=15, itap=27 am654_sdhci_write_itapdly, write itapdly=28 For otap=15, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=15, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=15, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=15, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=16, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=16, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=16, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=16, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=16, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=16, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=16, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=16, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=16, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=16, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=16, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=16, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=16, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=16, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=16, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=16, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=16, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=16, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=16, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=16, itap=19 :PASS am654_sdhci_write_itapdly, write itapdly=20 For otap=16, itap=20 :PASS am654_sdhci_write_itapdly, write itapdly=21 For otap=16, itap=21 :PASS am654_sdhci_write_itapdly, write itapdly=22 For otap=16, itap=22 :PASS am654_sdhci_write_itapdly, write itapdly=23 For otap=16, itap=23 :FAIL Failed otap=16, itap=23 am654_sdhci_write_itapdly, write itapdly=24 For otap=16, itap=24 :FAIL Failed otap=16, itap=24 am654_sdhci_write_itapdly, write itapdly=25 For otap=16, itap=25 :FAIL Failed otap=16, itap=25 am654_sdhci_write_itapdly, write itapdly=26 For otap=16, itap=26 :FAIL Failed otap=16, itap=26 am654_sdhci_write_itapdly, write itapdly=27 For otap=16, itap=27 :FAIL Failed otap=16, itap=27 am654_sdhci_write_itapdly, write itapdly=28 For otap=16, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=16, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=16, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=16, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=17, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=17, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=17, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=17, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=17, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=17, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=17, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=17, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=17, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=17, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=17, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=17, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=17, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=17, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=17, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=17, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=17, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=17, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=17, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=17, itap=19 :PASS am654_sdhci_write_itapdly, write itapdly=20 For otap=17, itap=20 :PASS am654_sdhci_write_itapdly, write itapdly=21 For otap=17, itap=21 :PASS am654_sdhci_write_itapdly, write itapdly=22 For otap=17, itap=22 :PASS am654_sdhci_write_itapdly, write itapdly=23 For otap=17, itap=23 :FAIL Failed otap=17, itap=23 am654_sdhci_write_itapdly, write itapdly=24 For otap=17, itap=24 :FAIL Failed otap=17, itap=24 am654_sdhci_write_itapdly, write itapdly=25 For otap=17, itap=25 :FAIL Failed otap=17, itap=25 am654_sdhci_write_itapdly, write itapdly=26 For otap=17, itap=26 :FAIL Failed otap=17, itap=26 am654_sdhci_write_itapdly, write itapdly=27 For otap=17, itap=27 :FAIL Failed otap=17, itap=27 am654_sdhci_write_itapdly, write itapdly=28 For otap=17, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=17, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=17, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=17, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=18, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=18, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=18, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=18, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=18, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=18, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=18, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=18, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=18, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=18, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=18, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=18, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=18, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=18, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=18, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=18, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=18, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=18, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=18, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=18, itap=19 :PASS am654_sdhci_write_itapdly, write itapdly=20 For otap=18, itap=20 :PASS am654_sdhci_write_itapdly, write itapdly=21 For otap=18, itap=21 :PASS am654_sdhci_write_itapdly, write itapdly=22 For otap=18, itap=22 :PASS am654_sdhci_write_itapdly, write itapdly=23 For otap=18, itap=23 :FAIL Failed otap=18, itap=23 am654_sdhci_write_itapdly, write itapdly=24 For otap=18, itap=24 :FAIL Failed otap=18, itap=24 am654_sdhci_write_itapdly, write itapdly=25 For otap=18, itap=25 :FAIL Failed otap=18, itap=25 am654_sdhci_write_itapdly, write itapdly=26 For otap=18, itap=26 :FAIL Failed otap=18, itap=26 am654_sdhci_write_itapdly, write itapdly=27 For otap=18, itap=27 :FAIL Failed otap=18, itap=27 am654_sdhci_write_itapdly, write itapdly=28 For otap=18, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=18, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=18, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=18, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=19, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=19, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=19, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=19, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=19, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=19, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=19, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=19, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=19, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=19, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=19, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=19, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=19, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=19, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=19, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=19, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=19, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=19, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=19, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=19, itap=19 :PASS am654_sdhci_write_itapdly, write itapdly=20 For otap=19, itap=20 :PASS am654_sdhci_write_itapdly, write itapdly=21 For otap=19, itap=21 :PASS am654_sdhci_write_itapdly, write itapdly=22 For otap=19, itap=22 :PASS am654_sdhci_write_itapdly, write itapdly=23 For otap=19, itap=23 :FAIL Failed otap=19, itap=23 am654_sdhci_write_itapdly, write itapdly=24 For otap=19, itap=24 :FAIL Failed otap=19, itap=24 am654_sdhci_write_itapdly, write itapdly=25 For otap=19, itap=25 :FAIL Failed otap=19, itap=25 am654_sdhci_write_itapdly, write itapdly=26 For otap=19, itap=26 :FAIL Failed otap=19, itap=26 am654_sdhci_write_itapdly, write itapdly=27 For otap=19, itap=27 :FAIL Failed otap=19, itap=27 am654_sdhci_write_itapdly, write itapdly=28 For otap=19, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=19, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=19, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=19, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=20, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=20, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=20, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=20, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=20, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=20, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=20, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=20, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=20, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=20, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=20, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=20, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=20, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=20, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=20, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=20, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=20, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=20, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=20, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=20, itap=19 :PASS am654_sdhci_write_itapdly, write itapdly=20 For otap=20, itap=20 :PASS am654_sdhci_write_itapdly, write itapdly=21 For otap=20, itap=21 :PASS am654_sdhci_write_itapdly, write itapdly=22 For otap=20, itap=22 :PASS am654_sdhci_write_itapdly, write itapdly=23 For otap=20, itap=23 :FAIL Failed otap=20, itap=23 am654_sdhci_write_itapdly, write itapdly=24 For otap=20, itap=24 :FAIL Failed otap=20, itap=24 am654_sdhci_write_itapdly, write itapdly=25 For otap=20, itap=25 :FAIL Failed otap=20, itap=25 am654_sdhci_write_itapdly, write itapdly=26 For otap=20, itap=26 :FAIL Failed otap=20, itap=26 am654_sdhci_write_itapdly, write itapdly=27 For otap=20, itap=27 :FAIL Failed otap=20, itap=27 am654_sdhci_write_itapdly, write itapdly=28 For otap=20, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=20, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=20, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=20, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=21, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=21, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=21, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=21, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=21, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=21, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=21, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=21, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=21, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=21, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=21, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=21, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=21, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=21, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=21, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=21, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=21, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=21, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=21, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=21, itap=19 :PASS am654_sdhci_write_itapdly, write itapdly=20 For otap=21, itap=20 :PASS am654_sdhci_write_itapdly, write itapdly=21 For otap=21, itap=21 :PASS am654_sdhci_write_itapdly, write itapdly=22 For otap=21, itap=22 :PASS am654_sdhci_write_itapdly, write itapdly=23 For otap=21, itap=23 :FAIL Failed otap=21, itap=23 am654_sdhci_write_itapdly, write itapdly=24 For otap=21, itap=24 :FAIL Failed otap=21, itap=24 am654_sdhci_write_itapdly, write itapdly=25 For otap=21, itap=25 :FAIL Failed otap=21, itap=25 am654_sdhci_write_itapdly, write itapdly=26 For otap=21, itap=26 :FAIL Failed otap=21, itap=26 am654_sdhci_write_itapdly, write itapdly=27 For otap=21, itap=27 :FAIL Failed otap=21, itap=27 am654_sdhci_write_itapdly, write itapdly=28 For otap=21, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=21, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=21, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=21, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=22, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=22, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=22, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=22, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=22, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=22, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=22, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=22, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=22, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=22, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=22, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=22, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=22, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=22, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=22, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=22, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=22, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=22, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=22, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=22, itap=19 :PASS am654_sdhci_write_itapdly, write itapdly=20 For otap=22, itap=20 :PASS am654_sdhci_write_itapdly, write itapdly=21 For otap=22, itap=21 :PASS am654_sdhci_write_itapdly, write itapdly=22 For otap=22, itap=22 :PASS am654_sdhci_write_itapdly, write itapdly=23 For otap=22, itap=23 :FAIL Failed otap=22, itap=23 am654_sdhci_write_itapdly, write itapdly=24 For otap=22, itap=24 :FAIL Failed otap=22, itap=24 am654_sdhci_write_itapdly, write itapdly=25 For otap=22, itap=25 :FAIL Failed otap=22, itap=25 am654_sdhci_write_itapdly, write itapdly=26 For otap=22, itap=26 :FAIL Failed otap=22, itap=26 am654_sdhci_write_itapdly, write itapdly=27 For otap=22, itap=27 :FAIL Failed otap=22, itap=27 am654_sdhci_write_itapdly, write itapdly=28 For otap=22, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=22, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=22, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=22, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=23, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=23, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=23, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=23, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=23, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=23, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=23, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=23, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=23, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=23, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=23, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=23, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=23, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=23, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=23, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=23, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=23, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=23, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=23, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=23, itap=19 :PASS am654_sdhci_write_itapdly, write itapdly=20 For otap=23, itap=20 :PASS am654_sdhci_write_itapdly, write itapdly=21 For otap=23, itap=21 :PASS am654_sdhci_write_itapdly, write itapdly=22 For otap=23, itap=22 :PASS am654_sdhci_write_itapdly, write itapdly=23 For otap=23, itap=23 :FAIL Failed otap=23, itap=23 am654_sdhci_write_itapdly, write itapdly=24 For otap=23, itap=24 :FAIL Failed otap=23, itap=24 am654_sdhci_write_itapdly, write itapdly=25 For otap=23, itap=25 :FAIL Failed otap=23, itap=25 am654_sdhci_write_itapdly, write itapdly=26 For otap=23, itap=26 :FAIL Failed otap=23, itap=26 am654_sdhci_write_itapdly, write itapdly=27 For otap=23, itap=27 :FAIL Failed otap=23, itap=27 am654_sdhci_write_itapdly, write itapdly=28 For otap=23, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=23, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=23, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=23, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=24, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=24, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=24, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=24, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=24, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=24, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=24, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=24, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=24, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=24, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=24, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=24, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=24, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=24, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=24, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=24, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=24, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=24, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=24, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=24, itap=19 :PASS am654_sdhci_write_itapdly, write itapdly=20 For otap=24, itap=20 :PASS am654_sdhci_write_itapdly, write itapdly=21 For otap=24, itap=21 :PASS am654_sdhci_write_itapdly, write itapdly=22 For otap=24, itap=22 :PASS am654_sdhci_write_itapdly, write itapdly=23 For otap=24, itap=23 :FAIL Failed otap=24, itap=23 am654_sdhci_write_itapdly, write itapdly=24 For otap=24, itap=24 :FAIL Failed otap=24, itap=24 am654_sdhci_write_itapdly, write itapdly=25 For otap=24, itap=25 :FAIL Failed otap=24, itap=25 am654_sdhci_write_itapdly, write itapdly=26 For otap=24, itap=26 :FAIL Failed otap=24, itap=26 am654_sdhci_write_itapdly, write itapdly=27 For otap=24, itap=27 :FAIL Failed otap=24, itap=27 am654_sdhci_write_itapdly, write itapdly=28 For otap=24, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=24, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=24, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=24, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=25, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=25, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=25, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=25, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=25, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=25, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=25, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=25, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=25, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=25, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=25, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=25, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=25, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=25, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=25, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=25, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=25, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=25, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=25, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=25, itap=19 :PASS am654_sdhci_write_itapdly, write itapdly=20 For otap=25, itap=20 :PASS am654_sdhci_write_itapdly, write itapdly=21 For otap=25, itap=21 :PASS am654_sdhci_write_itapdly, write itapdly=22 For otap=25, itap=22 :PASS am654_sdhci_write_itapdly, write itapdly=23 For otap=25, itap=23 :FAIL Failed otap=25, itap=23 am654_sdhci_write_itapdly, write itapdly=24 For otap=25, itap=24 :FAIL Failed otap=25, itap=24 am654_sdhci_write_itapdly, write itapdly=25 For otap=25, itap=25 :FAIL Failed otap=25, itap=25 am654_sdhci_write_itapdly, write itapdly=26 For otap=25, itap=26 :FAIL Failed otap=25, itap=26 am654_sdhci_write_itapdly, write itapdly=27 For otap=25, itap=27 :FAIL Failed otap=25, itap=27 am654_sdhci_write_itapdly, write itapdly=28 For otap=25, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=25, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=25, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=25, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=26, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=26, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=26, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=26, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=26, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=26, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=26, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=26, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=26, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=26, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=26, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=26, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=26, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=26, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=26, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=26, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=26, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=26, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=26, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=26, itap=19 :PASS am654_sdhci_write_itapdly, write itapdly=20 For otap=26, itap=20 :PASS am654_sdhci_write_itapdly, write itapdly=21 For otap=26, itap=21 :PASS am654_sdhci_write_itapdly, write itapdly=22 For otap=26, itap=22 :PASS am654_sdhci_write_itapdly, write itapdly=23 For otap=26, itap=23 :FAIL Failed otap=26, itap=23 am654_sdhci_write_itapdly, write itapdly=24 For otap=26, itap=24 :FAIL Failed otap=26, itap=24 am654_sdhci_write_itapdly, write itapdly=25 For otap=26, itap=25 :FAIL Failed otap=26, itap=25 am654_sdhci_write_itapdly, write itapdly=26 For otap=26, itap=26 :FAIL Failed otap=26, itap=26 am654_sdhci_write_itapdly, write itapdly=27 For otap=26, itap=27 :FAIL Failed otap=26, itap=27 am654_sdhci_write_itapdly, write itapdly=28 For otap=26, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=26, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=26, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=26, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=27, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=27, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=27, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=27, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=27, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=27, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=27, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=27, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=27, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=27, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=27, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=27, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=27, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=27, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=27, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=27, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=27, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=27, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=27, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=27, itap=19 :PASS am654_sdhci_write_itapdly, write itapdly=20 For otap=27, itap=20 :PASS am654_sdhci_write_itapdly, write itapdly=21 For otap=27, itap=21 :PASS am654_sdhci_write_itapdly, write itapdly=22 For otap=27, itap=22 :PASS am654_sdhci_write_itapdly, write itapdly=23 For otap=27, itap=23 :FAIL Failed otap=27, itap=23 am654_sdhci_write_itapdly, write itapdly=24 For otap=27, itap=24 :FAIL Failed otap=27, itap=24 am654_sdhci_write_itapdly, write itapdly=25 For otap=27, itap=25 :FAIL Failed otap=27, itap=25 am654_sdhci_write_itapdly, write itapdly=26 For otap=27, itap=26 :FAIL Failed otap=27, itap=26 am654_sdhci_write_itapdly, write itapdly=27 For otap=27, itap=27 :FAIL Failed otap=27, itap=27 am654_sdhci_write_itapdly, write itapdly=28 For otap=27, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=27, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=27, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=27, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=28, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=28, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=28, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=28, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=28, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=28, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=28, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=28, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=28, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=28, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=28, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=28, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=28, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=28, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=28, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=28, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=28, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=28, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=28, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=28, itap=19 :PASS am654_sdhci_write_itapdly, write itapdly=20 For otap=28, itap=20 :PASS am654_sdhci_write_itapdly, write itapdly=21 For otap=28, itap=21 :PASS am654_sdhci_write_itapdly, write itapdly=22 For otap=28, itap=22 :PASS am654_sdhci_write_itapdly, write itapdly=23 For otap=28, itap=23 :FAIL Failed otap=28, itap=23 am654_sdhci_write_itapdly, write itapdly=24 For otap=28, itap=24 :FAIL Failed otap=28, itap=24 am654_sdhci_write_itapdly, write itapdly=25 For otap=28, itap=25 :FAIL Failed otap=28, itap=25 am654_sdhci_write_itapdly, write itapdly=26 For otap=28, itap=26 :FAIL Failed otap=28, itap=26 am654_sdhci_write_itapdly, write itapdly=27 For otap=28, itap=27 :FAIL Failed otap=28, itap=27 am654_sdhci_write_itapdly, write itapdly=28 For otap=28, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=28, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=28, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=28, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=29, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=29, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=29, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=29, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=29, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=29, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=29, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=29, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=29, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=29, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=29, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=29, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=29, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=29, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=29, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=29, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=29, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=29, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=29, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=29, itap=19 :PASS am654_sdhci_write_itapdly, write itapdly=20 For otap=29, itap=20 :PASS am654_sdhci_write_itapdly, write itapdly=21 For otap=29, itap=21 :PASS am654_sdhci_write_itapdly, write itapdly=22 For otap=29, itap=22 :PASS am654_sdhci_write_itapdly, write itapdly=23 For otap=29, itap=23 :FAIL Failed otap=29, itap=23 am654_sdhci_write_itapdly, write itapdly=24 For otap=29, itap=24 :FAIL Failed otap=29, itap=24 am654_sdhci_write_itapdly, write itapdly=25 For otap=29, itap=25 :FAIL Failed otap=29, itap=25 am654_sdhci_write_itapdly, write itapdly=26 For otap=29, itap=26 :FAIL Failed otap=29, itap=26 am654_sdhci_write_itapdly, write itapdly=27 For otap=29, itap=27 :FAIL Failed otap=29, itap=27 am654_sdhci_write_itapdly, write itapdly=28 For otap=29, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=29, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=29, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=29, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=30, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=30, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=30, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=30, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=30, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=30, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=30, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=30, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=30, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=30, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=30, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=30, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=30, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=30, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=30, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=30, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=30, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=30, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=30, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=30, itap=19 :PASS am654_sdhci_write_itapdly, write itapdly=20 For otap=30, itap=20 :PASS am654_sdhci_write_itapdly, write itapdly=21 For otap=30, itap=21 :PASS am654_sdhci_write_itapdly, write itapdly=22 For otap=30, itap=22 :PASS am654_sdhci_write_itapdly, write itapdly=23 For otap=30, itap=23 :FAIL Failed otap=30, itap=23 am654_sdhci_write_itapdly, write itapdly=24 For otap=30, itap=24 :FAIL Failed otap=30, itap=24 am654_sdhci_write_itapdly, write itapdly=25 For otap=30, itap=25 :FAIL Failed otap=30, itap=25 am654_sdhci_write_itapdly, write itapdly=26 For otap=30, itap=26 :FAIL Failed otap=30, itap=26 am654_sdhci_write_itapdly, write itapdly=27 For otap=30, itap=27 :FAIL Failed otap=30, itap=27 am654_sdhci_write_itapdly, write itapdly=28 For otap=30, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=30, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=30, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=30, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=0 For otap=31, itap=0 :PASS am654_sdhci_write_itapdly, write itapdly=1 For otap=31, itap=1 :PASS am654_sdhci_write_itapdly, write itapdly=2 For otap=31, itap=2 :PASS am654_sdhci_write_itapdly, write itapdly=3 For otap=31, itap=3 :PASS am654_sdhci_write_itapdly, write itapdly=4 For otap=31, itap=4 :PASS am654_sdhci_write_itapdly, write itapdly=5 For otap=31, itap=5 :PASS am654_sdhci_write_itapdly, write itapdly=6 For otap=31, itap=6 :PASS am654_sdhci_write_itapdly, write itapdly=7 For otap=31, itap=7 :PASS am654_sdhci_write_itapdly, write itapdly=8 For otap=31, itap=8 :PASS am654_sdhci_write_itapdly, write itapdly=9 For otap=31, itap=9 :PASS am654_sdhci_write_itapdly, write itapdly=10 For otap=31, itap=10 :PASS am654_sdhci_write_itapdly, write itapdly=11 For otap=31, itap=11 :PASS am654_sdhci_write_itapdly, write itapdly=12 For otap=31, itap=12 :PASS am654_sdhci_write_itapdly, write itapdly=13 For otap=31, itap=13 :PASS am654_sdhci_write_itapdly, write itapdly=14 For otap=31, itap=14 :PASS am654_sdhci_write_itapdly, write itapdly=15 For otap=31, itap=15 :PASS am654_sdhci_write_itapdly, write itapdly=16 For otap=31, itap=16 :PASS am654_sdhci_write_itapdly, write itapdly=17 For otap=31, itap=17 :PASS am654_sdhci_write_itapdly, write itapdly=18 For otap=31, itap=18 :PASS am654_sdhci_write_itapdly, write itapdly=19 For otap=31, itap=19 :PASS am654_sdhci_write_itapdly, write itapdly=20 For otap=31, itap=20 :PASS am654_sdhci_write_itapdly, write itapdly=21 For otap=31, itap=21 :PASS am654_sdhci_write_itapdly, write itapdly=22 For otap=31, itap=22 :PASS am654_sdhci_write_itapdly, write itapdly=23 For otap=31, itap=23 :FAIL Failed otap=31, itap=23 am654_sdhci_write_itapdly, write itapdly=24 For otap=31, itap=24 :FAIL Failed otap=31, itap=24 am654_sdhci_write_itapdly, write itapdly=25 For otap=31, itap=25 :FAIL Failed otap=31, itap=25 am654_sdhci_write_itapdly, write itapdly=26 For otap=31, itap=26 :FAIL Failed otap=31, itap=26 am654_sdhci_write_itapdly, write itapdly=27 For otap=31, itap=27 :FAIL Failed otap=31, itap=27 am654_sdhci_write_itapdly, write itapdly=28 For otap=31, itap=28 :PASS am654_sdhci_write_itapdly, write itapdly=29 For otap=31, itap=29 :PASS am654_sdhci_write_itapdly, write itapdly=30 For otap=31, itap=30 :PASS am654_sdhci_write_itapdly, write itapdly=31 For otap=31, itap=31 :PASS am654_sdhci_write_itapdly, write itapdly=15 switch to partitions #0, OK mmc1 is current device => md.w 0xfa0810c 0fa0810c: 610f 0010 0007 0000 0000 0000 0000 0000 .a.............. 0fa0811c: 0000 0000 0000 0000 0000 0000 0000 0000 ................ 0fa0812c: 0000 0000 0000 0000 0000 0000 0000 0000 ................ 0fa0813c: 0000 0000 0000 0000 0000 0000 0000 0000 ................ 0fa0814c: 0000 0000 0000 0000 0000 0000 0000 0000 ................ 0fa0815c: 0000 0000 0000 0000 0000 0000 0000 0000 ................ 0fa0816c: 0000 0000 0000 0000 0000 0000 0000 0000 ................ 0fa0817c: 0000 0000 0000 0000 0000 0000 0000 0000 ................ =>
Hi Markus, Alexander, On 2/3/26 4:35 AM, Markus Schneider-Pargmann wrote: > Hi Judith, > > On Wed Jan 14, 2026 at 11:04 PM CET, Judith Mendez wrote: >> Hi Markus, >> >> On 1/14/26 3:16 AM, Markus Schneider-Pargmann wrote: >>> Hi Judith, >>> >>> On Tue Jan 13, 2026 at 1:29 AM CET, Judith Mendez wrote: >>>> On 1/6/26 10:22 AM, Markus Schneider-Pargmann (TI.com) wrote: >>>>> Remove Schmitt Trigger from mmc pins. With Schmitt Trigger enabled >>>>> u-boot SPL is not able to read u-boot from mmc: >>>>> >>>>> Trying to boot from MMC2 >>>>> Error reading cluster >>>>> spl_load_image_fat: error reading image u-boot.img, err - -22 >>>>> Error: -22 >>>>> SPL: Unsupported Boot Device! >>>>> SPL: failed to boot from all boot devices >>>>> ### ERROR ### Please RESET the board ### >>>>> >>>>> I bisected this issue between u-boot v2025.10 and v2026.01 and found the >>>>> devicetree merge to be the problem. At a closer look I found the >>>>> k3-pinctrl.h changes. Disabling the Schmitt Trigger fixes the u-boot SPL >>>>> failure to read from mmc. >>>> >>>> I have tested 4 AM62A SK boards and I cannot replicate the issue >>>> you are seeing. I do not see an issue with Schmitt Trigger in U-boot >>>> nor Linux /: >>> >>> Thanks for testing. >>> >>>> Can you please run a quick tap sweep on MMC1 and MMC0 interfaces like >>>> so? https://gist.github.com/jmenti/f4a73a8323e44bf717c6d2c528c499ca >>>> >>>> This will give me an idea if whether we should be talking about >>>> revisiting characterization with ST_ENA=1. >>> >>> The patch was a bit broken, but I think I managed to apply it to >>> v2026.01 as it was supposed to be. (master currently doesn't boot even >>> SPL, I don't have time right now to debug that). >> >> as Nishanth, mentioned, master is missing two patches [0][1] >> >>> >>> I attached the boot log. It does boot with your patch. Also can this be >>> an issue with different SD cards? >> >> Something does not quite add up, >> >> Can you try the following 2 commands? >> >> # mmc dev 1 >> # md.w 0xfa0810c > > Finally here is the output from boot and executing these commands. I am > now on v2026.04-rc1 with your sweep patch. Thanks for sending over the tap sweep. I compiled a comparison table here to show a bit of data for the u-boot tuning step: https://gist.github.com/jmenti/5d42f1e43fb357083eaa813cfee484a8 Based on the data I can conclude the following: 1. you seem to have more errors than I do 2. there seems to be an issue with the chosen final tap setting 3. the chosen final tap setting should still have worked for you but did not. For #2, something in the tuning results seems off so let me investigate this on my end and Ill get back. For #3, will have to discuss this internally & test a couple more things, then come back with more information. Meanwhile, I am interested to see what are the tap sweep results for the failing Verdin board, if those can be sent as well, that would be great info. ~ Judith
Hello Judith, On Wed, Feb 04, 2026 at 08:03:39PM -0600, Judith Mendez wrote: > On 2/3/26 4:35 AM, Markus Schneider-Pargmann wrote: > > On Wed Jan 14, 2026 at 11:04 PM CET, Judith Mendez wrote: > > > On 1/14/26 3:16 AM, Markus Schneider-Pargmann wrote: > > > > On Tue Jan 13, 2026 at 1:29 AM CET, Judith Mendez wrote: > > > > > On 1/6/26 10:22 AM, Markus Schneider-Pargmann (TI.com) wrote: > > > > > > Remove Schmitt Trigger from mmc pins. With Schmitt Trigger enabled > > > > > > u-boot SPL is not able to read u-boot from mmc: > > > > > > > > > > > > Trying to boot from MMC2 > > > > > > Error reading cluster > > > > > > spl_load_image_fat: error reading image u-boot.img, err - -22 > > > > > > Error: -22 > > > > > > SPL: Unsupported Boot Device! > > > > > > SPL: failed to boot from all boot devices > > > > > > ### ERROR ### Please RESET the board ### > > > > > > > > > > > > I bisected this issue between u-boot v2025.10 and v2026.01 and found the > > > > > > devicetree merge to be the problem. At a closer look I found the > > > > > > k3-pinctrl.h changes. Disabling the Schmitt Trigger fixes the u-boot SPL > > > > > > failure to read from mmc. > > > > > > > > > > I have tested 4 AM62A SK boards and I cannot replicate the issue > > > > > you are seeing. I do not see an issue with Schmitt Trigger in U-boot > > > > > nor Linux /: > > > > > > > > Thanks for testing. > > > > > > > > > Can you please run a quick tap sweep on MMC1 and MMC0 interfaces like > > > > > so? https://gist.github.com/jmenti/f4a73a8323e44bf717c6d2c528c499ca > > > > > > > > > > This will give me an idea if whether we should be talking about > > > > > revisiting characterization with ST_ENA=1. > > > > > > > > The patch was a bit broken, but I think I managed to apply it to > > > > v2026.01 as it was supposed to be. (master currently doesn't boot even > > > > SPL, I don't have time right now to debug that). > > > > > > as Nishanth, mentioned, master is missing two patches [0][1] > > > > > > > > > > > I attached the boot log. It does boot with your patch. Also can this be > > > > an issue with different SD cards? > > > > > > Something does not quite add up, > > > > > > Can you try the following 2 commands? > > > > > > # mmc dev 1 > > > # md.w 0xfa0810c > > > > Finally here is the output from boot and executing these commands. I am > > now on v2026.04-rc1 with your sweep patch. > > Thanks for sending over the tap sweep. I compiled a comparison table > here to show a bit of data for the u-boot tuning step: > https://gist.github.com/jmenti/5d42f1e43fb357083eaa813cfee484a8 > > Based on the data I can conclude the following: > 1. you seem to have more errors than I do > 2. there seems to be an issue with the chosen final tap setting > 3. the chosen final tap setting should still have worked for you > but did not. > > For #2, something in the tuning results seems off so let me investigate > this on my end and Ill get back. > For #3, will have to discuss this internally & test a couple more things, > then come back with more information. > > Meanwhile, I am interested to see what are the tap sweep results for the > failing Verdin board, if those can be sent as well, that would be great > info. Verdin is now booting fine. The boot failure was related to other U-Boot bugs (as Nishanth mentioned) that are now fixed. Thanks Francesco
Hi Fransesco, On 2/5/26 1:24 AM, Francesco Dolcini wrote: > Hello Judith, > > On Wed, Feb 04, 2026 at 08:03:39PM -0600, Judith Mendez wrote: >> On 2/3/26 4:35 AM, Markus Schneider-Pargmann wrote: >>> On Wed Jan 14, 2026 at 11:04 PM CET, Judith Mendez wrote: >>>> On 1/14/26 3:16 AM, Markus Schneider-Pargmann wrote: >>>>> On Tue Jan 13, 2026 at 1:29 AM CET, Judith Mendez wrote: >>>>>> On 1/6/26 10:22 AM, Markus Schneider-Pargmann (TI.com) wrote: >>>>>>> Remove Schmitt Trigger from mmc pins. With Schmitt Trigger enabled >>>>>>> u-boot SPL is not able to read u-boot from mmc: >>>>>>> >>>>>>> Trying to boot from MMC2 >>>>>>> Error reading cluster >>>>>>> spl_load_image_fat: error reading image u-boot.img, err - -22 >>>>>>> Error: -22 >>>>>>> SPL: Unsupported Boot Device! >>>>>>> SPL: failed to boot from all boot devices >>>>>>> ### ERROR ### Please RESET the board ### >>>>>>> >>>>>>> I bisected this issue between u-boot v2025.10 and v2026.01 and found the >>>>>>> devicetree merge to be the problem. At a closer look I found the >>>>>>> k3-pinctrl.h changes. Disabling the Schmitt Trigger fixes the u-boot SPL >>>>>>> failure to read from mmc. >>>>>> >>>>>> I have tested 4 AM62A SK boards and I cannot replicate the issue >>>>>> you are seeing. I do not see an issue with Schmitt Trigger in U-boot >>>>>> nor Linux /: >>>>> >>>>> Thanks for testing. >>>>> >>>>>> Can you please run a quick tap sweep on MMC1 and MMC0 interfaces like >>>>>> so? https://gist.github.com/jmenti/f4a73a8323e44bf717c6d2c528c499ca >>>>>> >>>>>> This will give me an idea if whether we should be talking about >>>>>> revisiting characterization with ST_ENA=1. >>>>> >>>>> The patch was a bit broken, but I think I managed to apply it to >>>>> v2026.01 as it was supposed to be. (master currently doesn't boot even >>>>> SPL, I don't have time right now to debug that). >>>> >>>> as Nishanth, mentioned, master is missing two patches [0][1] >>>> >>>>> >>>>> I attached the boot log. It does boot with your patch. Also can this be >>>>> an issue with different SD cards? >>>> >>>> Something does not quite add up, >>>> >>>> Can you try the following 2 commands? >>>> >>>> # mmc dev 1 >>>> # md.w 0xfa0810c >>> >>> Finally here is the output from boot and executing these commands. I am >>> now on v2026.04-rc1 with your sweep patch. >> >> Thanks for sending over the tap sweep. I compiled a comparison table >> here to show a bit of data for the u-boot tuning step: >> https://gist.github.com/jmenti/5d42f1e43fb357083eaa813cfee484a8 >> >> Based on the data I can conclude the following: >> 1. you seem to have more errors than I do >> 2. there seems to be an issue with the chosen final tap setting >> 3. the chosen final tap setting should still have worked for you >> but did not. >> >> For #2, something in the tuning results seems off so let me investigate >> this on my end and Ill get back. >> For #3, will have to discuss this internally & test a couple more things, >> then come back with more information. >> >> Meanwhile, I am interested to see what are the tap sweep results for the >> failing Verdin board, if those can be sent as well, that would be great >> info. > > Verdin is now booting fine. The boot failure was related to other U-Boot > bugs (as Nishanth mentioned) that are now fixed. Good to know, that isolates the issue to only one board. Thanks. ~ Judith
Hi Judith, On Thu, 2026-02-05 at 11:07 -0600, Judith Mendez wrote: > > Verdin is now booting fine. The boot failure was related to other U-Boot > > bugs (as Nishanth mentioned) that are now fixed. > > Good to know, that isolates the issue to only one board. not really, as I mentioned, I had observed some issues with one of our internal development boards, but I can only provide the data after couple of weeks, after my vacation. -- Alexander Sverdlin.
On Tue, 2026-01-06 at 17:22 +0100, Markus Schneider-Pargmann (TI.com) wrote:
> Remove Schmitt Trigger from mmc pins. With Schmitt Trigger enabled
> u-boot SPL is not able to read u-boot from mmc:
>
> Trying to boot from MMC2
> Error reading cluster
> spl_load_image_fat: error reading image u-boot.img, err - -22
> Error: -22
> SPL: Unsupported Boot Device!
> SPL: failed to boot from all boot devices
> ### ERROR ### Please RESET the board ###
>
> I bisected this issue between u-boot v2025.10 and v2026.01 and found the
> devicetree merge to be the problem. At a closer look I found the
> k3-pinctrl.h changes. Disabling the Schmitt Trigger fixes the u-boot SPL
> failure to read from mmc.
>
> Fixes: 5b272127884b ("arm64: dts: ti: k3-pinctrl: Enable Schmitt Trigger by
> default")
> Signed-off-by: Markus Schneider-Pargmann (TI.com) <msp@baylibre.com>
>
Hi Markus,
We're seeing a similar issue on Verdin AM62 with U-Boot 2026.01. The
board has complete SPL boot failure with no output at all.
This occurs in the same version you bisected (v2026.01 failing).
Could the Schmitt Trigger changes also affect Verdin AM62?
Best regards,
Vitor Soares
On 14:07-20260108, Vitor Soares wrote:
> On Tue, 2026-01-06 at 17:22 +0100, Markus Schneider-Pargmann (TI.com) wrote:
> > Remove Schmitt Trigger from mmc pins. With Schmitt Trigger enabled
> > u-boot SPL is not able to read u-boot from mmc:
> >
> > Trying to boot from MMC2
> > Error reading cluster
> > spl_load_image_fat: error reading image u-boot.img, err - -22
> > Error: -22
> > SPL: Unsupported Boot Device!
> > SPL: failed to boot from all boot devices
> > ### ERROR ### Please RESET the board ###
> >
> > I bisected this issue between u-boot v2025.10 and v2026.01 and found the
> > devicetree merge to be the problem. At a closer look I found the
> > k3-pinctrl.h changes. Disabling the Schmitt Trigger fixes the u-boot SPL
> > failure to read from mmc.
> >
> > Fixes: 5b272127884b ("arm64: dts: ti: k3-pinctrl: Enable Schmitt Trigger by
> > default")
> > Signed-off-by: Markus Schneider-Pargmann (TI.com) <msp@baylibre.com>
> >
> Hi Markus,
>
> We're seeing a similar issue on Verdin AM62 with U-Boot 2026.01. The
> board has complete SPL boot failure with no output at all.
>
> This occurs in the same version you bisected (v2026.01 failing).
> Could the Schmitt Trigger changes also affect Verdin AM62?
Side note:
There seem to be multiple issues playing around in U-boot regression.
Please see
https://lore.kernel.org/all/20260108141233.GQ3416603@bill-the-cat/ as
well. There is chunk of discussions on #u-boot irc channel. I'd wait for
U-boot folks to settle things down
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
https://ti.com/opensource
Hi Vitor,
On Thu, 2026-01-08 at 14:07 +0000, Vitor Soares wrote:
> On Tue, 2026-01-06 at 17:22 +0100, Markus Schneider-Pargmann (TI.com) wrote:
> > Remove Schmitt Trigger from mmc pins. With Schmitt Trigger enabled
> > u-boot SPL is not able to read u-boot from mmc:
> >
> > Trying to boot from MMC2
> > Error reading cluster
> > spl_load_image_fat: error reading image u-boot.img, err - -22
> > Error: -22
> > SPL: Unsupported Boot Device!
> > SPL: failed to boot from all boot devices
> > ### ERROR ### Please RESET the board ###
> >
> > I bisected this issue between u-boot v2025.10 and v2026.01 and found the
> > devicetree merge to be the problem. At a closer look I found the
> > k3-pinctrl.h changes. Disabling the Schmitt Trigger fixes the u-boot SPL
> > failure to read from mmc.
> >
> > Fixes: 5b272127884b ("arm64: dts: ti: k3-pinctrl: Enable Schmitt Trigger by
> > default")
> > Signed-off-by: Markus Schneider-Pargmann (TI.com) <msp@baylibre.com>
> >
> Hi Markus,
>
> We're seeing a similar issue on Verdin AM62 with U-Boot 2026.01. The
> board has complete SPL boot failure with no output at all.
>
> This occurs in the same version you bisected (v2026.01 failing).
> Could the Schmitt Trigger changes also affect Verdin AM62?
they do affect AM62, even though not not every HW, I have one HW variant
working properly and one where I observe the problem. Maybe a revert
of 5b272127884b for now would make more sense than just fixing AM62A7.
I unfortunately do not have any reply on this from TI yet.
--
Alexander Sverdlin.
Hi Markus,
I'm sorry my patch has caused regression for your use-case!
I think we would need to discuss this with TI via our FAE, because the change
in question has both been discussed with former FAE and the technical team
behind, and adopted in TI SDK.
Or have you already discused this with corresponding TI HW team?
Which hardware is affected, is it the official SK-AM62A-LP?
Is MMC2 the SD-card?
On Tue, 2026-01-06 at 17:22 +0100, Markus Schneider-Pargmann (TI.com) wrote:
> Remove Schmitt Trigger from mmc pins. With Schmitt Trigger enabled
> u-boot SPL is not able to read u-boot from mmc:
>
> Trying to boot from MMC2
> Error reading cluster
> spl_load_image_fat: error reading image u-boot.img, err - -22
> Error: -22
> SPL: Unsupported Boot Device!
> SPL: failed to boot from all boot devices
> ### ERROR ### Please RESET the board ###
>
> I bisected this issue between u-boot v2025.10 and v2026.01 and found the
> devicetree merge to be the problem. At a closer look I found the
> k3-pinctrl.h changes. Disabling the Schmitt Trigger fixes the u-boot SPL
> failure to read from mmc.
>
> Fixes: 5b272127884b ("arm64: dts: ti: k3-pinctrl: Enable Schmitt Trigger by default")
> Signed-off-by: Markus Schneider-Pargmann (TI.com) <msp@baylibre.com>
> ---
> arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 36 ++++++++++++++++-----------------
> 1 file changed, 18 insertions(+), 18 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
> index e99bdbc2e0cbdf858f1631096f9c2a086191bab3..9129045c8bbd3a83dba6ff6f2148a3624b91b546 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
> @@ -315,30 +315,30 @@ AM62AX_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
>
> main_mmc0_pins_default: main-mmc0-default-pins {
> pinctrl-single,pins = <
> - AM62AX_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
> - AM62AX_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLKLB */
> - AM62AX_IOPAD(0x21c, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
according to datasheet, MMC0_CLK should have address 0x218 and it's the ball AB7.
MMC0_CLKLB is not present in the datasheet and AB1 is actually VSS. 0x21C address
is not documented.
Something is not right here...
OK, grepping TRM for CLKLB, one can conclude that 0x21c is actually MMC0_CLKLB.
Could you please try to modify 0x21c address only? Does it solve the boot problem?
> - AM62AX_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */
> - AM62AX_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */
> - AM62AX_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */
> - AM62AX_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */
> - AM62AX_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */
> - AM62AX_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */
> - AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */
> - AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */
All the rest actually have ST enabled on PoR according to TRM and I suppose BootROM
would have had hard times booting from the affected MMC device if it would not be
the correct setting?
> + AM62AX_IOPAD(0x220, PIN_INPUT_NOST, 0) /* (Y3) MMC0_CMD */
> + AM62AX_IOPAD(0x218, PIN_INPUT_NOST, 0) /* (AB1) MMC0_CLKLB */
> + AM62AX_IOPAD(0x21c, PIN_INPUT_NOST, 0) /* (AB1) MMC0_CLK */
> + AM62AX_IOPAD(0x214, PIN_INPUT_NOST, 0) /* (AA2) MMC0_DAT0 */
> + AM62AX_IOPAD(0x210, PIN_INPUT_PULLUP_NOST, 0) /* (AA1) MMC0_DAT1 */
> + AM62AX_IOPAD(0x20c, PIN_INPUT_PULLUP_NOST, 0) /* (AA3) MMC0_DAT2 */
> + AM62AX_IOPAD(0x208, PIN_INPUT_PULLUP_NOST, 0) /* (Y4) MMC0_DAT3 */
> + AM62AX_IOPAD(0x204, PIN_INPUT_PULLUP_NOST, 0) /* (AB2) MMC0_DAT4 */
> + AM62AX_IOPAD(0x200, PIN_INPUT_PULLUP_NOST, 0) /* (AC1) MMC0_DAT5 */
> + AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP_NOST, 0) /* (AD2) MMC0_DAT6 */
> + AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP_NOST, 0) /* (AC2) MMC0_DAT7 */
> >;
> bootph-all;
> };
>
> main_mmc1_pins_default: main-mmc1-default-pins {
> pinctrl-single,pins = <
> - AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
> - AM62AX_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
> - AM62AX_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */
> - AM62AX_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */
> - AM62AX_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */
> - AM62AX_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */
> - AM62AX_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */
All of these have ST enabled on PoR, according to TRM.
> + AM62AX_IOPAD(0x23c, PIN_INPUT_NOST, 0) /* (A21) MMC1_CMD */
> + AM62AX_IOPAD(0x234, PIN_INPUT_NOST, 0) /* (B22) MMC1_CLK */
> + AM62AX_IOPAD(0x230, PIN_INPUT_NOST, 0) /* (A22) MMC1_DAT0 */
> + AM62AX_IOPAD(0x22c, PIN_INPUT_NOST, 0) /* (B21) MMC1_DAT1 */
> + AM62AX_IOPAD(0x228, PIN_INPUT_NOST, 0) /* (C21) MMC1_DAT2 */
> + AM62AX_IOPAD(0x224, PIN_INPUT_NOST, 0) /* (D22) MMC1_DAT3 */
> + AM62AX_IOPAD(0x240, PIN_INPUT_NOST, 0) /* (D17) MMC1_SDCD */
> >;
> bootph-all;
> };
>
> ---
> base-commit: 6cd6c12031130a349a098dbeb19d8c3070d2dfbe
> change-id: 20260106-topic-am62a-mmc-pinctrl-v6-19-next-2f3e5563fbb5
>
> Best regards,
--
Alexander Sverdlin.
Hi Markus,
On Tue, 2026-01-06 at 18:25 +0100, Alexander Sverdlin wrote:
> > main_mmc1_pins_default: main-mmc1-default-pins {
> > pinctrl-single,pins = <
> > - AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
this is a bit trial-and-error, but maybe you could try to add missing clock
retimer/loopback pin for test instead of disabling ST? Would this help:
AM62AX_IOPAD(0x238, PIN_INPUT, 0) /* (N/A) MMC1_CLKLB */
some SoCs from AM6x family seem to require it even though TRMs claim the default
PoR state is the proper one.
> > - AM62AX_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
> > - AM62AX_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */
> > - AM62AX_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */
> > - AM62AX_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */
> > - AM62AX_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */
> > - AM62AX_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */
>
> All of these have ST enabled on PoR, according to TRM.
>
> > + AM62AX_IOPAD(0x23c, PIN_INPUT_NOST, 0) /* (A21) MMC1_CMD */
> > + AM62AX_IOPAD(0x234, PIN_INPUT_NOST, 0) /* (B22) MMC1_CLK */
> > + AM62AX_IOPAD(0x230, PIN_INPUT_NOST, 0) /* (A22) MMC1_DAT0 */
> > + AM62AX_IOPAD(0x22c, PIN_INPUT_NOST, 0) /* (B21) MMC1_DAT1 */
> > + AM62AX_IOPAD(0x228, PIN_INPUT_NOST, 0) /* (C21) MMC1_DAT2 */
> > + AM62AX_IOPAD(0x224, PIN_INPUT_NOST, 0) /* (D22) MMC1_DAT3 */
> > + AM62AX_IOPAD(0x240, PIN_INPUT_NOST, 0) /* (D17) MMC1_SDCD */
> > >;
> > bootph-all;
> > };
--
Alexander Sverdlin.
Hi Alexander,
On Wed Jan 7, 2026 at 3:49 PM CET, Alexander Sverdlin wrote:
> Hi Markus,
>
> On Tue, 2026-01-06 at 18:25 +0100, Alexander Sverdlin wrote:
>> > main_mmc1_pins_default: main-mmc1-default-pins {
>> > pinctrl-single,pins = <
>> > - AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
>
> this is a bit trial-and-error, but maybe you could try to add missing clock
> retimer/loopback pin for test instead of disabling ST? Would this help:
>
> AM62AX_IOPAD(0x238, PIN_INPUT, 0) /* (N/A) MMC1_CLKLB */
>
> some SoCs from AM6x family seem to require it even though TRMs claim the default
> PoR state is the proper one.
Thanks, but adding that does not help unfortunately. And it seems ST
being enabled on that pin does not break it either. The data lines seem
to be the important ones.
Best
Markus
>
>> > - AM62AX_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
>> > - AM62AX_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */
>> > - AM62AX_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */
>> > - AM62AX_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */
>> > - AM62AX_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */
>> > - AM62AX_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */
>>
>> All of these have ST enabled on PoR, according to TRM.
>>
>> > + AM62AX_IOPAD(0x23c, PIN_INPUT_NOST, 0) /* (A21) MMC1_CMD */
>> > + AM62AX_IOPAD(0x234, PIN_INPUT_NOST, 0) /* (B22) MMC1_CLK */
>> > + AM62AX_IOPAD(0x230, PIN_INPUT_NOST, 0) /* (A22) MMC1_DAT0 */
>> > + AM62AX_IOPAD(0x22c, PIN_INPUT_NOST, 0) /* (B21) MMC1_DAT1 */
>> > + AM62AX_IOPAD(0x228, PIN_INPUT_NOST, 0) /* (C21) MMC1_DAT2 */
>> > + AM62AX_IOPAD(0x224, PIN_INPUT_NOST, 0) /* (D22) MMC1_DAT3 */
>> > + AM62AX_IOPAD(0x240, PIN_INPUT_NOST, 0) /* (D17) MMC1_SDCD */
>> > >;
>> > bootph-all;
>> > };
Hi Alexander,
On Tue Jan 6, 2026 at 6:25 PM CET, Alexander Sverdlin wrote:
> Hi Markus,
>
> I'm sorry my patch has caused regression for your use-case!
>
> I think we would need to discuss this with TI via our FAE, because the change
> in question has both been discussed with former FAE and the technical team
> behind, and adopted in TI SDK.
>
> Or have you already discused this with corresponding TI HW team?
>
> Which hardware is affected, is it the official SK-AM62A-LP?
> Is MMC2 the SD-card?
I only tested my am62a board on u-boot v2026.01. It is a SK-AM62A-LP.
MMC2 is the SD-card and mmc1 in the devicetree.
I am using u-boot's am62ax_evm_r5_defconfig and am62ax_evm_a53_defconfig
as defconfigs.
>
> On Tue, 2026-01-06 at 17:22 +0100, Markus Schneider-Pargmann (TI.com) wrote:
>> Remove Schmitt Trigger from mmc pins. With Schmitt Trigger enabled
>> u-boot SPL is not able to read u-boot from mmc:
>>
>> Trying to boot from MMC2
>> Error reading cluster
>> spl_load_image_fat: error reading image u-boot.img, err - -22
>> Error: -22
>> SPL: Unsupported Boot Device!
>> SPL: failed to boot from all boot devices
>> ### ERROR ### Please RESET the board ###
>>
>> I bisected this issue between u-boot v2025.10 and v2026.01 and found the
>> devicetree merge to be the problem. At a closer look I found the
>> k3-pinctrl.h changes. Disabling the Schmitt Trigger fixes the u-boot SPL
>> failure to read from mmc.
>>
>> Fixes: 5b272127884b ("arm64: dts: ti: k3-pinctrl: Enable Schmitt Trigger by default")
>> Signed-off-by: Markus Schneider-Pargmann (TI.com) <msp@baylibre.com>
>> ---
>> arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 36 ++++++++++++++++-----------------
>> 1 file changed, 18 insertions(+), 18 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
>> index e99bdbc2e0cbdf858f1631096f9c2a086191bab3..9129045c8bbd3a83dba6ff6f2148a3624b91b546 100644
>> --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
>> +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
>> @@ -315,30 +315,30 @@ AM62AX_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
>>
>> main_mmc0_pins_default: main-mmc0-default-pins {
>> pinctrl-single,pins = <
>> - AM62AX_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
>> - AM62AX_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLKLB */
>> - AM62AX_IOPAD(0x21c, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
>
> according to datasheet, MMC0_CLK should have address 0x218 and it's the ball AB7.
> MMC0_CLKLB is not present in the datasheet and AB1 is actually VSS. 0x21C address
> is not documented.
>
> Something is not right here...
>
> OK, grepping TRM for CLKLB, one can conclude that 0x21c is actually MMC0_CLKLB.
>
> Could you please try to modify 0x21c address only? Does it solve the boot problem?
>
>> - AM62AX_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */
>> - AM62AX_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */
>> - AM62AX_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */
>> - AM62AX_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */
>> - AM62AX_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */
>> - AM62AX_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */
>> - AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */
>> - AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */
>
> All the rest actually have ST enabled on PoR according to TRM and I suppose BootROM
> would have had hard times booting from the affected MMC device if it would not be
> the correct setting?
>
>> + AM62AX_IOPAD(0x220, PIN_INPUT_NOST, 0) /* (Y3) MMC0_CMD */
>> + AM62AX_IOPAD(0x218, PIN_INPUT_NOST, 0) /* (AB1) MMC0_CLKLB */
>> + AM62AX_IOPAD(0x21c, PIN_INPUT_NOST, 0) /* (AB1) MMC0_CLK */
>> + AM62AX_IOPAD(0x214, PIN_INPUT_NOST, 0) /* (AA2) MMC0_DAT0 */
>> + AM62AX_IOPAD(0x210, PIN_INPUT_PULLUP_NOST, 0) /* (AA1) MMC0_DAT1 */
>> + AM62AX_IOPAD(0x20c, PIN_INPUT_PULLUP_NOST, 0) /* (AA3) MMC0_DAT2 */
>> + AM62AX_IOPAD(0x208, PIN_INPUT_PULLUP_NOST, 0) /* (Y4) MMC0_DAT3 */
>> + AM62AX_IOPAD(0x204, PIN_INPUT_PULLUP_NOST, 0) /* (AB2) MMC0_DAT4 */
>> + AM62AX_IOPAD(0x200, PIN_INPUT_PULLUP_NOST, 0) /* (AC1) MMC0_DAT5 */
>> + AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP_NOST, 0) /* (AD2) MMC0_DAT6 */
>> + AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP_NOST, 0) /* (AC2) MMC0_DAT7 */
>> >;
>> bootph-all;
>> };
>>
>> main_mmc1_pins_default: main-mmc1-default-pins {
>> pinctrl-single,pins = <
>> - AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
>> - AM62AX_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
>> - AM62AX_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */
>> - AM62AX_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */
>> - AM62AX_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */
>> - AM62AX_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */
>> - AM62AX_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */
>
> All of these have ST enabled on PoR, according to TRM.
>
>> + AM62AX_IOPAD(0x23c, PIN_INPUT_NOST, 0) /* (A21) MMC1_CMD */
>> + AM62AX_IOPAD(0x234, PIN_INPUT_NOST, 0) /* (B22) MMC1_CLK */
>> + AM62AX_IOPAD(0x230, PIN_INPUT_NOST, 0) /* (A22) MMC1_DAT0 */
>> + AM62AX_IOPAD(0x22c, PIN_INPUT_NOST, 0) /* (B21) MMC1_DAT1 */
>> + AM62AX_IOPAD(0x228, PIN_INPUT_NOST, 0) /* (C21) MMC1_DAT2 */
>> + AM62AX_IOPAD(0x224, PIN_INPUT_NOST, 0) /* (D22) MMC1_DAT3 */
>> + AM62AX_IOPAD(0x240, PIN_INPUT_NOST, 0) /* (D17) MMC1_SDCD */
My board is setup to boot from SD card for easier u-boot testing. So
only the mmc1 is relevant for my setup. I just tested which pins need
NOST here for the boot to work, all DAT pins need the NOST variants,
otherwise it does not boot here. Not sure if this is just my board or it
fails on other boards as well.
Best
Markus
Hi Markus, On Tue, 2026-01-06 at 21:25 +0100, Markus Schneider-Pargmann wrote: > > I think we would need to discuss this with TI via our FAE, because the change > > in question has both been discussed with former FAE and the technical team > > behind, and adopted in TI SDK. > > > > Or have you already discused this with corresponding TI HW team? > > > > Which hardware is affected, is it the official SK-AM62A-LP? > > Is MMC2 the SD-card? > > I only tested my am62a board on u-boot v2026.01. It is a SK-AM62A-LP. > MMC2 is the SD-card and mmc1 in the devicetree. just wanted to let you know, I was able to reproduce the problems with SD card access via MMC2 under Linux on AM623 with ST enabled. We will seek clarification from TI on why this happens, which peripherals are affected and what should be the course of actions. -- Alexander Sverdlin.
On 23:57-20260107, Alexander Sverdlin wrote: > Hi Markus, > > On Tue, 2026-01-06 at 21:25 +0100, Markus Schneider-Pargmann wrote: > > > I think we would need to discuss this with TI via our FAE, because the change > > > in question has both been discussed with former FAE and the technical team > > > behind, and adopted in TI SDK. > > > > > > Or have you already discused this with corresponding TI HW team? > > > > > > Which hardware is affected, is it the official SK-AM62A-LP? > > > Is MMC2 the SD-card? > > > > I only tested my am62a board on u-boot v2026.01. It is a SK-AM62A-LP. > > MMC2 is the SD-card and mmc1 in the devicetree. > > just wanted to let you know, I was able to reproduce the problems with SD > card access via MMC2 under Linux on AM623 with ST enabled. > > We will seek clarification from TI on why this happens, which peripherals > are affected and what should be the course of actions. I have passed this up the chain here at TI. What confuses the heck out of me is this: from an internal email chain I am privy to, i am being told that "the ST_EN bit in every PADCONFIG register should never be changed from its power-on default state of 0b1" and the fact that Linux kernel has been stable with the setting for a long period, So I am confused why U-Boot would show this instability.. I don't have answers at the moment. until we clarify the reasoning, I am going to have to hold off this given that kernel behavior has not regressed that I am aware of. -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D https://ti.com/opensource
Hi Nishanth! > > > > I think we would need to discuss this with TI via our FAE, because the change > > > > in question has both been discussed with former FAE and the technical team > > > > behind, and adopted in TI SDK. > > > > > > > > Or have you already discused this with corresponding TI HW team? > > > > > > > > Which hardware is affected, is it the official SK-AM62A-LP? > > > > Is MMC2 the SD-card? > > > > > > I only tested my am62a board on u-boot v2026.01. It is a SK-AM62A-LP. > > > MMC2 is the SD-card and mmc1 in the devicetree. > > > > just wanted to let you know, I was able to reproduce the problems with SD > > card access via MMC2 under Linux on AM623 with ST enabled. > > > > We will seek clarification from TI on why this happens, which peripherals > > are affected and what should be the course of actions. > > > I have passed this up the chain here at TI. What confuses the heck out Great, thanks Nishanth! > of me is this: from an internal email chain I am privy to, i am being > told that "the ST_EN bit in every PADCONFIG register should never be > changed from its power-on default state of 0b1" and the fact that Linux that's the info we've got from FAE initially and... > kernel has been stable with the setting for a long period, So I am ... realized that Linux actually did the exact opposite of it since the first K3s (AM65) and though "Ouch!" That's how I quickly came up with 5b272127884b and though "finally we are safe!" And "stable" is relative, we've found it out because GPIOs did produce spurious interrupts, it's just that most of the drivers can handle it gracefully. Except interrupt event counters... > confused why U-Boot would show this instability.. I don't have answers > at the moment. until we clarify the reasoning, I am going to have to > hold off this given that kernel behavior has not regressed that I am > aware of. Indeed, I've reproduced it with AM623 in Linux [1], even though it's not TI evaluation board, it's our HW. We do have other HW design where the problem doesn't manifest itself, so ST seems to put MMC on the edge somehow. I can try to retest TI AM625 based EKs at some point, but it could take some days on my side... [1] https://lore.kernel.org/all/6c90102537c3e3f1712538ca0b165cd54d71d8c2.camel@gmail.com/ -- Alexander Sverdlin Siemens AG www.siemens.com
Hi Markus, short update from my side: > > I think we would need to discuss this with TI via our FAE, because the change > > in question has both been discussed with former FAE and the technical team > > behind, and adopted in TI SDK. I've reported this to the new FAE at TI, let's see how quickly relevant people at TI could look into it... I unfortunately don't have access to AM62A7 HW, but I've re-tested SD card on our AM623-based HW and I see no issues under Linux. > > > > + AM62AX_IOPAD(0x23c, PIN_INPUT_NOST, 0) /* (A21) MMC1_CMD */ > > > + AM62AX_IOPAD(0x234, PIN_INPUT_NOST, 0) /* (B22) MMC1_CLK */ > > > + AM62AX_IOPAD(0x230, PIN_INPUT_NOST, 0) /* (A22) MMC1_DAT0 */ > > > + AM62AX_IOPAD(0x22c, PIN_INPUT_NOST, 0) /* (B21) MMC1_DAT1 */ > > > + AM62AX_IOPAD(0x228, PIN_INPUT_NOST, 0) /* (C21) MMC1_DAT2 */ > > > + AM62AX_IOPAD(0x224, PIN_INPUT_NOST, 0) /* (D22) MMC1_DAT3 */ > > > + AM62AX_IOPAD(0x240, PIN_INPUT_NOST, 0) /* (D17) MMC1_SDCD */ > > My board is setup to boot from SD card for easier u-boot testing. So > only the mmc1 is relevant for my setup. I just tested which pins need > NOST here for the boot to work, all DAT pins need the NOST variants, > otherwise it does not boot here. Not sure if this is just my board or it > fails on other boards as well. Thanks for checking this! I'm curious: is it only U-Boot issue? Does the card work properly if you still have ST enabled in Linux? I'm a bit hesitatnt to revert the ST on these (or any other) pins without understanding what's going on in HW, because from all our discussions with TI we've concluded that ST shall be used on all pins without any drawbacks. Getting this back to TI will also help them to figure out the HW requirements and document them better. I'll keep you informed, shall I have any new info... -- Alexander Sverdlin.
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