Add some of the UFS symbol rx/tx muxes were not initially described.
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
---
Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml | 8 +++++++-
include/dt-bindings/clock/qcom,x1e80100-gcc.h | 3 +++
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml
index 1b15b507095455c93b1ba39404cafbb6f96be5a9..881a5dd8d06f924a4627db5f8d17ad147a1011dd 100644
--- a/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml
@@ -62,6 +62,9 @@ properties:
- description: USB4_1 PHY max PIPE clock source
- description: USB4_2 PHY PCIE PIPE clock source
- description: USB4_2 PHY max PIPE clock source
+ - description: UFS PHY RX Symbol 0 clock source
+ - description: UFS PHY RX Symbol 1 clock source
+ - description: UFS PHY TX Symbol 0 clock source
power-domains:
description:
@@ -121,7 +124,10 @@ examples:
<&usb4_1_phy_pcie_pipe_clk>,
<&usb4_1_phy_max_pipe_clk>,
<&usb4_2_phy_pcie_pipe_clk>,
- <&usb4_2_phy_max_pipe_clk>;
+ <&usb4_2_phy_max_pipe_clk>,
+ <&ufs_phy_rx_symbol_0>,
+ <&ufs_phy_rx_symbol_1>,
+ <&ufs_phy_tx_symbol_0>;
power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
diff --git a/include/dt-bindings/clock/qcom,x1e80100-gcc.h b/include/dt-bindings/clock/qcom,x1e80100-gcc.h
index 62aa1242559270dd3bd31cd10322ee265468b8e4..d905804e64654dc8d01ab20eb1106cebf6e54b0e 100644
--- a/include/dt-bindings/clock/qcom,x1e80100-gcc.h
+++ b/include/dt-bindings/clock/qcom,x1e80100-gcc.h
@@ -387,6 +387,9 @@
#define GCC_USB4_2_PHY_RX0_CLK_SRC 377
#define GCC_USB4_2_PHY_RX1_CLK_SRC 378
#define GCC_USB4_2_PHY_SYS_CLK_SRC 379
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 380
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 381
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 382
/* GCC power domains */
#define GCC_PCIE_0_TUNNEL_GDSC 0
--
2.34.1