Document the device tree bindings for UFS host controller on
Qualcomm SA8255P platform which integrates firmware-managed
resources.
The platform firmware implements the SCMI server and manages
resources such as the PHY, clocks, regulators and resets via the
SCMI power protocol. As a result, the OS-visible DT only describes
the controller’s MMIO, interrupt, IOMMU and power-domain interfaces.
The generic "qcom,ufshc" and "jedec,ufs-2.0" compatible strings are
removed from the binding, since this firmware managed design won't
be compatible with the drivers doing full resource management.
Co-developed-by: Anjana Hari <anjana.hari@oss.qualcomm.com>
Signed-off-by: Anjana Hari <anjana.hari@oss.qualcomm.com>
Signed-off-by: Ram Kumar Dwivedi <ram.dwivedi@oss.qualcomm.com>
---
.../bindings/ufs/qcom,sa8255p-ufshc.yaml | 62 +++++++++++++++++++
1 file changed, 62 insertions(+)
create mode 100644 Documentation/devicetree/bindings/ufs/qcom,sa8255p-ufshc.yaml
diff --git a/Documentation/devicetree/bindings/ufs/qcom,sa8255p-ufshc.yaml b/Documentation/devicetree/bindings/ufs/qcom,sa8255p-ufshc.yaml
new file mode 100644
index 000000000000..846a3552a9e4
--- /dev/null
+++ b/Documentation/devicetree/bindings/ufs/qcom,sa8255p-ufshc.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ufs/qcom,sa8255p-ufshc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SA8255P UFS Host Controller
+
+maintainers:
+ - Ram Kumar Dwivedi <ram.dwivedi@oss.qualcomm.com>
+ - Anjana Hari <anjana.hari@oss.qualcomm.com>
+
+properties:
+ compatible:
+ const: qcom,sa8255p-ufshc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ iommus:
+ maxItems: 1
+
+ dma-coherent: true
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+ - iommus
+ - dma-coherent
+
+allOf:
+ - $ref: ufs-common.yaml
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ufshc@1d84000 {
+ compatible = "qcom,sa8255p-ufshc";
+ reg = <0x01d84000 0x3000>;
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+ lanes-per-direction = <2>;
+
+ iommus = <&apps_smmu 0x100 0x0>;
+ power-domains = <&scmi3_pd 0>;
+ dma-coherent;
+ };
+ };
--
2.34.1
On Wed, Dec 31, 2025 at 10:25:51AM +0530, Ram Kumar Dwivedi wrote:
> Document the device tree bindings for UFS host controller on
> Qualcomm SA8255P platform which integrates firmware-managed
> resources.
>
> The platform firmware implements the SCMI server and manages
> resources such as the PHY, clocks, regulators and resets via the
> SCMI power protocol. As a result, the OS-visible DT only describes
> the controller’s MMIO, interrupt, IOMMU and power-domain interfaces.
>
> The generic "qcom,ufshc" and "jedec,ufs-2.0" compatible strings are
> removed from the binding, since this firmware managed design won't
> be compatible with the drivers doing full resource management.
>
> Co-developed-by: Anjana Hari <anjana.hari@oss.qualcomm.com>
> Signed-off-by: Anjana Hari <anjana.hari@oss.qualcomm.com>
> Signed-off-by: Ram Kumar Dwivedi <ram.dwivedi@oss.qualcomm.com>
> ---
> .../bindings/ufs/qcom,sa8255p-ufshc.yaml | 62 +++++++++++++++++++
> 1 file changed, 62 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/ufs/qcom,sa8255p-ufshc.yaml
>
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + soc {
> + #address-cells = <1>;
> + #size-cells = <1>;
This didn't really improve. You don't need 'soc' node at all. Please
drop it.
> +
> + ufshc@1d84000 {
> + compatible = "qcom,sa8255p-ufshc";
> + reg = <0x01d84000 0x3000>;
> + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
> + lanes-per-direction = <2>;
> +
> + iommus = <&apps_smmu 0x100 0x0>;
> + power-domains = <&scmi3_pd 0>;
> + dma-coherent;
> + };
> + };
> --
> 2.34.1
>
--
With best wishes
Dmitry
On 31/12/2025 06:19, Dmitry Baryshkov wrote:
> On Wed, Dec 31, 2025 at 10:25:51AM +0530, Ram Kumar Dwivedi wrote:
>> Document the device tree bindings for UFS host controller on
>> Qualcomm SA8255P platform which integrates firmware-managed
>> resources.
>>
>> The platform firmware implements the SCMI server and manages
>> resources such as the PHY, clocks, regulators and resets via the
>> SCMI power protocol. As a result, the OS-visible DT only describes
>> the controller’s MMIO, interrupt, IOMMU and power-domain interfaces.
>>
>> The generic "qcom,ufshc" and "jedec,ufs-2.0" compatible strings are
>> removed from the binding, since this firmware managed design won't
>> be compatible with the drivers doing full resource management.
>>
>> Co-developed-by: Anjana Hari <anjana.hari@oss.qualcomm.com>
>> Signed-off-by: Anjana Hari <anjana.hari@oss.qualcomm.com>
>> Signed-off-by: Ram Kumar Dwivedi <ram.dwivedi@oss.qualcomm.com>
>> ---
>> .../bindings/ufs/qcom,sa8255p-ufshc.yaml | 62 +++++++++++++++++++
>> 1 file changed, 62 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/ufs/qcom,sa8255p-ufshc.yaml
>>
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> + soc {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>
> This didn't really improve. You don't need 'soc' node at all. Please
> drop it.
>
It was already asked by Bjorn, then I reminded that. So I wonder if
repeating three times will work?
Feels like a waste of our time if same feedback has to be repeated three
times.
Best regards,
Krzysztof
On 31-Dec-25 1:23 PM, Krzysztof Kozlowski wrote:
> On 31/12/2025 06:19, Dmitry Baryshkov wrote:
>> On Wed, Dec 31, 2025 at 10:25:51AM +0530, Ram Kumar Dwivedi wrote:
>>> Document the device tree bindings for UFS host controller on
>>> Qualcomm SA8255P platform which integrates firmware-managed
>>> resources.
>>>
>>> The platform firmware implements the SCMI server and manages
>>> resources such as the PHY, clocks, regulators and resets via the
>>> SCMI power protocol. As a result, the OS-visible DT only describes
>>> the controller’s MMIO, interrupt, IOMMU and power-domain interfaces.
>>>
>>> The generic "qcom,ufshc" and "jedec,ufs-2.0" compatible strings are
>>> removed from the binding, since this firmware managed design won't
>>> be compatible with the drivers doing full resource management.
>>>
>>> Co-developed-by: Anjana Hari <anjana.hari@oss.qualcomm.com>
>>> Signed-off-by: Anjana Hari <anjana.hari@oss.qualcomm.com>
>>> Signed-off-by: Ram Kumar Dwivedi <ram.dwivedi@oss.qualcomm.com>
>>> ---
>>> .../bindings/ufs/qcom,sa8255p-ufshc.yaml | 62 +++++++++++++++++++
>>> 1 file changed, 62 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/ufs/qcom,sa8255p-ufshc.yaml
>>>
>>> +
>>> +examples:
>>> + - |
>>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +
>>> + soc {
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>
>> This didn't really improve. You don't need 'soc' node at all. Please
>> drop it.
>>
>
> It was already asked by Bjorn, then I reminded that. So I wonder if
> repeating three times will work?
>
> Feels like a waste of our time if same feedback has to be repeated three
> times.
Hi Krzysztof and Dmitry,
I have removed the address-cells and size-cells in latest patchset.
Thanks,
Ram.
>
> Best regards,
> Krzysztof
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