PCI/ASPM: Avoid L0s and L1 on Sophgo 2042/2044 PCIe Root Ports

[PATCH 0/2] PCI/ASPM: Avoid L0s and L1 on Sophgo 2042/2044 PCIe Root Ports

Posted by Inochi Amaoto 1 month, 1 week ago

Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM
states for devicetree platforms") force enable ASPM on all device tree
platform, the SG2042/SG2044 PCIe Root Ports breaks as it advertises L0s
and L1 capabilities without supporting it.

Override the L0s and L1 Support advertised in Link Capabilities by the
SG2042/SG2044 Root Ports so we don't try to enable those states.

Inochi Amaoto (2):
  PCI/ASPM: Avoid L0s and L1 on Sophgo 2042 PCIe [1f1c:2042] Root Ports
  PCI/ASPM: Avoid L0s and L1 on Sophgo 2044 PCIe [1f1c:2044] Root Ports

 drivers/pci/quirks.c    | 2 ++
 include/linux/pci_ids.h | 2 ++
 2 files changed, 4 insertions(+)

--
2.52.0

Re: [PATCH 0/2] PCI/ASPM: Avoid L0s and L1 on Sophgo 2042/2044 PCIe Root Ports

Posted by Bjorn Helgaas 1 month, 1 week ago

On Thu, Dec 25, 2025 at 06:05:27PM +0800, Inochi Amaoto wrote:
> Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM
> states for devicetree platforms") force enable ASPM on all device tree
> platform, the SG2042/SG2044 PCIe Root Ports breaks as it advertises L0s
> and L1 capabilities without supporting it.
> 
> Override the L0s and L1 Support advertised in Link Capabilities by the
> SG2042/SG2044 Root Ports so we don't try to enable those states.
> 
> Inochi Amaoto (2):
>   PCI/ASPM: Avoid L0s and L1 on Sophgo 2042 PCIe [1f1c:2042] Root Ports
>   PCI/ASPM: Avoid L0s and L1 on Sophgo 2044 PCIe [1f1c:2044] Root Ports
> 
>  drivers/pci/quirks.c    | 2 ++
>  include/linux/pci_ids.h | 2 ++
>  2 files changed, 4 insertions(+)

1) Can somebody at Sophgo confirm that this is a hardware erratum?  I
just want to make rule out some kind of OS bug in configuring L0s/L1.

2) Why don't we have a MAINTAINERS entry for this driver?  I failed to
notice that the series we applied
(https://lore.kernel.org/all/cover.1757643388.git.unicorn_wang@outlook.com/)
does not include a maintainer.  Chen, since you posted that series,
are you willing to sign up to maintain it?

Bjorn

Re: [PATCH 0/2] PCI/ASPM: Avoid L0s and L1 on Sophgo 2042/2044 PCIe Root Ports

Posted by Inochi Amaoto 1 month, 1 week ago

On Fri, Dec 26, 2025 at 10:30:31AM -0600, Bjorn Helgaas wrote:
> On Thu, Dec 25, 2025 at 06:05:27PM +0800, Inochi Amaoto wrote:
> > Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM
> > states for devicetree platforms") force enable ASPM on all device tree
> > platform, the SG2042/SG2044 PCIe Root Ports breaks as it advertises L0s
> > and L1 capabilities without supporting it.
> > 
> > Override the L0s and L1 Support advertised in Link Capabilities by the
> > SG2042/SG2044 Root Ports so we don't try to enable those states.
> > 
> > Inochi Amaoto (2):
> >   PCI/ASPM: Avoid L0s and L1 on Sophgo 2042 PCIe [1f1c:2042] Root Ports
> >   PCI/ASPM: Avoid L0s and L1 on Sophgo 2044 PCIe [1f1c:2044] Root Ports
> > 
> >  drivers/pci/quirks.c    | 2 ++
> >  include/linux/pci_ids.h | 2 ++
> >  2 files changed, 4 insertions(+)
> 
> 1) Can somebody at Sophgo confirm that this is a hardware erratum?  I
> just want to make rule out some kind of OS bug in configuring L0s/L1.
> 

Hi Bjorn,

I have asked for the Sophgo staff, and they already confirmed this 
hardware errata.

Regards,
Inochi

Re: [PATCH 0/2] PCI/ASPM: Avoid L0s and L1 on Sophgo 2042/2044 PCIe Root Ports

Posted by Manivannan Sadhasivam 1 month, 1 week ago

On Tue, Dec 30, 2025 at 05:45:39PM +0800, Inochi Amaoto wrote:
> On Fri, Dec 26, 2025 at 10:30:31AM -0600, Bjorn Helgaas wrote:
> > On Thu, Dec 25, 2025 at 06:05:27PM +0800, Inochi Amaoto wrote:
> > > Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM
> > > states for devicetree platforms") force enable ASPM on all device tree
> > > platform, the SG2042/SG2044 PCIe Root Ports breaks as it advertises L0s
> > > and L1 capabilities without supporting it.
> > > 
> > > Override the L0s and L1 Support advertised in Link Capabilities by the
> > > SG2042/SG2044 Root Ports so we don't try to enable those states.
> > > 
> > > Inochi Amaoto (2):
> > >   PCI/ASPM: Avoid L0s and L1 on Sophgo 2042 PCIe [1f1c:2042] Root Ports
> > >   PCI/ASPM: Avoid L0s and L1 on Sophgo 2044 PCIe [1f1c:2044] Root Ports
> > > 
> > >  drivers/pci/quirks.c    | 2 ++
> > >  include/linux/pci_ids.h | 2 ++
> > >  2 files changed, 4 insertions(+)
> > 
> > 1) Can somebody at Sophgo confirm that this is a hardware erratum?  I
> > just want to make rule out some kind of OS bug in configuring L0s/L1.
> > 
> 
> Hi Bjorn,
> 
> I have asked for the Sophgo staff, and they already confirmed this 
> hardware errata.
> 

Okay. If the hardware (Root Port) doesn't support L0s and L1, you should disable
the capability in the sophgo controller driver instead. You can use this as a
reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/controller/dwc/pcie-qcom.c#n331

Quirks is mostly meant for PCI endpoint devices (sometimes Root Ports also if
there is no host controller driver).

- Mani

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH 0/2] PCI/ASPM: Avoid L0s and L1 on Sophgo 2042/2044 PCIe Root Ports

Posted by Inochi Amaoto 1 month, 1 week ago

On Tue, Dec 30, 2025 at 03:38:11PM +0530, Manivannan Sadhasivam wrote:
> On Tue, Dec 30, 2025 at 05:45:39PM +0800, Inochi Amaoto wrote:
> > On Fri, Dec 26, 2025 at 10:30:31AM -0600, Bjorn Helgaas wrote:
> > > On Thu, Dec 25, 2025 at 06:05:27PM +0800, Inochi Amaoto wrote:
> > > > Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM
> > > > states for devicetree platforms") force enable ASPM on all device tree
> > > > platform, the SG2042/SG2044 PCIe Root Ports breaks as it advertises L0s
> > > > and L1 capabilities without supporting it.
> > > > 
> > > > Override the L0s and L1 Support advertised in Link Capabilities by the
> > > > SG2042/SG2044 Root Ports so we don't try to enable those states.
> > > > 
> > > > Inochi Amaoto (2):
> > > >   PCI/ASPM: Avoid L0s and L1 on Sophgo 2042 PCIe [1f1c:2042] Root Ports
> > > >   PCI/ASPM: Avoid L0s and L1 on Sophgo 2044 PCIe [1f1c:2044] Root Ports
> > > > 
> > > >  drivers/pci/quirks.c    | 2 ++
> > > >  include/linux/pci_ids.h | 2 ++
> > > >  2 files changed, 4 insertions(+)
> > > 
> > > 1) Can somebody at Sophgo confirm that this is a hardware erratum?  I
> > > just want to make rule out some kind of OS bug in configuring L0s/L1.
> > > 
> > 
> > Hi Bjorn,
> > 
> > I have asked for the Sophgo staff, and they already confirmed this 
> > hardware errata.
> > 
> 
> Okay. If the hardware (Root Port) doesn't support L0s and L1, you should disable
> the capability in the sophgo controller driver instead. You can use this as a
> reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/controller/dwc/pcie-qcom.c#n331
> 
> Quirks is mostly meant for PCI endpoint devices (sometimes Root Ports also if
> there is no host controller driver).
> 
> - Mani
> 

Good to know, I will switch to quirks, thanks.

Regards,
Inochi