This series adds glue driver for Motorcomm YT6801 PCIe ethernet
controller, which is considered mostly compatible with DWMAC-4 IP by
inspecting the register layout[1]. It integrates a Motorcomm YT8531S PHY
(confirmed by reading PHY ID) and GMII is used to connect the PHY to
MAC[2].
The initialization logic of the MAC is mostly based on previous upstream
effort for the controller[3] and the Deepin-maintained downstream Linux
driver[4] licensed under GPL-2.0 according to its SPDX headers. However,
this series is a completely re-write of the previous patch series,
utilizing the existing DWMAC4 driver and introducing a glue driver only.
This series only aims to add basic networking functions for the
controller, features like WoL, RSS and LED control are omitted for now.
Testing is done on i3-4170, it reaches 939Mbps (TX)/932Mbps (RX) on
average,
YT6801 TX
Connecting to host 192.168.114.51, port 5201
[ 5] local 192.168.114.50 port 59372 connected to 192.168.114.51 port 5201
[ ID] Interval Transfer Bitrate Retr Cwnd
[ 5] 0.00-1.00 sec 112 MBytes 938 Mbits/sec 0 980 KBytes
[ 5] 1.00-2.00 sec 112 MBytes 940 Mbits/sec 0 1.01 MBytes
[ 5] 2.00-3.00 sec 112 MBytes 943 Mbits/sec 0 1.11 MBytes
[ 5] 3.00-4.00 sec 112 MBytes 935 Mbits/sec 0 1.11 MBytes
[ 5] 4.00-5.00 sec 113 MBytes 947 Mbits/sec 0 1.11 MBytes
[ 5] 5.00-6.00 sec 112 MBytes 940 Mbits/sec 0 1.11 MBytes
[ 5] 6.00-7.00 sec 112 MBytes 938 Mbits/sec 0 1.11 MBytes
[ 5] 7.00-8.00 sec 111 MBytes 933 Mbits/sec 0 1.11 MBytes
[ 5] 8.00-9.00 sec 112 MBytes 942 Mbits/sec 0 1.17 MBytes
[ 5] 9.00-10.00 sec 112 MBytes 938 Mbits/sec 0 1.17 MBytes
YT6801 RX
Connecting to host 192.168.114.50, port 5201
[ 5] local 192.168.114.51 port 34896 connected to 192.168.114.50 port 5201
[ ID] Interval Transfer Bitrate Retr Cwnd
[ 5] 0.00-1.00 sec 112 MBytes 940 Mbits/sec 0 484 KBytes
[ 5] 1.00-2.00 sec 111 MBytes 934 Mbits/sec 0 484 KBytes
[ 5] 2.00-3.00 sec 112 MBytes 936 Mbits/sec 0 718 KBytes
[ 5] 3.00-4.00 sec 112 MBytes 936 Mbits/sec 0 839 KBytes
[ 5] 4.00-5.00 sec 110 MBytes 928 Mbits/sec 0 882 KBytes
[ 5] 5.00-6.00 sec 112 MBytes 940 Mbits/sec 0 882 KBytes
[ 5] 6.00-7.00 sec 112 MBytes 936 Mbits/sec 0 882 KBytes
[ 5] 7.00-8.00 sec 111 MBytes 934 Mbits/sec 0 926 KBytes
[ 5] 8.00-9.00 sec 112 MBytes 937 Mbits/sec 0 1021 KBytes
[ 5] 9.00-10.00 sec 111 MBytes 929 Mbits/sec 0 1021 KBytes
Thanks for your time and review.
[1]: https://lore.kernel.org/all/Z_T6vv013jraCzSD@shell.armlinux.org.uk/
[2]: https://lore.kernel.org/all/a48d76ac-db08-46d5-9528-f046a7b541dc@motor-comm.com/
[3]: https://lore.kernel.org/all/a48d76ac-db08-46d5-9528-f046a7b541dc@motor-comm.com/
[4]: https://github.com/deepin-community/kernel/tree/dc61248a0e21/drivers/net/ethernet/motorcomm/yt6801
Changed from v4
- PATCH 1: don't set RGMII delay register in GMII mode
- PATCH 2
- Disable ASPM L1 link state to work around problematic PCIe addon
cards
- Don't use an extra buffer when reading eFuse patches
- Call eth_random_addr() directly when generating a random MAC is
necessary
- Drop unused register field definitions
- Fix indentation for interrupt-moderation-related field definitions
- Link to v4: https://lore.kernel.org/all/20251216180331.61586-1-me@ziyao.cc/
Changed from v3
- Manually register a devres action to call pci_free_irq_vectors(),
instead of relying on the obsolete behavior of
pci_alloc_irq_vectors().
- Remove redundant call to pci_free_irq_vectors() in remove callback.
- Use my new mail address me@ziyao.cc for Sign-off-by and commit author.
- Link to v3: https://lore.kernel.org/netdev/20251124163211.54994-1-ziyao@disroot.org/
Changed from v2
- Rebase on top of next-20251124
- Switch to stmmac_plat_dat_alloc() then drop now redundant parameters
from motorcomm_default_plat_data()
- Set STMMAC_FLAG_EN_TX_LPI_CLK_PHY_CAP
- Add a comment indicating the possible source of CSR clock
- Link to v2: https://lore.kernel.org/netdev/20251111105252.53487-1-ziyao@disroot.org/
Changed from v1
- Drop (original) PATCH 1, add no vendor ID entry to linux/pci_ids.h
- Use PHY_INTERFACE_MODE_GMII instead of PHY_INTERFACE_MODE_INTERNAL
- Drop extra register read in motorcomm_efuse_read_byte()
- Rename EPHY_RESET to EPHY_MDIO_PHY_RESET, add a comment to reflect its
function better
- Use the newly-introduced generic PCI suspend/resume routines
- Generate a random MAC address instead of failing to probe when no MAC
address is programmed in eFuse (seen on some OEM EVBs).
- Collect Tested-by tags
- Link to v1: https://lore.kernel.org/netdev/20251014164746.50696-2-ziyao@disroot.org/
Yao Zi (3):
net: phy: motorcomm: Support YT8531S PHY in YT6801 Ethernet controller
net: stmmac: Add glue driver for Motorcomm YT6801 ethernet controller
MAINTAINERS: Assign myself as maintainer of Motorcomm DWMAC glue
driver
MAINTAINERS | 6 +
drivers/net/ethernet/stmicro/stmmac/Kconfig | 9 +
drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
.../ethernet/stmicro/stmmac/dwmac-motorcomm.c | 386 ++++++++++++++++++
drivers/net/phy/motorcomm.c | 4 +
5 files changed, 406 insertions(+)
create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c
--
2.51.2