From: Tzu-Hao Wei <twei@axiado.com>

The Cadence GPIO controller (CDNS IP6508) supports edge-triggered
interrupts (rising, falling, and both) via IRQ_TYPE, IRQ_VALUE,
and IRQ_ANY_EDGE registers. This commit enables support for these
modes in cdns_gpio_irq_set_type().

Although the interrupt status register is cleared on read and lacks
per-pin acknowledgment, the driver already handles this safely by
reading the ISR once and dispatching all pending interrupts immediately.
This allows edge IRQs to be used reliably in controlled environments.

Signed-off-by: Tzu-Hao Wei <twei@axiado.com>
Signed-off-by: Swark Yang <syang@axiado.com>
Signed-off-by: Prasad Bolisetty <pbolisetty@axiado.com>
---
 drivers/gpio/gpio-cadence.c | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/drivers/gpio/gpio-cadence.c b/drivers/gpio/gpio-cadence.c
index b9f39566b0f9..e34a160088fb 100644
--- a/drivers/gpio/gpio-cadence.c
+++ b/drivers/gpio/gpio-cadence.c
@@ -93,6 +93,7 @@ static int cdns_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 	struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);
 	u32 int_value;
 	u32 int_type;
+	u32 int_any;
 	u32 mask = BIT(d->hwirq);
 	int ret = 0;
 
@@ -100,24 +101,26 @@ static int cdns_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 
 	int_value = ioread32(cgpio->regs + CDNS_GPIO_IRQ_VALUE) & ~mask;
 	int_type = ioread32(cgpio->regs + CDNS_GPIO_IRQ_TYPE) & ~mask;
-
-	/*
-	 * The GPIO controller doesn't have an ACK register.
-	 * All interrupt statuses are cleared on a status register read.
-	 * Don't support edge interrupts for now.
-	 */
+	int_any = ioread32(cgpio->regs + CDNS_GPIO_IRQ_ANY_EDGE) & ~mask;
 
 	if (type == IRQ_TYPE_LEVEL_HIGH) {
 		int_type |= mask;
 		int_value |= mask;
 	} else if (type == IRQ_TYPE_LEVEL_LOW) {
 		int_type |= mask;
+	} else if (type == IRQ_TYPE_EDGE_RISING) {
+		int_value |= mask;
+	} else if (type == IRQ_TYPE_EDGE_FALLING) {
+		/* edge trigger, int_value remains cleared for falling */
+	} else if (type == IRQ_TYPE_EDGE_BOTH) {
+		int_any |= mask;
 	} else {
 		return -EINVAL;
 	}
 
 	iowrite32(int_value, cgpio->regs + CDNS_GPIO_IRQ_VALUE);
 	iowrite32(int_type, cgpio->regs + CDNS_GPIO_IRQ_TYPE);
+	iowrite32(int_any, cgpio->regs + CDNS_GPIO_IRQ_ANY_EDGE);
 
 	return ret;
 }

-- 
2.25.1

Hi Swark,

thanks for your patch! This is an important improvement for the Cadence
GPIO driver.

On Tue, Dec 23, 2025 at 8:30 AM Swark Yang <syang@axiado.com> wrote:
>
> From: Tzu-Hao Wei <twei@axiado.com>
>
> The Cadence GPIO controller (CDNS IP6508) supports edge-triggered
> interrupts (rising, falling, and both) via IRQ_TYPE, IRQ_VALUE,
> and IRQ_ANY_EDGE registers. This commit enables support for these
> modes in cdns_gpio_irq_set_type().
>
> Although the interrupt status register is cleared on read and lacks
> per-pin acknowledgment, the driver already handles this safely by
> reading the ISR once and dispatching all pending interrupts immediately.
> This allows edge IRQs to be used reliably in controlled environments.
>
> Signed-off-by: Tzu-Hao Wei <twei@axiado.com>
> Signed-off-by: Swark Yang <syang@axiado.com>
> Signed-off-by: Prasad Bolisetty <pbolisetty@axiado.com>

> -       /*
> -        * The GPIO controller doesn't have an ACK register.
> -        * All interrupt statuses are cleared on a status register read.
> -        * Don't support edge interrupts for now.
> -        */

Maybe we can instead insert a comment with a little table like this:

Interrupt polarity and trigger behaviour is configured like this:

(type, value)
(0, 0) = Falling edge triggered
(0, 1) = Rising edge triggered
(1, 0) = Low level triggered
(1, 1) = High level triggered

It's good that you also clear the "any" register for all other modes which
is something we didn't do before and could cause problems if e.g. the
boot loader set some value into that register!

+/- this small comment addition:
Reviewed-by: Linus Walleij <linusw@kernel.org>

Yours,
Linus Walleij