On 2025-12-19 21:04, Hou Tao wrote:
> From: Hou Tao <houtao1@huawei.com>
>
> Compound page support for P2PDMA memory in both kernel and user space is
> now in place. Enable it by allowing PUD_SIZE and PMD_SIZE alignment.
>
> Signed-off-by: Hou Tao <houtao1@huawei.com>
> ---
> drivers/pci/p2pdma.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/pci/p2pdma.c b/drivers/pci/p2pdma.c
> index 4a133219ac43..969bdacdcf8b 100644
> --- a/drivers/pci/p2pdma.c
> +++ b/drivers/pci/p2pdma.c
> @@ -452,9 +452,19 @@ static inline int pci_p2pdma_check_pagemap_align(struct pci_dev *pdev, int bar,
> u64 size, size_t align,
> u64 offset)
> {
> + if (has_transparent_pud_hugepage() && align == PUD_SIZE)
> + goto more_check;
> + if (has_transparent_hugepage() && align == PMD_SIZE)
> + goto more_check;
> if (align == PAGE_SIZE)
> return 0;
> return -EINVAL;
> +
> +more_check:
> + if (IS_ALIGNED(pci_resource_start(pdev, bar), align) &&
> + IS_ALIGNED(size, align) && IS_ALIGNED(offset, align))
> + return 0;
> + return -EINVAL;
> }
Again this seems strange. It's a bit unlikely to have a large BAR that
wouldn't be well aligned, but this change is now requiring all P2P
memory to be aligned to 1GB if the CPU supports PUDs. So if a particular
device only has a small (say 256MB) imperfectly aligned bar it may now
fail to be registered.
I don't think the alignment should be a property of the device. When a
mapping is created, if everything is aligned appropriately, and there is
enough free aligned P2PDMA memory, then it should map a full PUD page.
There shouldn't be other restrictions placed on the hardware to make
this work.
Logan