Add a new multi_lane_mode field to struct spi_transfer to allow
peripherals that support multiple SPI lanes to be used with a single
SPI controller.

This requires both the peripheral and the controller to have multiple
serializers connected to separate data lanes. It could also be used with
a single controller and multiple peripherals that are functioning as a
single logical device (similar to parallel memories).

Acked-by: Nuno Sá <nuno.sa@analog.com>
Acked-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Signed-off-by: David Lechner <dlechner@baylibre.com>
---

v4 changes:
* Shortened commit message (useful info will be in docs instead).
* Added whitespace to create clear grouping of macros and the field.

v3 changes:
* Renamed "buses" to "lanes" to reflect devicetree property name change.
---
 include/linux/spi/spi.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 7aff60ab257e..eba7ae8466ac 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -981,6 +981,8 @@ struct spi_res {
  *      (SPI_NBITS_SINGLE) is used.
  * @rx_nbits: number of bits used for reading. If 0 the default
  *      (SPI_NBITS_SINGLE) is used.
+ * @multi_lane_mode: How to serialize data on multiple lanes. One of the
+ *      SPI_MULTI_LANE_MODE_* values.
  * @len: size of rx and tx buffers (in bytes)
  * @speed_hz: Select a speed other than the device default for this
  *      transfer. If 0 the default (from @spi_device) is used.
@@ -1117,6 +1119,12 @@ struct spi_transfer {
 	unsigned	cs_change:1;
 	unsigned	tx_nbits:4;
 	unsigned	rx_nbits:4;
+
+#define SPI_MULTI_LANE_MODE_SINGLE	0 /* only use single lane */
+#define SPI_MULTI_LANE_MODE_STRIPE	1 /* one data word per lane */
+#define SPI_MULTI_LANE_MODE_MIRROR	2 /* same word sent on all lanes */
+	unsigned	multi_lane_mode: 2;
+
 	unsigned	timestamped:1;
 	bool		dtr_mode;
 #define	SPI_NBITS_SINGLE	0x01 /* 1-bit transfer */

-- 
2.43.0

On Fri, Dec 19, 2025 at 03:32:12PM -0600, David Lechner wrote:
> Add a new multi_lane_mode field to struct spi_transfer to allow
> peripherals that support multiple SPI lanes to be used with a single
> SPI controller.
> 
> This requires both the peripheral and the controller to have multiple
> serializers connected to separate data lanes. It could also be used with
> a single controller and multiple peripherals that are functioning as a
> single logical device (similar to parallel memories).

...

>  	unsigned	cs_change:1;
>  	unsigned	tx_nbits:4;
>  	unsigned	rx_nbits:4;
> +
> +#define SPI_MULTI_LANE_MODE_SINGLE	0 /* only use single lane */
> +#define SPI_MULTI_LANE_MODE_STRIPE	1 /* one data word per lane */
> +#define SPI_MULTI_LANE_MODE_MIRROR	2 /* same word sent on all lanes */
> +	unsigned	multi_lane_mode: 2;
> +
>  	unsigned	timestamped:1;

Btw, have you checked the layout of these bitfields? Are they all in one 32-bit
word or split? Dunno if `pahole` handles them, never actually paid attention
before.

-- 
With Best Regards,
Andy Shevchenko

On 12/27/25 9:14 AM, Andy Shevchenko wrote:
> On Fri, Dec 19, 2025 at 03:32:12PM -0600, David Lechner wrote:
>> Add a new multi_lane_mode field to struct spi_transfer to allow
>> peripherals that support multiple SPI lanes to be used with a single
>> SPI controller.
>>
>> This requires both the peripheral and the controller to have multiple
>> serializers connected to separate data lanes. It could also be used with
>> a single controller and multiple peripherals that are functioning as a
>> single logical device (similar to parallel memories).
> 
> ...
> 
>>  	unsigned	cs_change:1;
>>  	unsigned	tx_nbits:4;
>>  	unsigned	rx_nbits:4;
>> +
>> +#define SPI_MULTI_LANE_MODE_SINGLE	0 /* only use single lane */
>> +#define SPI_MULTI_LANE_MODE_STRIPE	1 /* one data word per lane */
>> +#define SPI_MULTI_LANE_MODE_MIRROR	2 /* same word sent on all lanes */
>> +	unsigned	multi_lane_mode: 2;
>> +
>>  	unsigned	timestamped:1;
> 
> Btw, have you checked the layout of these bitfields? Are they all in one 32-bit
> word or split? Dunno if `pahole` handles them, never actually paid attention
> before.
> 

There are only 14 bits used so far.