On Fri, Dec 19, 2025 at 08:22:15PM +0100, Miquel Raynal (Schneider Electric) wrote:
> Add a node describing the QSPI controller.
> There are 2 clocks feeding this controller:
> - one for the reference clock
> - one that feeds both the ahb and the apb interfaces
> As the binding expect either the ref clock, or all three (ref, ahb and
> apb) clocks, it makes sense to provide the same clock twice.
>
> Signed-off-by: Miquel Raynal (Schneider Electric) <miquel.raynal@bootlin.com>
> ---
> arch/arm/boot/dts/renesas/r9a06g032.dtsi | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
> index 8debb77803bb..a6f4670f5c45 100644
> --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi
> +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
> @@ -66,6 +66,20 @@ soc {
> #size-cells = <1>;
> ranges;
>
> + qspi0: spi@40005000 {
> + compatible = "renesas,r9a06g032-qspi", "renesas,rzn1-qspi", "cdns,qspi-nor";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x40005000 0x1000>, <0x10000000 0x10000000>;
reg is always the second property.
> + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&sysctrl R9A06G032_CLK_QSPI0>, <&sysctrl R9A06G032_HCLK_QSPI0>,
> + <&sysctrl R9A06G032_HCLK_QSPI0>;
> + clock-names = "ref", "ahb", "apb";
> + cdns,fifo-width = <4>;
> + cdns,trigger-address = <0>;
> + status = "disabled";
> + };
> +
> rtc0: rtc@40006000 {
> compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc";
> reg = <0x40006000 0x1000>;
Even nodes around tend to agree...
Best regards,
Krzysztof