Add support for the Renesas RZ/N1D400 QSPI controller.

This SoC is identified in the bindings with its other name: r9a06g032.
It is part of the RZ/N1 family, which contains a "D" and a "S"
variant. Align the compatibles used with all other IPs from the same
SoC, which requires providing 3 compatibles (the SoC specific
compatible, the family compatible, and the original Cadence IP).

Signed-off-by: Miquel Raynal (Schneider Electric) <miquel.raynal@bootlin.com>
---
 Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
index 53a52fb8b819..62948990defb 100644
--- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
+++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
@@ -80,6 +80,10 @@ properties:
           # controllers are meant to be used with flashes of all kinds,
           # ie. also NAND flashes, not only NOR flashes.
           - const: cdns,qspi-nor
+      - items:
+          - const: renesas,r9a06g032-qspi
+          - const: renesas,rzn1-qspi
+          - const: cdns,qspi-nor
       - const: cdns,qspi-nor
         deprecated: true
 

-- 
2.51.1

On Fri, Dec 19, 2025 at 08:22:03PM +0100, Miquel Raynal (Schneider Electric) wrote:
> Add support for the Renesas RZ/N1D400 QSPI controller.
> 
> This SoC is identified in the bindings with its other name: r9a06g032.
> It is part of the RZ/N1 family, which contains a "D" and a "S"
> variant. Align the compatibles used with all other IPs from the same

I don't get it. I see only one front compatible, so what is exactly
aligned?

> SoC, which requires providing 3 compatibles (the SoC specific
> compatible, the family compatible, and the original Cadence IP).
> 
> Signed-off-by: Miquel Raynal (Schneider Electric) <miquel.raynal@bootlin.com>
> ---
>  Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
> index 53a52fb8b819..62948990defb 100644
> --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
> +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
> @@ -80,6 +80,10 @@ properties:
>            # controllers are meant to be used with flashes of all kinds,
>            # ie. also NAND flashes, not only NOR flashes.
>            - const: cdns,qspi-nor
> +      - items:
> +          - const: renesas,r9a06g032-qspi

This should be enum, knowing how Renesas adds more devices.

> +          - const: renesas,rzn1-qspi
> +          - const: cdns,qspi-nor

Best regards,
Krzysztof

On 20/12/2025 at 10:35:56 +01, Krzysztof Kozlowski <krzk@kernel.org> wrote:

> On Fri, Dec 19, 2025 at 08:22:03PM +0100, Miquel Raynal (Schneider Electric) wrote:
>> Add support for the Renesas RZ/N1D400 QSPI controller.
>> 
>> This SoC is identified in the bindings with its other name: r9a06g032.
>> It is part of the RZ/N1 family, which contains a "D" and a "S"
>> variant. Align the compatibles used with all other IPs from the same
>
> I don't get it. I see only one front compatible, so what is exactly
> aligned?

Sorry, indeed the sentence isn't clear. The Cadence QSPI IP is usually
described using two compatibles, and the second is cdns,qspi-nor.

The way that has been historically used to describe RZ/N1D IPs, however,
is to use 3 compatibles. I wanted to "align" with this, ie. declaring 3
strings instead of 2.

I will change the commit log to:

    This SoC is identified in the bindings with its other name: r9a06g032.
    It is part of the RZ/N1 family, which contains a "D" and a "S"
    variant. IPs in this SoC are typically described using 3
    compatibles (the SoC specific compatible, the family compatible, and
    the original Cadence IP compatible), follow this convention.

I hope this is clearer.

Thanks,
Miquèl

> > +      - items:
> > +          - const: renesas,r9a06g032-qspi
> 
> This should be enum, knowing how Renesas adds more devices.

In general, yes...

> 
> > +          - const: renesas,rzn1-qspi

... but this platform is old. We are at N2 meanwhile. Extremly likely
that no more N1 variants come out. And the other existing ones cannot
run Linux (no SDRAM interface). I think const is fine in this case.

On 20/12/2025 at 11:13:09 +01, Wolfram Sang <wsa+renesas@sang-engineering.com> wrote:

>> > +      - items:
>> > +          - const: renesas,r9a06g032-qspi
>> 
>> This should be enum, knowing how Renesas adds more devices.
>
> In general, yes...
>
>> 
>> > +          - const: renesas,rzn1-qspi
>
> ... but this platform is old. We are at N2 meanwhile. Extremly likely
> that no more N1 variants come out. And the other existing ones cannot
> run Linux (no SDRAM interface). I think const is fine in this case.

Indeed, it is a rather old SoC, unlikely to get new cousins, but I don't
mind switching to enum either, I like future proof descriptions :), so
either ways I'm fine.

Cheers,
Miquèl