This series introduces a PHY driver to support PCIe on the SpacemiT K1
SoC.  The PCIe controller implementation is derived from a Synopsys
DesignWare PCIe IP.  The PHY driver supports one combination PCIe/USB
PHY as well as two PCIe-only PHYs.  The combo PHY port uses one PCIe
lane, and the other two ports each have two lanes.  All PCIe ports
operate at 5 GT/second.

The PCIe PHYs must be configured using a value that can only be
determined using the combo PHY, operating in PCIe mode.  To allow
that PHY to be used for USB, the needed calibration step is performed
by the PHY driver automatically at probe time.  Once this step is done,
the PHY can be used for either PCIe or USB.

The PCIe controller driver that was included in earlier versions of
this series has already been accepted upstream:
  a812b09a6b599 ("dt-bindings: pci: spacemit: Introduce PCIe host
		  controller")
  ff64e078e45fa ("PCI: spacemit: Add SpacemiT PCIe host driver")
However this series still includes devicetree patches to enable the
PCIe controller (along with the PHYs).

The patches that remain in version 7 of this series are unchanged;
they are simply rebased on top of Linux v6.19-rc1.  The first two
patches are the DT bindings for the PCIe and combo PCIe/USB PHY.
The third is the PHY driver, and the last two are devicetree updates
to enable the PCIe controller and PHYs.

					-Alex

Alex Elder (5):
  dt-bindings: phy: spacemit: Add SpacemiT PCIe/combo PHY
  dt-bindings: phy: spacemit: Introduce PCIe PHY
  phy: spacemit: Introduce PCIe/combo PHY
  riscv: dts: spacemit: Add a PCIe regulator
  riscv: dts: spacemit: PCIe and PHY-related updates

 .../bindings/phy/spacemit,k1-combo-phy.yaml   | 114 +++
 .../bindings/phy/spacemit,k1-pcie-phy.yaml    |  71 ++
 .../boot/dts/spacemit/k1-bananapi-f3.dts      |  44 ++
 arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi  |  33 +
 arch/riscv/boot/dts/spacemit/k1.dtsi          | 176 +++++
 drivers/phy/Kconfig                           |  11 +
 drivers/phy/Makefile                          |   1 +
 drivers/phy/phy-spacemit-k1-pcie.c            | 670 ++++++++++++++++++
 8 files changed, 1120 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml
 create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml
 create mode 100644 drivers/phy/phy-spacemit-k1-pcie.c


base-commit: 8f0b4cce4481fb22653697cced8d0d04027cb1e8
-- 
2.48.1

On 12/18/25 9:12 AM, Alex Elder wrote:
> This series introduces a PHY driver to support PCIe on the SpacemiT K1
> SoC.  The PCIe controller implementation is derived from a Synopsys
> DesignWare PCIe IP.  The PHY driver supports one combination PCIe/USB
> PHY as well as two PCIe-only PHYs.  The combo PHY port uses one PCIe
> lane, and the other two ports each have two lanes.  All PCIe ports
> operate at 5 GT/second.
> 
> The PCIe PHYs must be configured using a value that can only be
> determined using the combo PHY, operating in PCIe mode.  To allow
> that PHY to be used for USB, the needed calibration step is performed
> by the PHY driver automatically at probe time.  Once this step is done,
> the PHY can be used for either PCIe or USB.
> 
> The PCIe controller driver that was included in earlier versions of
> this series has already been accepted upstream:
>    a812b09a6b599 ("dt-bindings: pci: spacemit: Introduce PCIe host
> 		  controller")
>    ff64e078e45fa ("PCI: spacemit: Add SpacemiT PCIe host driver")
> However this series still includes devicetree patches to enable the
> PCIe controller (along with the PHYs).
> 
> The patches that remain in version 7 of this series are unchanged;
> they are simply rebased on top of Linux v6.19-rc1.  The first two
> patches are the DT bindings for the PCIe and combo PCIe/USB PHY.
> The third is the PHY driver, and the last two are devicetree updates
> to enable the PCIe controller and PHYs.
> 
> 					-Alex

Yixun pointed out that I neglected to provide a summary of the
change history in this message.  Here is a link to version 6,
which summarizes prior history.  My explanation for v7 indicates
what changed since v6.
  
https://lore.kernel.org/lkml/20251113214540.2623070-1-elder@riscstar.com/

He also said I neglected to add Neil's Reviewed-by tag, which
is true.  That is here:
  
https://lore.kernel.org/all/ba532f8d-a452-40e5-af46-b58b89f70a92@linaro.org/

Sorry about that.  If requested, I can send an otherwise
unchanged version 8, but for now I'll assume that's not
necessary.

					-Alex

> Alex Elder (5):
>    dt-bindings: phy: spacemit: Add SpacemiT PCIe/combo PHY
>    dt-bindings: phy: spacemit: Introduce PCIe PHY
>    phy: spacemit: Introduce PCIe/combo PHY
>    riscv: dts: spacemit: Add a PCIe regulator
>    riscv: dts: spacemit: PCIe and PHY-related updates
> 
>   .../bindings/phy/spacemit,k1-combo-phy.yaml   | 114 +++
>   .../bindings/phy/spacemit,k1-pcie-phy.yaml    |  71 ++
>   .../boot/dts/spacemit/k1-bananapi-f3.dts      |  44 ++
>   arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi  |  33 +
>   arch/riscv/boot/dts/spacemit/k1.dtsi          | 176 +++++
>   drivers/phy/Kconfig                           |  11 +
>   drivers/phy/Makefile                          |   1 +
>   drivers/phy/phy-spacemit-k1-pcie.c            | 670 ++++++++++++++++++
>   8 files changed, 1120 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml
>   create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml
>   create mode 100644 drivers/phy/phy-spacemit-k1-pcie.c
> 
> 
> base-commit: 8f0b4cce4481fb22653697cced8d0d04027cb1e8

Hi Vinod,
 Could you take a look of this series? I suppose patch 1-3 should go via
the generic phy tree, for patch 3, it's already got Neil's R-y [1] which
Alex should collect the tag..
 the Changelog for previous versions are also dropped.. which is bad

Link: https://lore.kernel.org/all/ba532f8d-a452-40e5-af46-b58b89f70a92@linaro.org/ [1]

On 09:12 Thu 18 Dec     , Alex Elder wrote:
> This series introduces a PHY driver to support PCIe on the SpacemiT K1
> SoC.  The PCIe controller implementation is derived from a Synopsys
> DesignWare PCIe IP.  The PHY driver supports one combination PCIe/USB
> PHY as well as two PCIe-only PHYs.  The combo PHY port uses one PCIe
> lane, and the other two ports each have two lanes.  All PCIe ports
> operate at 5 GT/second.
> 
> The PCIe PHYs must be configured using a value that can only be
> determined using the combo PHY, operating in PCIe mode.  To allow
> that PHY to be used for USB, the needed calibration step is performed
> by the PHY driver automatically at probe time.  Once this step is done,
> the PHY can be used for either PCIe or USB.
> 
> The PCIe controller driver that was included in earlier versions of
> this series has already been accepted upstream:
>   a812b09a6b599 ("dt-bindings: pci: spacemit: Introduce PCIe host
> 		  controller")
>   ff64e078e45fa ("PCI: spacemit: Add SpacemiT PCIe host driver")
> However this series still includes devicetree patches to enable the
> PCIe controller (along with the PHYs).
> 
> The patches that remain in version 7 of this series are unchanged;
> they are simply rebased on top of Linux v6.19-rc1.  The first two
> patches are the DT bindings for the PCIe and combo PCIe/USB PHY.
> The third is the PHY driver, and the last two are devicetree updates
> to enable the PCIe controller and PHYs.
> 
> 					-Alex
> 
> Alex Elder (5):
>   dt-bindings: phy: spacemit: Add SpacemiT PCIe/combo PHY
>   dt-bindings: phy: spacemit: Introduce PCIe PHY
>   phy: spacemit: Introduce PCIe/combo PHY
>   riscv: dts: spacemit: Add a PCIe regulator
>   riscv: dts: spacemit: PCIe and PHY-related updates
> 
anyway, for this series, I've also tested on bananapi with nvme card, so

Tested-by: Yixun Lan <dlan@gentoo.org>

-- 
Yixun Lan (dlan)

On Thu, 18 Dec 2025 09:12:26 -0600, Alex Elder wrote:
> This series introduces a PHY driver to support PCIe on the SpacemiT K1
> SoC.  The PCIe controller implementation is derived from a Synopsys
> DesignWare PCIe IP.  The PHY driver supports one combination PCIe/USB
> PHY as well as two PCIe-only PHYs.  The combo PHY port uses one PCIe
> lane, and the other two ports each have two lanes.  All PCIe ports
> operate at 5 GT/second.
> 
> [...]

Applied, thanks!

[1/5] dt-bindings: phy: spacemit: Add SpacemiT PCIe/combo PHY
      commit: f6194de7df023ecfd5156caf8e2762487be07ef7
[2/5] dt-bindings: phy: spacemit: Introduce PCIe PHY
      commit: 326a278a3682d390269699f68e597b5ef5a57d26
[3/5] phy: spacemit: Introduce PCIe/combo PHY
      commit: 57e920b92724dd568526990c04e79ed54241c5fc

Best regards,
-- 
~Vinod

On Thu, 18 Dec 2025 09:12:26 -0600, Alex Elder wrote:
> This series introduces a PHY driver to support PCIe on the SpacemiT K1
> SoC.  The PCIe controller implementation is derived from a Synopsys
> DesignWare PCIe IP.  The PHY driver supports one combination PCIe/USB
> PHY as well as two PCIe-only PHYs.  The combo PHY port uses one PCIe
> lane, and the other two ports each have two lanes.  All PCIe ports
> operate at 5 GT/second.
> 
> [...]

Applied, thanks!

[4/5] riscv: dts: spacemit: Add a PCIe regulator
      https://github.com/spacemit-com/linux/commit/73a6c811fa0d07078c9e1eaecea76ce26fb5f10e
[5/5] riscv: dts: spacemit: PCIe and PHY-related updates
      https://github.com/spacemit-com/linux/commit/0be016a4b5d1b927de04e2e7a0a2bce51aacbfff

Best regards,
-- 
Yixun Lan