Add the device tree of the evaluation board of the EyeQ6Lplus SoC.
The board comes with 2GB of RAM, an SPI NAND connected to the octoSPI
controller, and the two SPI controllers are connected to each other via
an intermediate MCU for loopback testing. The UART of the SoC is used
as the serial console.
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
arch/mips/boot/dts/mobileye/Makefile | 1 +
arch/mips/boot/dts/mobileye/eyeq6lplus-epm6.dts | 112 ++++++++++++++++++++++++
2 files changed, 113 insertions(+)
diff --git a/arch/mips/boot/dts/mobileye/Makefile b/arch/mips/boot/dts/mobileye/Makefile
index 7cc89968aaac..9305dd01f4c8 100644
--- a/arch/mips/boot/dts/mobileye/Makefile
+++ b/arch/mips/boot/dts/mobileye/Makefile
@@ -3,3 +3,4 @@
dtb-$(CONFIG_MACH_EYEQ5) += eyeq5-epm5.dtb
dtb-$(CONFIG_MACH_EYEQ6H) += eyeq6h-epm6.dtb
+dtb-$(CONFIG_MACH_EYEQ6LPLUS) += eyeq6lplus-epm6.dtb
diff --git a/arch/mips/boot/dts/mobileye/eyeq6lplus-epm6.dts b/arch/mips/boot/dts/mobileye/eyeq6lplus-epm6.dts
new file mode 100644
index 000000000000..e42d05a4d213
--- /dev/null
+++ b/arch/mips/boot/dts/mobileye/eyeq6lplus-epm6.dts
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright 2025 Mobileye Vision Technologies Ltd.
+ */
+
+/dts-v1/;
+
+#include "eyeq6lplus.dtsi"
+
+/ {
+ compatible = "mobileye,eyeq6lplus-epm6", "mobileye,eyeq6lplus";
+ model = "Mobileye EyeQ6Lplus Evaluation board";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x1 0x00000000 0x0 0x80000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* These reserved memory regions are also defined in bootmanager
+ * for configuring inbound translation for BARS, don't change
+ * these without syncing with bootmanager
+ */
+ mhm_reserved_0: the-mhm-reserved-0 {
+ reg = <0x1 0x00000000 0x0 0x0000800>;
+ };
+ bm_logs_reserved: bm-logs-reserved {
+ reg = <0x1 0x0000800 0x0 0x000f800>;
+ };
+ shmem0_reserved: shmem@804000000 {
+ reg = <0x1 0x04000000 0x0 0x1000000>;
+ };
+ shmem1_reserved: shmem@805000000 {
+ reg = <0x1 0x05000000 0x0 0x1000000>;
+ };
+ mini_coredump0_reserved: mini-coredump0@806200000 {
+ reg = <0x1 0x06200000 0x0 0x100000>;
+ };
+ mailbox_reserved: mailbox-reserved {
+ reg = <0x1 0x06300000 0x0 0x000300>;
+ };
+ sys_logs_reserved: sys-logs-reserved {
+ reg = <0x1 0x10000000 0x0 0x800000>;
+ };
+ csl_policy_logs_reserved: csl-policy-logs-reserved {
+ reg = <0x1 0x10800000 0x0 0x10000>;
+ };
+ };
+};
+
+&ospi {
+ status = "okay";
+ flash@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ cdns,read-delay = <0>;
+ cdns,tshsl-ns = <400>;
+ cdns,tsd2d-ns = <120>;
+ cdns,tchsh-ns = <40>;
+ cdns,tslch-ns = <20>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <8>;
+ };
+};
+
+&spi0 {
+ pinctrl-0 = <&spi0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ spidev@0 {
+ compatible = "lwn,bk4-spi";
+ spi-max-frequency = <5000000>;
+ reg = <0>;
+ };
+};
+
+&spi1 {
+ pinctrl-0 = <&spi1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ slave {
+ compatible = "lwn,bk4-spi";
+ spi-max-frequency = <5000000>;
+ };
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
--
2.52.0