arch/x86/kvm/vmx/nested.c | 6 ----- arch/x86/kvm/vmx/vmcs.h | 8 ++++++ arch/x86/kvm/vmx/vmcs12.c | 55 +++++++++++++++++++++++++++++++++++++-- arch/x86/kvm/vmx/vmcs12.h | 8 ++++-- arch/x86/kvm/vmx/vmx.c | 2 ++ 5 files changed, 69 insertions(+), 10 deletions(-)
Disallow access (VMREAD/VMWRITE) to fields that the loaded incarnation of
KVM doesn't support, e.g. due to lack of hardware support, as a middle
ground between allowing access to any vmcs12 field defined by KVM (current
behavior) and gating access based on the userspace-defined vCPU model (the
most correct, but costly, implementation).
Disallowing access to unsupported fields helps a tiny bit in terms of
closing the virtualization hole (see below), but the main motivation is to
avoid having to weed out unsupported fields when synchronizing between
vmcs12 and a shadow VMCS. Because shadow VMCS accesses are done via
VMREAD and VMWRITE, KVM _must_ filter out unsupported fields (or eat
VMREAD/VMWRITE failures), and filtering out just shadow VMCS fields is
about the same amount of effort, and arguably much more confusing.
As a bonus, this also fixes a KVM-Unit-Test failure bug when running on
_hardware_ without support for TSC Scaling, which fails with the same
signature as the bug fixed by commit ba1f82456ba8 ("KVM: nVMX: Dynamically
compute max VMCS index for vmcs12"):
FAIL: VMX_VMCS_ENUM.MAX_INDEX expected: 19, actual: 17
Dynamically computing the max VMCS index only resolved the issue where KVM
was hardcoding max index, but for CPUs with TSC Scaling, that was "good
enough".
Cc: Yosry Ahmed <yosry.ahmed@linux.dev>
Link: https://lore.kernel.org/all/20251026201911.505204-22-xin@zytor.com
Link: https://lore.kernel.org/all/YR2Tf9WPNEzrE7Xg@google.com
Signed-off-by: Sean Christopherson <seanjc@google.com>
---
arch/x86/kvm/vmx/nested.c | 6 -----
arch/x86/kvm/vmx/vmcs.h | 8 ++++++
arch/x86/kvm/vmx/vmcs12.c | 55 +++++++++++++++++++++++++++++++++++++--
arch/x86/kvm/vmx/vmcs12.h | 8 ++++--
arch/x86/kvm/vmx/vmx.c | 2 ++
5 files changed, 69 insertions(+), 10 deletions(-)
diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
index 6137e5307d0f..9d8f84e3f2da 100644
--- a/arch/x86/kvm/vmx/nested.c
+++ b/arch/x86/kvm/vmx/nested.c
@@ -7074,12 +7074,6 @@ void nested_vmx_set_vmcs_shadowing_bitmap(void)
}
}
-/*
- * Indexing into the vmcs12 uses the VMCS encoding rotated left by 6. Undo
- * that madness to get the encoding for comparison.
- */
-#define VMCS12_IDX_TO_ENC(idx) ((u16)(((u16)(idx) >> 6) | ((u16)(idx) << 10)))
-
static u64 nested_vmx_calc_vmcs_enum_msr(void)
{
/*
diff --git a/arch/x86/kvm/vmx/vmcs.h b/arch/x86/kvm/vmx/vmcs.h
index b25625314658..98281e019e38 100644
--- a/arch/x86/kvm/vmx/vmcs.h
+++ b/arch/x86/kvm/vmx/vmcs.h
@@ -11,7 +11,15 @@
#include "capabilities.h"
+/*
+ * Indexing into the vmcs12 uses the VMCS encoding rotated left by 6 as a very
+ * rudimentary compression of the range of indices. The compression ratio is
+ * good enough to allow KVM to use a (very sparsely populated) array without
+ * wasting too much memory, while the "algorithm" is fast enough to be used to
+ * lookup vmcs12 fields on-demand, e.g. for emulation.
+ */
#define ROL16(val, n) ((u16)(((u16)(val) << (n)) | ((u16)(val) >> (16 - (n)))))
+#define VMCS12_IDX_TO_ENC(idx) ((u16)(((u16)(idx) >> 6) | ((u16)(idx) << 10)))
struct vmcs_hdr {
u32 revision_id:31;
diff --git a/arch/x86/kvm/vmx/vmcs12.c b/arch/x86/kvm/vmx/vmcs12.c
index 4233b5ca9461..78eca9399975 100644
--- a/arch/x86/kvm/vmx/vmcs12.c
+++ b/arch/x86/kvm/vmx/vmcs12.c
@@ -9,7 +9,7 @@
FIELD(number, name), \
[ROL16(number##_HIGH, 6)] = VMCS12_OFFSET(name) + sizeof(u32)
-const unsigned short vmcs12_field_offsets[] = {
+const __initconst u16 supported_vmcs12_field_offsets[] = {
FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
FIELD(POSTED_INTR_NV, posted_intr_nv),
FIELD(GUEST_ES_SELECTOR, guest_es_selector),
@@ -158,4 +158,55 @@ const unsigned short vmcs12_field_offsets[] = {
FIELD(HOST_SSP, host_ssp),
FIELD(HOST_INTR_SSP_TABLE, host_ssp_tbl),
};
-const unsigned int nr_vmcs12_fields = ARRAY_SIZE(vmcs12_field_offsets);
+
+u16 vmcs12_field_offsets[ARRAY_SIZE(supported_vmcs12_field_offsets)] __ro_after_init;
+unsigned int nr_vmcs12_fields __ro_after_init;
+
+#define VMCS12_CASE64(enc) case enc##_HIGH: case enc
+
+static __init bool cpu_has_vmcs12_field(unsigned int idx)
+{
+ switch (VMCS12_IDX_TO_ENC(idx)) {
+ case VIRTUAL_PROCESSOR_ID: return cpu_has_vmx_vpid();
+ case POSTED_INTR_NV: return cpu_has_vmx_posted_intr();
+ VMCS12_CASE64(TSC_MULTIPLIER): return cpu_has_vmx_tsc_scaling();
+ VMCS12_CASE64(VIRTUAL_APIC_PAGE_ADDR): return cpu_has_vmx_tpr_shadow();
+ VMCS12_CASE64(APIC_ACCESS_ADDR): return cpu_has_vmx_virtualize_apic_accesses();
+ VMCS12_CASE64(POSTED_INTR_DESC_ADDR): return cpu_has_vmx_posted_intr();
+ VMCS12_CASE64(VM_FUNCTION_CONTROL): return cpu_has_vmx_vmfunc();
+ VMCS12_CASE64(EPT_POINTER): return cpu_has_vmx_ept();
+ VMCS12_CASE64(EPTP_LIST_ADDRESS): return cpu_has_vmx_vmfunc();
+ VMCS12_CASE64(XSS_EXIT_BITMAP): return cpu_has_vmx_xsaves();
+ VMCS12_CASE64(ENCLS_EXITING_BITMAP): return cpu_has_vmx_encls_vmexit();
+ VMCS12_CASE64(GUEST_IA32_PERF_GLOBAL_CTRL): return cpu_has_load_perf_global_ctrl();
+ VMCS12_CASE64(HOST_IA32_PERF_GLOBAL_CTRL): return cpu_has_load_perf_global_ctrl();
+ case TPR_THRESHOLD: return cpu_has_vmx_tpr_shadow();
+ case SECONDARY_VM_EXEC_CONTROL: return cpu_has_secondary_exec_ctrls();
+ case GUEST_S_CET: return cpu_has_load_cet_ctrl();
+ case GUEST_SSP: return cpu_has_load_cet_ctrl();
+ case GUEST_INTR_SSP_TABLE: return cpu_has_load_cet_ctrl();
+ case HOST_S_CET: return cpu_has_load_cet_ctrl();
+ case HOST_SSP: return cpu_has_load_cet_ctrl();
+ case HOST_INTR_SSP_TABLE: return cpu_has_load_cet_ctrl();
+
+ /* KVM always emulates PML and the VMX preemption timer in software. */
+ case GUEST_PML_INDEX:
+ case VMX_PREEMPTION_TIMER_VALUE:
+ default:
+ return true;
+ }
+}
+
+void __init nested_vmx_setup_vmcs12_fields(void)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(supported_vmcs12_field_offsets); i++) {
+ if (!supported_vmcs12_field_offsets[i] ||
+ !cpu_has_vmcs12_field(i))
+ continue;
+
+ vmcs12_field_offsets[i] = supported_vmcs12_field_offsets[i];
+ nr_vmcs12_fields = i + 1;
+ }
+}
diff --git a/arch/x86/kvm/vmx/vmcs12.h b/arch/x86/kvm/vmx/vmcs12.h
index 4ad6b16525b9..e5905ba0bb42 100644
--- a/arch/x86/kvm/vmx/vmcs12.h
+++ b/arch/x86/kvm/vmx/vmcs12.h
@@ -374,8 +374,12 @@ static inline void vmx_check_vmcs12_offsets(void)
CHECK_OFFSET(guest_pml_index, 996);
}
-extern const unsigned short vmcs12_field_offsets[];
-extern const unsigned int nr_vmcs12_fields;
+extern const __initconst u16 supported_vmcs12_field_offsets[];
+
+extern u16 vmcs12_field_offsets[] __ro_after_init;
+extern unsigned int nr_vmcs12_fields __ro_after_init;
+
+void __init nested_vmx_setup_vmcs12_fields(void);
static inline short get_vmcs12_field_offset(unsigned long field)
{
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index 6b96f7aea20b..e5ad3853f51d 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -8670,6 +8670,8 @@ __init int vmx_hardware_setup(void)
* can hide/show features based on kvm_cpu_cap_has().
*/
if (nested) {
+ nested_vmx_setup_vmcs12_fields();
+
nested_vmx_setup_ctls_msrs(&vmcs_config, vmx_capability.ept);
r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
base-commit: 58e10b63777d0aebee2cf4e6c67e1a83e7edbe0f
--
2.52.0.239.gd5f0c6e74e-goog>+static __init bool cpu_has_vmcs12_field(unsigned int idx)
>+{
>+ switch (VMCS12_IDX_TO_ENC(idx)) {
>+ case VIRTUAL_PROCESSOR_ID: return cpu_has_vmx_vpid();
>+ case POSTED_INTR_NV: return cpu_has_vmx_posted_intr();
>+ VMCS12_CASE64(TSC_MULTIPLIER): return cpu_has_vmx_tsc_scaling();
>+ VMCS12_CASE64(VIRTUAL_APIC_PAGE_ADDR): return cpu_has_vmx_tpr_shadow();
>+ VMCS12_CASE64(APIC_ACCESS_ADDR): return cpu_has_vmx_virtualize_apic_accesses();
>+ VMCS12_CASE64(POSTED_INTR_DESC_ADDR): return cpu_has_vmx_posted_intr();
>+ VMCS12_CASE64(VM_FUNCTION_CONTROL): return cpu_has_vmx_vmfunc();
>+ VMCS12_CASE64(EPT_POINTER): return cpu_has_vmx_ept();
>+ VMCS12_CASE64(EPTP_LIST_ADDRESS): return cpu_has_vmx_vmfunc();
>+ VMCS12_CASE64(XSS_EXIT_BITMAP): return cpu_has_vmx_xsaves();
>+ VMCS12_CASE64(ENCLS_EXITING_BITMAP): return cpu_has_vmx_encls_vmexit();
>+ VMCS12_CASE64(GUEST_IA32_PERF_GLOBAL_CTRL): return cpu_has_load_perf_global_ctrl();
>+ VMCS12_CASE64(HOST_IA32_PERF_GLOBAL_CTRL): return cpu_has_load_perf_global_ctrl();
>+ case TPR_THRESHOLD: return cpu_has_vmx_tpr_shadow();
>+ case SECONDARY_VM_EXEC_CONTROL: return cpu_has_secondary_exec_ctrls();
>+ case GUEST_S_CET: return cpu_has_load_cet_ctrl();
>+ case GUEST_SSP: return cpu_has_load_cet_ctrl();
>+ case GUEST_INTR_SSP_TABLE: return cpu_has_load_cet_ctrl();
>+ case HOST_S_CET: return cpu_has_load_cet_ctrl();
>+ case HOST_SSP: return cpu_has_load_cet_ctrl();
>+ case HOST_INTR_SSP_TABLE: return cpu_has_load_cet_ctrl();
Most fields here are not shadowed, e.g., CET-related fields. So, the plan is
that new fields should be added here regardless of whether they are shadowed or
not, right?
And GUEST_INTR_STATUS is missing here. It depends on APICv and is handled
explicitly in init_vmcs_shadow_fields().
>+
>+ /* KVM always emulates PML and the VMX preemption timer in software. */
>+ case GUEST_PML_INDEX:
>+ case VMX_PREEMPTION_TIMER_VALUE:
>+ default:
>+ return true;
>+ }
>+}
>+
>+void __init nested_vmx_setup_vmcs12_fields(void)
>+{
>+ unsigned int i;
>+
>+ for (i = 0; i < ARRAY_SIZE(supported_vmcs12_field_offsets); i++) {
>+ if (!supported_vmcs12_field_offsets[i] ||
>+ !cpu_has_vmcs12_field(i))
>+ continue;
>+
>+ vmcs12_field_offsets[i] = supported_vmcs12_field_offsets[i];
>+ nr_vmcs12_fields = i + 1;
>+ }
>+}
>diff --git a/arch/x86/kvm/vmx/vmcs12.h b/arch/x86/kvm/vmx/vmcs12.h
>index 4ad6b16525b9..e5905ba0bb42 100644
>--- a/arch/x86/kvm/vmx/vmcs12.h
>+++ b/arch/x86/kvm/vmx/vmcs12.h
>@@ -374,8 +374,12 @@ static inline void vmx_check_vmcs12_offsets(void)
> CHECK_OFFSET(guest_pml_index, 996);
> }
>
>-extern const unsigned short vmcs12_field_offsets[];
>-extern const unsigned int nr_vmcs12_fields;
>+extern const __initconst u16 supported_vmcs12_field_offsets[];
No need to extern supported_vmcs12_field_offsets since it's only used in
vmcs12.c.
>+
>+extern u16 vmcs12_field_offsets[] __ro_after_init;
>+extern unsigned int nr_vmcs12_fields __ro_after_init;
>+
>+void __init nested_vmx_setup_vmcs12_fields(void);
>
> static inline short get_vmcs12_field_offset(unsigned long field)
> {
>diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
>index 6b96f7aea20b..e5ad3853f51d 100644
>--- a/arch/x86/kvm/vmx/vmx.c
>+++ b/arch/x86/kvm/vmx/vmx.c
>@@ -8670,6 +8670,8 @@ __init int vmx_hardware_setup(void)
> * can hide/show features based on kvm_cpu_cap_has().
> */
> if (nested) {
>+ nested_vmx_setup_vmcs12_fields();
>+
> nested_vmx_setup_ctls_msrs(&vmcs_config, vmx_capability.ept);
>
> r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
>
>base-commit: 58e10b63777d0aebee2cf4e6c67e1a83e7edbe0f
>--
>2.52.0.239.gd5f0c6e74e-goog
>
>
On Wed, Dec 17, 2025, Chao Gao wrote:
> >+static __init bool cpu_has_vmcs12_field(unsigned int idx)
> >+{
> >+ switch (VMCS12_IDX_TO_ENC(idx)) {
> >+ case VIRTUAL_PROCESSOR_ID: return cpu_has_vmx_vpid();
> >+ case POSTED_INTR_NV: return cpu_has_vmx_posted_intr();
> >+ VMCS12_CASE64(TSC_MULTIPLIER): return cpu_has_vmx_tsc_scaling();
> >+ VMCS12_CASE64(VIRTUAL_APIC_PAGE_ADDR): return cpu_has_vmx_tpr_shadow();
> >+ VMCS12_CASE64(APIC_ACCESS_ADDR): return cpu_has_vmx_virtualize_apic_accesses();
> >+ VMCS12_CASE64(POSTED_INTR_DESC_ADDR): return cpu_has_vmx_posted_intr();
> >+ VMCS12_CASE64(VM_FUNCTION_CONTROL): return cpu_has_vmx_vmfunc();
> >+ VMCS12_CASE64(EPT_POINTER): return cpu_has_vmx_ept();
> >+ VMCS12_CASE64(EPTP_LIST_ADDRESS): return cpu_has_vmx_vmfunc();
> >+ VMCS12_CASE64(XSS_EXIT_BITMAP): return cpu_has_vmx_xsaves();
> >+ VMCS12_CASE64(ENCLS_EXITING_BITMAP): return cpu_has_vmx_encls_vmexit();
> >+ VMCS12_CASE64(GUEST_IA32_PERF_GLOBAL_CTRL): return cpu_has_load_perf_global_ctrl();
> >+ VMCS12_CASE64(HOST_IA32_PERF_GLOBAL_CTRL): return cpu_has_load_perf_global_ctrl();
> >+ case TPR_THRESHOLD: return cpu_has_vmx_tpr_shadow();
> >+ case SECONDARY_VM_EXEC_CONTROL: return cpu_has_secondary_exec_ctrls();
> >+ case GUEST_S_CET: return cpu_has_load_cet_ctrl();
> >+ case GUEST_SSP: return cpu_has_load_cet_ctrl();
> >+ case GUEST_INTR_SSP_TABLE: return cpu_has_load_cet_ctrl();
> >+ case HOST_S_CET: return cpu_has_load_cet_ctrl();
> >+ case HOST_SSP: return cpu_has_load_cet_ctrl();
> >+ case HOST_INTR_SSP_TABLE: return cpu_has_load_cet_ctrl();
>
> Most fields here are not shadowed, e.g., CET-related fields. So, the plan is
> that new fields should be added here regardless of whether they are shadowed or
> not, right?
Yep. It'll be mildly annoying to keep up-to-date, but I hopefully having an
"unconditional" rule will be less confusing than limiting the checks to fields
that are allowed to hit the shadow VMCS.
> And GUEST_INTR_STATUS is missing here. It depends on APICv and is handled
> explicitly in init_vmcs_shadow_fields().
Gah, I had that one on my todo list, but got sidetracked for a week and completely
forgot about it.
Thank you!
> diff --git a/arch/x86/kvm/vmx/vmcs12.c b/arch/x86/kvm/vmx/vmcs12.c
> index 4233b5ca9461..78eca9399975 100644
> --- a/arch/x86/kvm/vmx/vmcs12.c
> +++ b/arch/x86/kvm/vmx/vmcs12.c
> @@ -9,7 +9,7 @@
> FIELD(number, name), \
> [ROL16(number##_HIGH, 6)] = VMCS12_OFFSET(name) + sizeof(u32)
>
> -const unsigned short vmcs12_field_offsets[] = {
> +const __initconst u16 supported_vmcs12_field_offsets[] = {
I initially misunderstood "supported" to mean the VMCS fields available at
runtime. I'm unsure if it's necessary to make its meaning more explicit.
E.g., prefix with kvm_?
> FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
> FIELD(POSTED_INTR_NV, posted_intr_nv),
> FIELD(GUEST_ES_SELECTOR, guest_es_selector),
> @@ -158,4 +158,55 @@ const unsigned short vmcs12_field_offsets[] = {
> FIELD(HOST_SSP, host_ssp),
> FIELD(HOST_INTR_SSP_TABLE, host_ssp_tbl),
> };
> -const unsigned int nr_vmcs12_fields = ARRAY_SIZE(vmcs12_field_offsets);
> +
> +u16 vmcs12_field_offsets[ARRAY_SIZE(supported_vmcs12_field_offsets)] __ro_after_init;
> +unsigned int nr_vmcs12_fields __ro_after_init;
> +
> +#define VMCS12_CASE64(enc) case enc##_HIGH: case enc
> +
> +static __init bool cpu_has_vmcs12_field(unsigned int idx)
> +{
> + switch (VMCS12_IDX_TO_ENC(idx)) {
> + case VIRTUAL_PROCESSOR_ID: return cpu_has_vmx_vpid();
> + case POSTED_INTR_NV: return cpu_has_vmx_posted_intr();
> + VMCS12_CASE64(TSC_MULTIPLIER): return cpu_has_vmx_tsc_scaling();
> + VMCS12_CASE64(VIRTUAL_APIC_PAGE_ADDR): return cpu_has_vmx_tpr_shadow();
> + VMCS12_CASE64(APIC_ACCESS_ADDR): return cpu_has_vmx_virtualize_apic_accesses();
> + VMCS12_CASE64(POSTED_INTR_DESC_ADDR): return cpu_has_vmx_posted_intr();
> + VMCS12_CASE64(VM_FUNCTION_CONTROL): return cpu_has_vmx_vmfunc();
> + VMCS12_CASE64(EPT_POINTER): return cpu_has_vmx_ept();
> + VMCS12_CASE64(EPTP_LIST_ADDRESS): return cpu_has_vmx_vmfunc();
> + VMCS12_CASE64(XSS_EXIT_BITMAP): return cpu_has_vmx_xsaves();
> + VMCS12_CASE64(ENCLS_EXITING_BITMAP): return cpu_has_vmx_encls_vmexit();
> + VMCS12_CASE64(GUEST_IA32_PERF_GLOBAL_CTRL): return cpu_has_load_perf_global_ctrl();
> + VMCS12_CASE64(HOST_IA32_PERF_GLOBAL_CTRL): return cpu_has_load_perf_global_ctrl();
Combine the above 2 cases?
> + case TPR_THRESHOLD: return cpu_has_vmx_tpr_shadow();
> + case SECONDARY_VM_EXEC_CONTROL: return cpu_has_secondary_exec_ctrls();
> + case GUEST_S_CET: return cpu_has_load_cet_ctrl();
> + case GUEST_SSP: return cpu_has_load_cet_ctrl();
> + case GUEST_INTR_SSP_TABLE: return cpu_has_load_cet_ctrl();
> + case HOST_S_CET: return cpu_has_load_cet_ctrl();
> + case HOST_SSP: return cpu_has_load_cet_ctrl();
> + case HOST_INTR_SSP_TABLE: return cpu_has_load_cet_ctrl();
Combine all CET cases?
On Tue, Dec 16, 2025, Xin Li wrote:
> > diff --git a/arch/x86/kvm/vmx/vmcs12.c b/arch/x86/kvm/vmx/vmcs12.c
> > index 4233b5ca9461..78eca9399975 100644
> > --- a/arch/x86/kvm/vmx/vmcs12.c
> > +++ b/arch/x86/kvm/vmx/vmcs12.c
> > @@ -9,7 +9,7 @@
> > FIELD(number, name), \
> > [ROL16(number##_HIGH, 6)] = VMCS12_OFFSET(name) + sizeof(u32)
> >
> > -const unsigned short vmcs12_field_offsets[] = {
> > +const __initconst u16 supported_vmcs12_field_offsets[] = {
>
> I initially misunderstood "supported" to mean the VMCS fields available at
> runtime. I'm unsure if it's necessary to make its meaning more explicit.
> E.g., prefix with kvm_?
Oh, good point. Ya, will do.
> > FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
> > FIELD(POSTED_INTR_NV, posted_intr_nv),
> > FIELD(GUEST_ES_SELECTOR, guest_es_selector),
> > @@ -158,4 +158,55 @@ const unsigned short vmcs12_field_offsets[] = {
> > FIELD(HOST_SSP, host_ssp),
> > FIELD(HOST_INTR_SSP_TABLE, host_ssp_tbl),
> > };
> > -const unsigned int nr_vmcs12_fields = ARRAY_SIZE(vmcs12_field_offsets);
> > +
> > +u16 vmcs12_field_offsets[ARRAY_SIZE(supported_vmcs12_field_offsets)] __ro_after_init;
> > +unsigned int nr_vmcs12_fields __ro_after_init;
> > +
> > +#define VMCS12_CASE64(enc) case enc##_HIGH: case enc
> > +
> > +static __init bool cpu_has_vmcs12_field(unsigned int idx)
> > +{
> > + switch (VMCS12_IDX_TO_ENC(idx)) {
> > + case VIRTUAL_PROCESSOR_ID: return cpu_has_vmx_vpid();
> > + case POSTED_INTR_NV: return cpu_has_vmx_posted_intr();
> > + VMCS12_CASE64(TSC_MULTIPLIER): return cpu_has_vmx_tsc_scaling();
> > + VMCS12_CASE64(VIRTUAL_APIC_PAGE_ADDR): return cpu_has_vmx_tpr_shadow();
> > + VMCS12_CASE64(APIC_ACCESS_ADDR): return cpu_has_vmx_virtualize_apic_accesses();
> > + VMCS12_CASE64(POSTED_INTR_DESC_ADDR): return cpu_has_vmx_posted_intr();
> > + VMCS12_CASE64(VM_FUNCTION_CONTROL): return cpu_has_vmx_vmfunc();
> > + VMCS12_CASE64(EPT_POINTER): return cpu_has_vmx_ept();
> > + VMCS12_CASE64(EPTP_LIST_ADDRESS): return cpu_has_vmx_vmfunc();
> > + VMCS12_CASE64(XSS_EXIT_BITMAP): return cpu_has_vmx_xsaves();
> > + VMCS12_CASE64(ENCLS_EXITING_BITMAP): return cpu_has_vmx_encls_vmexit();
> > + VMCS12_CASE64(GUEST_IA32_PERF_GLOBAL_CTRL): return cpu_has_load_perf_global_ctrl();
> > + VMCS12_CASE64(HOST_IA32_PERF_GLOBAL_CTRL): return cpu_has_load_perf_global_ctrl();
>
> Combine the above 2 cases?
>
> > + case TPR_THRESHOLD: return cpu_has_vmx_tpr_shadow();
> > + case SECONDARY_VM_EXEC_CONTROL: return cpu_has_secondary_exec_ctrls();
> > + case GUEST_S_CET: return cpu_has_load_cet_ctrl();
> > + case GUEST_SSP: return cpu_has_load_cet_ctrl();
> > + case GUEST_INTR_SSP_TABLE: return cpu_has_load_cet_ctrl();
> > + case HOST_S_CET: return cpu_has_load_cet_ctrl();
> > + case HOST_SSP: return cpu_has_load_cet_ctrl();
> > + case HOST_INTR_SSP_TABLE: return cpu_has_load_cet_ctrl();
>
> Combine all CET cases?
Yeah, will do. I was on the fence as to whether it would be a net positive to
combine them.
Thanks!
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