Document the required configuration to enable the PCIe Endpoint controller
on SA8255p which is managed by firmware using power-domain based handling.
Signed-off-by: Mrinmay Sarkar <mrinmay.sarkar@oss.qualcomm.com>
---
.../bindings/pci/qcom,pcie-ep-sa8255p.yaml | 110 +++++++++++++++++++++
1 file changed, 110 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep-sa8255p.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep-sa8255p.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..a88c39b7f8b8bc0cfdf4e62678b8ad89f2043031
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep-sa8255p.yaml
@@ -0,0 +1,110 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-ep-sa8255p.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm firmware managed PCIe Endpoint Controller
+
+description:
+ Qualcomm SA8255p SoC PCIe endpoint controller is based on the Synopsys
+ DesignWare PCIe IP which is managed by firmware.
+
+maintainers:
+ - Manivannan Sadhasivam <mani@kernel.org>
+
+properties:
+ compatible:
+ const: qcom,pcie-ep-sa8255p
+
+ reg:
+ items:
+ - description: Qualcomm-specific PARF configuration registers
+ - description: DesignWare PCIe registers
+ - description: External local bus interface registers
+ - description: Address Translation Unit (ATU) registers
+ - description: Memory region used to map remote RC address space
+ - description: BAR memory region
+ - description: DMA register space
+
+ reg-names:
+ items:
+ - const: parf
+ - const: dbi
+ - const: elbi
+ - const: atu
+ - const: addr_space
+ - const: mmio
+ - const: dma
+
+ interrupts:
+ items:
+ - description: PCIe Global interrupt
+ - description: PCIe Doorbell interrupt
+ - description: DMA interrupt
+
+ interrupt-names:
+ items:
+ - const: global
+ - const: doorbell
+ - const: dma
+
+ iommus:
+ maxItems: 1
+
+ reset-gpios:
+ description: GPIO used as PERST# input signal
+ maxItems: 1
+
+ wake-gpios:
+ description: GPIO used as WAKE# output signal
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ dma-coherent: true
+
+ num-lanes:
+ default: 2
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - interrupt-names
+ - reset-gpios
+ - power-domains
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ pcie1_ep: pcie-ep@1c10000 {
+ compatible = "qcom,sa8255p-pcie-ep";
+ reg = <0x0 0x01c10000 0x0 0x3000>,
+ <0x0 0x60000000 0x0 0xf20>,
+ <0x0 0x60000f20 0x0 0xa8>,
+ <0x0 0x60001000 0x0 0x4000>,
+ <0x0 0x60200000 0x0 0x100000>,
+ <0x0 0x01c13000 0x0 0x1000>,
+ <0x0 0x60005000 0x0 0x2000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "addr_space", "mmio", "dma";
+ interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global", "doorbell", "dma";
+ reset-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
+ dma-coherent;
+ iommus = <&pcie_smmu 0x80 0x7f>;
+ power-domains = <&scmi6_pd 1>;
+ num-lanes = <4>;
+ };
+ };
--
2.25.1On Tue, 16 Dec 2025 19:19:17 +0530, Mrinmay Sarkar wrote: > Document the required configuration to enable the PCIe Endpoint controller > on SA8255p which is managed by firmware using power-domain based handling. > > Signed-off-by: Mrinmay Sarkar <mrinmay.sarkar@oss.qualcomm.com> > --- > .../bindings/pci/qcom,pcie-ep-sa8255p.yaml | 110 +++++++++++++++++++++ > 1 file changed, 110 insertions(+) > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: dtschema/dtc warnings/errors: Documentation/devicetree/bindings/pci/qcom,pcie-ep-sa8255p.example.dtb: /example-0/soc/pcie-ep@1c10000: failed to match any schema with compatible: ['qcom,sa8255p-pcie-ep'] doc reference errors (make refcheckdocs): See https://patchwork.kernel.org/project/devicetree/patch/20251216-firmware_managed_ep-v2-1-7a731327307f@oss.qualcomm.com The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
On Tue, Dec 16, 2025 at 8:59 PM Rob Herring (Arm) <robh@kernel.org> wrote: > > > On Tue, 16 Dec 2025 19:19:17 +0530, Mrinmay Sarkar wrote: > > Document the required configuration to enable the PCIe Endpoint controller > > on SA8255p which is managed by firmware using power-domain based handling. > > > > Signed-off-by: Mrinmay Sarkar <mrinmay.sarkar@oss.qualcomm.com> > > --- > > .../bindings/pci/qcom,pcie-ep-sa8255p.yaml | 110 +++++++++++++++++++++ > > 1 file changed, 110 insertions(+) > > > > My bot found errors running 'make dt_binding_check' on your patch: > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > Documentation/devicetree/bindings/pci/qcom,pcie-ep-sa8255p.example.dtb: /example-0/soc/pcie-ep@1c10000: failed to match any schema with compatible: ['qcom,sa8255p-pcie-ep'] > > doc reference errors (make refcheckdocs): > > See https://patchwork.kernel.org/project/devicetree/patch/20251216-firmware_managed_ep-v2-1-7a731327307f@oss.qualcomm.com > > The base for the series is generally the latest rc1. A different dependency > should be noted in *this* patch. > > If you already ran 'make dt_binding_check' and didn't see the above > error(s), then make sure 'yamllint' is installed and dt-schema is up to > date: > > pip3 install dtschema --upgrade > > Please check and re-submit after running the above command yourself. Note > that DT_SCHEMA_FILES can be set to your schema file to speed up checking > your schema. However, it must be unset to test all examples with your schema. > Thanks Rob for sharing this. I already ran 'make dt_binding_check' but somehow I didn't see this error. Maybe I need to upgrade all the tools .. I will resolve this and submit again. Thanks, Mrinmay
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