arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 334 +++++++++++++++++++ 1 file changed, 334 insertions(+)
The QCS6490 rb3gen2 board uses the same Qualcomm QCM6490 platform
but has a different thermal junction temperature specification
due to package-level differences.
Update passive/hot trip thresholds to 105°C and critical trip
thresholds to 115°C for various subsystem TSENS sensors.
Disable CPU cooling maps for CPU TSENS since CPU thermal mitigation
is handled automatically in hardware on this board.
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 334 +++++++++++++++++++
1 file changed, 334 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
index f29a352b0288..a7e62e3845a6 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
@@ -1081,6 +1081,340 @@ right_spkr: speaker@0,2 {
};
};
+&thermal_zones {
+ cpu0-thermal {
+ trips {
+ /delete-node/ trip-point0;
+ /delete-node/ trip-point1;
+
+ cpu-crit {
+ temperature = <115000>;
+ };
+ };
+
+ /delete-node/ cooling-maps;
+ };
+
+ cpu1-thermal {
+ trips {
+ /delete-node/ trip-point0;
+ /delete-node/ trip-point1;
+
+ cpu-crit {
+ temperature = <115000>;
+ };
+ };
+
+ /delete-node/ cooling-maps;
+ };
+
+ cpu2-thermal {
+ trips {
+ /delete-node/ trip-point0;
+ /delete-node/ trip-point1;
+
+ cpu-crit {
+ temperature = <115000>;
+ };
+ };
+
+ /delete-node/ cooling-maps;
+ };
+
+ cpu3-thermal {
+ trips {
+ /delete-node/ trip-point0;
+ /delete-node/ trip-point1;
+
+ cpu-crit {
+ temperature = <115000>;
+ };
+ };
+
+ /delete-node/ cooling-maps;
+ };
+
+ cpu4-thermal {
+ trips {
+ /delete-node/ trip-point0;
+ /delete-node/ trip-point1;
+
+ cpu-crit {
+ temperature = <115000>;
+ };
+ };
+
+ /delete-node/ cooling-maps;
+ };
+
+ cpu5-thermal {
+ trips {
+ /delete-node/ trip-point0;
+ /delete-node/ trip-point1;
+
+ cpu-crit {
+ temperature = <115000>;
+ };
+ };
+
+ /delete-node/ cooling-maps;
+ };
+
+ cpu6-thermal {
+ trips {
+ /delete-node/ trip-point0;
+ /delete-node/ trip-point1;
+
+ cpu-crit {
+ temperature = <115000>;
+ };
+ };
+
+ /delete-node/ cooling-maps;
+ };
+
+ cpu7-thermal {
+ trips {
+ /delete-node/ trip-point0;
+ /delete-node/ trip-point1;
+
+ cpu-crit {
+ temperature = <115000>;
+ };
+ };
+
+ /delete-node/ cooling-maps;
+ };
+
+ cpu8-thermal {
+ trips {
+ /delete-node/ trip-point0;
+ /delete-node/ trip-point1;
+
+ cpu-crit {
+ temperature = <115000>;
+ };
+ };
+
+ /delete-node/ cooling-maps;
+ };
+
+ cpu9-thermal {
+ trips {
+ /delete-node/ trip-point0;
+ /delete-node/ trip-point1;
+
+ cpu-crit {
+ temperature = <115000>;
+ };
+ };
+
+ /delete-node/ cooling-maps;
+ };
+
+ cpu10-thermal {
+ trips {
+ /delete-node/ trip-point0;
+ /delete-node/ trip-point1;
+
+ cpu-crit {
+ temperature = <115000>;
+ };
+ };
+
+ /delete-node/ cooling-maps;
+ };
+
+ cpu11-thermal {
+ trips {
+ /delete-node/ trip-point0;
+ /delete-node/ trip-point1;
+
+ cpu-crit {
+ temperature = <115000>;
+ };
+ };
+
+ /delete-node/ cooling-maps;
+ };
+
+ aoss0-thermal {
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ };
+
+ aoss0-crit {
+ temperature = <115000>;
+ };
+ };
+ };
+
+ aoss1-thermal {
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ };
+
+ aoss1-crit {
+ temperature = <115000>;
+ };
+ };
+ };
+
+ cpuss0-thermal {
+ trips {
+ /delete-node/ trip-point0;
+
+ cluster0-crit {
+ temperature = <115000>;
+ };
+ };
+ };
+
+ cpuss1-thermal {
+ trips {
+ /delete-node/ trip-point0;
+
+ cluster0-crit {
+ temperature = <115000>;
+ };
+ };
+ };
+
+ gpuss0-thermal {
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ };
+
+ gpuss0-crit {
+ temperature = <115000>;
+ };
+ };
+ };
+
+ gpuss1-thermal {
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ };
+
+ gpuss1-crit {
+ temperature = <115000>;
+ };
+ };
+ };
+
+ nspss0-thermal {
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ };
+
+ nspss0-crit {
+ temperature = <115000>;
+ };
+ };
+ };
+
+ nspss1-thermal {
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ };
+
+ nspss1-crit {
+ temperature = <115000>;
+ };
+ };
+ };
+
+ video-thermal {
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ };
+
+ video-crit {
+ temperature = <115000>;
+ };
+ };
+ };
+
+ ddr-thermal {
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ };
+
+ ddr-crit {
+ temperature = <115000>;
+ };
+ };
+ };
+
+ mdmss0-thermal {
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ };
+
+ mdmss0-crit {
+ temperature = <115000>;
+ };
+ };
+ };
+
+ mdmss1-thermal {
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ };
+
+ mdmss1-crit {
+ temperature = <115000>;
+ };
+ };
+ };
+
+ mdmss2-thermal {
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ };
+
+ mdmss2-crit {
+ temperature = <115000>;
+ };
+ };
+ };
+
+ mdmss3-thermal {
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ };
+
+ mdmss3-crit {
+ temperature = <115000>;
+ };
+ };
+ };
+
+ camera0-thermal {
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ };
+
+ camera0-crit {
+ temperature = <115000>;
+ };
+ };
+ };
+};
+
&tlmm {
gpio-reserved-ranges = <32 2>, /* ADSP */
<48 4>; /* NFC */
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
On Mon, Dec 15, 2025 at 04:29:34PM +0530, Manaf Meethalavalappu Pallikunhi wrote: > The QCS6490 rb3gen2 board uses the same Qualcomm QCM6490 platform Is there a difference between QCS6490 and QCM6490 or between QC[SM]6490 and SC7280? > but has a different thermal junction temperature specification > due to package-level differences. > > Update passive/hot trip thresholds to 105°C and critical trip > thresholds to 115°C for various subsystem TSENS sensors. > > Disable CPU cooling maps for CPU TSENS since CPU thermal mitigation > is handled automatically in hardware on this board. Is it a peculiarity of the RB3 Gen2 or is it that Chrome devices didn't do it? What about QCM6490 IDP or FairPhone FP5? > > Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com> > --- > arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 334 +++++++++++++++++++ > 1 file changed, 334 insertions(+) > -- With best wishes Dmitry
Hi Dmitry, On 12/16/2025 1:21 AM, Dmitry Baryshkov wrote: > On Mon, Dec 15, 2025 at 04:29:34PM +0530, Manaf Meethalavalappu Pallikunhi wrote: >> The QCS6490 rb3gen2 board uses the same Qualcomm QCM6490 platform > Is there a difference between QCS6490 and QCM6490 or between QC[SM]6490 > and SC7280? Difference is only for qcs6490-rb3gen2 (IOT ). > >> but has a different thermal junction temperature specification >> due to package-level differences. >> >> Update passive/hot trip thresholds to 105°C and critical trip >> thresholds to 115°C for various subsystem TSENS sensors. >> >> Disable CPU cooling maps for CPU TSENS since CPU thermal mitigation >> is handled automatically in hardware on this board. > Is it a peculiarity of the RB3 Gen2 or is it that Chrome devices didn't > do it? What about QCM6490 IDP or FairPhone FP5? Chrome devices do not perform automatic thermal mitigation, whereas all other boards handle it automatically. I will push another patch to disable cpu mitigation for all other boards other than chrome. Thanks, Manaf > >> Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com> >> --- >> arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 334 +++++++++++++++++++ >> 1 file changed, 334 insertions(+) >>
On Tue, Dec 16, 2025 at 01:01:01PM +0530, Manaf Meethalavalappu Pallikunhi wrote: > Hi Dmitry, > > > On 12/16/2025 1:21 AM, Dmitry Baryshkov wrote: > > On Mon, Dec 15, 2025 at 04:29:34PM +0530, Manaf Meethalavalappu Pallikunhi wrote: > > > The QCS6490 rb3gen2 board uses the same Qualcomm QCM6490 platform > > Is there a difference between QCS6490 and QCM6490 or between QC[SM]6490 > > and SC7280? > Difference is only for qcs6490-rb3gen2 (IOT ). > > > > > but has a different thermal junction temperature specification > > > due to package-level differences. > > > > > > Update passive/hot trip thresholds to 105°C and critical trip > > > thresholds to 115°C for various subsystem TSENS sensors. > > > > > > Disable CPU cooling maps for CPU TSENS since CPU thermal mitigation > > > is handled automatically in hardware on this board. > > Is it a peculiarity of the RB3 Gen2 or is it that Chrome devices didn't > > do it? What about QCM6490 IDP or FairPhone FP5? > > Chrome devices do not perform automatic thermal mitigation, whereas all > other boards handle it automatically. I will push another patch to disable > cpu mitigation for all other boards other than chrome. > This matches what we're doing everywhere else (i.e. rely on LMh/OSM/EPSS to do the fast throttling of cores), so I'd expect that this should apply to all non-Chrome boards... Instead of doing this for every board, can we push the cpu/cooling-maps into e.g. sc7280-chrome-common.dtsi? If I understand you correctly, we'd still have the desire to adjust the temperature values, but that's a smaller per-board change. Regards, Bjorn > Thanks, > > Manaf > > > > > > Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com> > > > --- > > > arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 334 +++++++++++++++++++ > > > 1 file changed, 334 insertions(+) > > >
On 12/16/25 8:31 AM, Manaf Meethalavalappu Pallikunhi wrote: > Hi Dmitry, > > > On 12/16/2025 1:21 AM, Dmitry Baryshkov wrote: >> On Mon, Dec 15, 2025 at 04:29:34PM +0530, Manaf Meethalavalappu Pallikunhi wrote: >>> The QCS6490 rb3gen2 board uses the same Qualcomm QCM6490 platform >> Is there a difference between QCS6490 and QCM6490 or between QC[SM]6490 >> and SC7280? > Difference is only for qcs6490-rb3gen2 (IOT ). FYI https://lpc.events/event/19/contributions/2245/ Konrad
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