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[PATCH 6/7] perf/x86/intel/uncore: Update DMR uncore constraints preliminarily

Zide Chen posted 7 patches 1 month, 4 weeks ago
[PATCH 6/7] perf/x86/intel/uncore: Update DMR uncore constraints preliminarily
Posted by Zide Chen 1 month, 4 weeks ago 
Update event constraints base on the latest DMR uncore event list.

Signed-off-by: Zide Chen <zide.chen@intel.com>
---
 arch/x86/events/intel/uncore_snbep.c | 81 ++++++++++++++++++++++++++++
 1 file changed, 81 insertions(+)

diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index e5b95fa75313..8068b9404ecb 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -6760,10 +6760,72 @@ static const struct attribute_group dmr_cxlcm_uncore_format_group = {
 	.attrs = dmr_cxlcm_uncore_formats_attr,
 };
 
+static struct event_constraint dmr_uncore_cxlcm_constraints[] = {
+	UNCORE_EVENT_CONSTRAINT(0x1, 0x0f),
+	UNCORE_EVENT_CONSTRAINT(0x2, 0x0f),
+	UNCORE_EVENT_CONSTRAINT(0x3, 0x0f),
+	UNCORE_EVENT_CONSTRAINT(0x4, 0x0f),
+	UNCORE_EVENT_CONSTRAINT(0x5, 0x0f),
+	UNCORE_EVENT_CONSTRAINT(0x6, 0x0f),
+	UNCORE_EVENT_CONSTRAINT(0x7, 0x0f),
+	UNCORE_EVENT_CONSTRAINT(0x8, 0x0f),
+	UNCORE_EVENT_CONSTRAINT(0x9, 0x0f),
+	UNCORE_EVENT_CONSTRAINT(0xa, 0x0f),
+	UNCORE_EVENT_CONSTRAINT(0xb, 0x0f),
+	UNCORE_EVENT_CONSTRAINT(0xc, 0x0f),
+	UNCORE_EVENT_CONSTRAINT(0xd, 0x0f),
+	UNCORE_EVENT_CONSTRAINT(0xe, 0x0f),
+	UNCORE_EVENT_CONSTRAINT(0xf, 0x0f),
+	UNCORE_EVENT_CONSTRAINT(0x10, 0x0f),
+	UNCORE_EVENT_CONSTRAINT(0x11, 0x0f),
+	UNCORE_EVENT_CONSTRAINT(0x12, 0x0f),
+	UNCORE_EVENT_CONSTRAINT(0x14, 0x0f),
+	UNCORE_EVENT_CONSTRAINT(0x1d, 0x0f),
+	UNCORE_EVENT_CONSTRAINT(0x1e, 0x0f),
+	UNCORE_EVENT_CONSTRAINT(0x1f, 0x0f),
+	UNCORE_EVENT_CONSTRAINT(0x20, 0x0f),
+	UNCORE_EVENT_CONSTRAINT(0x21, 0x0f),
+	UNCORE_EVENT_CONSTRAINT(0x22, 0x0f),
+	UNCORE_EVENT_CONSTRAINT(0x23, 0x0f),
+	UNCORE_EVENT_CONSTRAINT(0x24, 0x0f),
+	UNCORE_EVENT_CONSTRAINT(0x41, 0xf0),
+	UNCORE_EVENT_CONSTRAINT(0x42, 0xf0),
+	UNCORE_EVENT_CONSTRAINT(0x43, 0xf0),
+	UNCORE_EVENT_CONSTRAINT(0x44, 0xf0),
+	UNCORE_EVENT_CONSTRAINT(0x45, 0xf0),
+	UNCORE_EVENT_CONSTRAINT(0x46, 0xf0),
+	UNCORE_EVENT_CONSTRAINT(0x47, 0xf0),
+	UNCORE_EVENT_CONSTRAINT(0x48, 0xf0),
+	UNCORE_EVENT_CONSTRAINT(0x49, 0xf0),
+	UNCORE_EVENT_CONSTRAINT(0x4a, 0xf0),
+	UNCORE_EVENT_CONSTRAINT(0x4b, 0xf0),
+	UNCORE_EVENT_CONSTRAINT(0x4c, 0xf0),
+	UNCORE_EVENT_CONSTRAINT(0x4e, 0xf0),
+	UNCORE_EVENT_CONSTRAINT(0x50, 0xf0),
+	UNCORE_EVENT_CONSTRAINT(0x51, 0xf0),
+	UNCORE_EVENT_CONSTRAINT(0x52, 0xf0),
+	UNCORE_EVENT_CONSTRAINT(0x53, 0xf0),
+	UNCORE_EVENT_CONSTRAINT(0x54, 0xf0),
+	UNCORE_EVENT_CONSTRAINT(0x55, 0xf0),
+	UNCORE_EVENT_CONSTRAINT(0x56, 0xf0),
+	UNCORE_EVENT_CONSTRAINT(0x57, 0xf0),
+	UNCORE_EVENT_CONSTRAINT(0x58, 0xf0),
+	UNCORE_EVENT_CONSTRAINT(0x59, 0xf0),
+	UNCORE_EVENT_CONSTRAINT(0x5a, 0xf0),
+	UNCORE_EVENT_CONSTRAINT(0x5b, 0xf0),
+	UNCORE_EVENT_CONSTRAINT(0x5c, 0xf0),
+	UNCORE_EVENT_CONSTRAINT(0x5d, 0xf0),
+	UNCORE_EVENT_CONSTRAINT(0x5e, 0xf0),
+	UNCORE_EVENT_CONSTRAINT(0x60, 0xf0),
+	UNCORE_EVENT_CONSTRAINT(0x61, 0xf0),
+	EVENT_CONSTRAINT_END
+};
+
 static struct intel_uncore_type dmr_uncore_cxlcm = {
 	.name			= "cxlcm",
 	.event_mask		= GENERIC_PMON_RAW_EVENT_MASK,
 	.event_mask_ext		= DMR_CXLCM_EVENT_MASK_EXT,
+	.constraints		= dmr_uncore_cxlcm_constraints,
 	.format_group		= &dmr_cxlcm_uncore_format_group,
 	.attr_update		= uncore_alias_groups,
 };
@@ -6775,9 +6837,21 @@ static struct intel_uncore_type dmr_uncore_hamvf = {
 	.attr_update		= uncore_alias_groups,
 };
 
+static struct event_constraint dmr_uncore_cbo_constraints[] = {
+	UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
+	UNCORE_EVENT_CONSTRAINT(0x19, 0x1),
+	UNCORE_EVENT_CONSTRAINT(0x1a, 0x1),
+	UNCORE_EVENT_CONSTRAINT(0x1f, 0x1),
+	UNCORE_EVENT_CONSTRAINT(0x21, 0x1),
+	UNCORE_EVENT_CONSTRAINT(0x25, 0x1),
+	UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
+	EVENT_CONSTRAINT_END
+};
+
 static struct intel_uncore_type dmr_uncore_cbo = {
 	.name			= "cbo",
 	.event_mask_ext		= DMR_HAMVF_EVENT_MASK_EXT,
+	.constraints            = dmr_uncore_cbo_constraints,
 	.format_group		= &dmr_sca_uncore_format_group,
 	.attr_update		= uncore_alias_groups,
 };
@@ -6811,9 +6885,16 @@ static struct intel_uncore_type dmr_uncore_dda = {
 	.attr_update		= uncore_alias_groups,
 };
 
+static struct event_constraint dmr_uncore_sbo_constraints[] = {
+	UNCORE_EVENT_CONSTRAINT(0x1f, 0x01),
+	UNCORE_EVENT_CONSTRAINT(0x25, 0x01),
+	EVENT_CONSTRAINT_END
+};
+
 static struct intel_uncore_type dmr_uncore_sbo = {
 	.name			= "sbo",
 	.event_mask_ext		= DMR_HAMVF_EVENT_MASK_EXT,
+	.constraints		= dmr_uncore_sbo_constraints,
 	.format_group		= &dmr_sca_uncore_format_group,
 	.attr_update		= uncore_alias_groups,
 };
-- 
2.52.0
Re: [PATCH 6/7] perf/x86/intel/uncore: Update DMR uncore constraints preliminarily
Posted by Mi, Dapeng 1 month, 2 weeks ago 
On 12/13/2025 5:00 AM, Zide Chen wrote:
> Update event constraints base on the latest DMR uncore event list.
>
> Signed-off-by: Zide Chen <zide.chen@intel.com>
> ---
>  arch/x86/events/intel/uncore_snbep.c | 81 ++++++++++++++++++++++++++++
>  1 file changed, 81 insertions(+)
>
> diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
> index e5b95fa75313..8068b9404ecb 100644
> --- a/arch/x86/events/intel/uncore_snbep.c
> +++ b/arch/x86/events/intel/uncore_snbep.c
> @@ -6760,10 +6760,72 @@ static const struct attribute_group dmr_cxlcm_uncore_format_group = {
>  	.attrs = dmr_cxlcm_uncore_formats_attr,
>  };
>  
> +static struct event_constraint dmr_uncore_cxlcm_constraints[] = {
> +	UNCORE_EVENT_CONSTRAINT(0x1, 0x0f),
> +	UNCORE_EVENT_CONSTRAINT(0x2, 0x0f),
> +	UNCORE_EVENT_CONSTRAINT(0x3, 0x0f),
> +	UNCORE_EVENT_CONSTRAINT(0x4, 0x0f),
> +	UNCORE_EVENT_CONSTRAINT(0x5, 0x0f),
> +	UNCORE_EVENT_CONSTRAINT(0x6, 0x0f),
> +	UNCORE_EVENT_CONSTRAINT(0x7, 0x0f),
> +	UNCORE_EVENT_CONSTRAINT(0x8, 0x0f),
> +	UNCORE_EVENT_CONSTRAINT(0x9, 0x0f),
> +	UNCORE_EVENT_CONSTRAINT(0xa, 0x0f),
> +	UNCORE_EVENT_CONSTRAINT(0xb, 0x0f),
> +	UNCORE_EVENT_CONSTRAINT(0xc, 0x0f),
> +	UNCORE_EVENT_CONSTRAINT(0xd, 0x0f),
> +	UNCORE_EVENT_CONSTRAINT(0xe, 0x0f),
> +	UNCORE_EVENT_CONSTRAINT(0xf, 0x0f),
> +	UNCORE_EVENT_CONSTRAINT(0x10, 0x0f),
> +	UNCORE_EVENT_CONSTRAINT(0x11, 0x0f),
> +	UNCORE_EVENT_CONSTRAINT(0x12, 0x0f),
> +	UNCORE_EVENT_CONSTRAINT(0x14, 0x0f),
> +	UNCORE_EVENT_CONSTRAINT(0x1d, 0x0f),
> +	UNCORE_EVENT_CONSTRAINT(0x1e, 0x0f),
> +	UNCORE_EVENT_CONSTRAINT(0x1f, 0x0f),
> +	UNCORE_EVENT_CONSTRAINT(0x20, 0x0f),
> +	UNCORE_EVENT_CONSTRAINT(0x21, 0x0f),
> +	UNCORE_EVENT_CONSTRAINT(0x22, 0x0f),
> +	UNCORE_EVENT_CONSTRAINT(0x23, 0x0f),
> +	UNCORE_EVENT_CONSTRAINT(0x24, 0x0f),
> +	UNCORE_EVENT_CONSTRAINT(0x41, 0xf0),
> +	UNCORE_EVENT_CONSTRAINT(0x42, 0xf0),
> +	UNCORE_EVENT_CONSTRAINT(0x43, 0xf0),
> +	UNCORE_EVENT_CONSTRAINT(0x44, 0xf0),
> +	UNCORE_EVENT_CONSTRAINT(0x45, 0xf0),
> +	UNCORE_EVENT_CONSTRAINT(0x46, 0xf0),
> +	UNCORE_EVENT_CONSTRAINT(0x47, 0xf0),
> +	UNCORE_EVENT_CONSTRAINT(0x48, 0xf0),
> +	UNCORE_EVENT_CONSTRAINT(0x49, 0xf0),
> +	UNCORE_EVENT_CONSTRAINT(0x4a, 0xf0),
> +	UNCORE_EVENT_CONSTRAINT(0x4b, 0xf0),
> +	UNCORE_EVENT_CONSTRAINT(0x4c, 0xf0),
> +	UNCORE_EVENT_CONSTRAINT(0x4e, 0xf0),
> +	UNCORE_EVENT_CONSTRAINT(0x50, 0xf0),
> +	UNCORE_EVENT_CONSTRAINT(0x51, 0xf0),
> +	UNCORE_EVENT_CONSTRAINT(0x52, 0xf0),
> +	UNCORE_EVENT_CONSTRAINT(0x53, 0xf0),
> +	UNCORE_EVENT_CONSTRAINT(0x54, 0xf0),
> +	UNCORE_EVENT_CONSTRAINT(0x55, 0xf0),
> +	UNCORE_EVENT_CONSTRAINT(0x56, 0xf0),
> +	UNCORE_EVENT_CONSTRAINT(0x57, 0xf0),
> +	UNCORE_EVENT_CONSTRAINT(0x58, 0xf0),
> +	UNCORE_EVENT_CONSTRAINT(0x59, 0xf0),
> +	UNCORE_EVENT_CONSTRAINT(0x5a, 0xf0),
> +	UNCORE_EVENT_CONSTRAINT(0x5b, 0xf0),
> +	UNCORE_EVENT_CONSTRAINT(0x5c, 0xf0),
> +	UNCORE_EVENT_CONSTRAINT(0x5d, 0xf0),
> +	UNCORE_EVENT_CONSTRAINT(0x5e, 0xf0),
> +	UNCORE_EVENT_CONSTRAINT(0x60, 0xf0),
> +	UNCORE_EVENT_CONSTRAINT(0x61, 0xf0),

Could we define a "UNCORE_EVENT_CONSTRAINT_RANGE()" macro just like what
core PMU does (refer INTEL_EVENT_CONSTRAINT_RANGE macro)? Then we don't
need to add so many lines.

Maybe like this,

diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c
index 698bcd7fe5a0..bc4367a6628e 100644
--- a/arch/x86/events/intel/uncore.c
+++ b/arch/x86/events/intel/uncore.c
@@ -437,7 +437,7 @@ uncore_get_event_constraint(struct intel_uncore_box
*box, struct perf_event *eve

        if (type->constraints) {
                for_each_event_constraint(c, type->constraints) {
-                       if ((event->hw.config & c->cmask) == c->code)
+                       if (constraint_match(c, event->hw.config))
                                return c;
                }
        }
diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h
index 338713cd7a7d..f6fcee2a505e 100644
--- a/arch/x86/events/intel/uncore.h
+++ b/arch/x86/events/intel/uncore.h
@@ -32,7 +32,8 @@
 #define UNCORE_EXTRA_PCI_DEV           0xff
 #define UNCORE_EXTRA_PCI_DEV_MAX       4

-#define UNCORE_EVENT_CONSTRAINT(c, n) EVENT_CONSTRAINT(c, n, 0xff)
+#define UNCORE_EVENT_CONSTRAINT(c, n)          EVENT_CONSTRAINT(c, n, 0xff)
+#define UNCORE_EVENT_CONSTRAINT_RANGE(c, e, n) EVENT_CONSTRAINT_RANGE(c,
e, n, 0xff)

 #define UNCORE_IGNORE_END              -1


> +	EVENT_CONSTRAINT_END
> +};
> +
>  static struct intel_uncore_type dmr_uncore_cxlcm = {
>  	.name			= "cxlcm",
>  	.event_mask		= GENERIC_PMON_RAW_EVENT_MASK,
>  	.event_mask_ext		= DMR_CXLCM_EVENT_MASK_EXT,
> +	.constraints		= dmr_uncore_cxlcm_constraints,
>  	.format_group		= &dmr_cxlcm_uncore_format_group,
>  	.attr_update		= uncore_alias_groups,
>  };
> @@ -6775,9 +6837,21 @@ static struct intel_uncore_type dmr_uncore_hamvf = {
>  	.attr_update		= uncore_alias_groups,
>  };
>  
> +static struct event_constraint dmr_uncore_cbo_constraints[] = {
> +	UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
> +	UNCORE_EVENT_CONSTRAINT(0x19, 0x1),
> +	UNCORE_EVENT_CONSTRAINT(0x1a, 0x1),
> +	UNCORE_EVENT_CONSTRAINT(0x1f, 0x1),
> +	UNCORE_EVENT_CONSTRAINT(0x21, 0x1),
> +	UNCORE_EVENT_CONSTRAINT(0x25, 0x1),
> +	UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
> +	EVENT_CONSTRAINT_END
> +};
> +
>  static struct intel_uncore_type dmr_uncore_cbo = {
>  	.name			= "cbo",
>  	.event_mask_ext		= DMR_HAMVF_EVENT_MASK_EXT,
> +	.constraints            = dmr_uncore_cbo_constraints,
>  	.format_group		= &dmr_sca_uncore_format_group,
>  	.attr_update		= uncore_alias_groups,
>  };
> @@ -6811,9 +6885,16 @@ static struct intel_uncore_type dmr_uncore_dda = {
>  	.attr_update		= uncore_alias_groups,
>  };
>  
> +static struct event_constraint dmr_uncore_sbo_constraints[] = {
> +	UNCORE_EVENT_CONSTRAINT(0x1f, 0x01),
> +	UNCORE_EVENT_CONSTRAINT(0x25, 0x01),
> +	EVENT_CONSTRAINT_END
> +};
> +
>  static struct intel_uncore_type dmr_uncore_sbo = {
>  	.name			= "sbo",
>  	.event_mask_ext		= DMR_HAMVF_EVENT_MASK_EXT,
> +	.constraints		= dmr_uncore_sbo_constraints,
>  	.format_group		= &dmr_sca_uncore_format_group,
>  	.attr_update		= uncore_alias_groups,
>  };
Re: [PATCH 6/7] perf/x86/intel/uncore: Update DMR uncore constraints preliminarily
Posted by Chen, Zide 1 month, 2 weeks ago 

On 12/22/2025 9:52 PM, Mi, Dapeng wrote:
> 
> On 12/13/2025 5:00 AM, Zide Chen wrote:
>> Update event constraints base on the latest DMR uncore event list.
>>
>> Signed-off-by: Zide Chen <zide.chen@intel.com>
>> ---
>>  arch/x86/events/intel/uncore_snbep.c | 81 ++++++++++++++++++++++++++++
>>  1 file changed, 81 insertions(+)
>>
>> diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
>> index e5b95fa75313..8068b9404ecb 100644
>> --- a/arch/x86/events/intel/uncore_snbep.c
>> +++ b/arch/x86/events/intel/uncore_snbep.c
>> @@ -6760,10 +6760,72 @@ static const struct attribute_group dmr_cxlcm_uncore_format_group = {
>>  	.attrs = dmr_cxlcm_uncore_formats_attr,
>>  };
>>  
>> +static struct event_constraint dmr_uncore_cxlcm_constraints[] = {
>> +	UNCORE_EVENT_CONSTRAINT(0x1, 0x0f),
>> +	UNCORE_EVENT_CONSTRAINT(0x2, 0x0f),
>> +	UNCORE_EVENT_CONSTRAINT(0x3, 0x0f),
>> +	UNCORE_EVENT_CONSTRAINT(0x4, 0x0f),
>> +	UNCORE_EVENT_CONSTRAINT(0x5, 0x0f),
>> +	UNCORE_EVENT_CONSTRAINT(0x6, 0x0f),
>> +	UNCORE_EVENT_CONSTRAINT(0x7, 0x0f),
>> +	UNCORE_EVENT_CONSTRAINT(0x8, 0x0f),
>> +	UNCORE_EVENT_CONSTRAINT(0x9, 0x0f),
>> +	UNCORE_EVENT_CONSTRAINT(0xa, 0x0f),
>> +	UNCORE_EVENT_CONSTRAINT(0xb, 0x0f),
>> +	UNCORE_EVENT_CONSTRAINT(0xc, 0x0f),
>> +	UNCORE_EVENT_CONSTRAINT(0xd, 0x0f),
>> +	UNCORE_EVENT_CONSTRAINT(0xe, 0x0f),
>> +	UNCORE_EVENT_CONSTRAINT(0xf, 0x0f),
>> +	UNCORE_EVENT_CONSTRAINT(0x10, 0x0f),
>> +	UNCORE_EVENT_CONSTRAINT(0x11, 0x0f),
>> +	UNCORE_EVENT_CONSTRAINT(0x12, 0x0f),
>> +	UNCORE_EVENT_CONSTRAINT(0x14, 0x0f),
>> +	UNCORE_EVENT_CONSTRAINT(0x1d, 0x0f),
>> +	UNCORE_EVENT_CONSTRAINT(0x1e, 0x0f),
>> +	UNCORE_EVENT_CONSTRAINT(0x1f, 0x0f),
>> +	UNCORE_EVENT_CONSTRAINT(0x20, 0x0f),
>> +	UNCORE_EVENT_CONSTRAINT(0x21, 0x0f),
>> +	UNCORE_EVENT_CONSTRAINT(0x22, 0x0f),
>> +	UNCORE_EVENT_CONSTRAINT(0x23, 0x0f),
>> +	UNCORE_EVENT_CONSTRAINT(0x24, 0x0f),
>> +	UNCORE_EVENT_CONSTRAINT(0x41, 0xf0),
>> +	UNCORE_EVENT_CONSTRAINT(0x42, 0xf0),
>> +	UNCORE_EVENT_CONSTRAINT(0x43, 0xf0),
>> +	UNCORE_EVENT_CONSTRAINT(0x44, 0xf0),
>> +	UNCORE_EVENT_CONSTRAINT(0x45, 0xf0),
>> +	UNCORE_EVENT_CONSTRAINT(0x46, 0xf0),
>> +	UNCORE_EVENT_CONSTRAINT(0x47, 0xf0),
>> +	UNCORE_EVENT_CONSTRAINT(0x48, 0xf0),
>> +	UNCORE_EVENT_CONSTRAINT(0x49, 0xf0),
>> +	UNCORE_EVENT_CONSTRAINT(0x4a, 0xf0),
>> +	UNCORE_EVENT_CONSTRAINT(0x4b, 0xf0),
>> +	UNCORE_EVENT_CONSTRAINT(0x4c, 0xf0),
>> +	UNCORE_EVENT_CONSTRAINT(0x4e, 0xf0),
>> +	UNCORE_EVENT_CONSTRAINT(0x50, 0xf0),
>> +	UNCORE_EVENT_CONSTRAINT(0x51, 0xf0),
>> +	UNCORE_EVENT_CONSTRAINT(0x52, 0xf0),
>> +	UNCORE_EVENT_CONSTRAINT(0x53, 0xf0),
>> +	UNCORE_EVENT_CONSTRAINT(0x54, 0xf0),
>> +	UNCORE_EVENT_CONSTRAINT(0x55, 0xf0),
>> +	UNCORE_EVENT_CONSTRAINT(0x56, 0xf0),
>> +	UNCORE_EVENT_CONSTRAINT(0x57, 0xf0),
>> +	UNCORE_EVENT_CONSTRAINT(0x58, 0xf0),
>> +	UNCORE_EVENT_CONSTRAINT(0x59, 0xf0),
>> +	UNCORE_EVENT_CONSTRAINT(0x5a, 0xf0),
>> +	UNCORE_EVENT_CONSTRAINT(0x5b, 0xf0),
>> +	UNCORE_EVENT_CONSTRAINT(0x5c, 0xf0),
>> +	UNCORE_EVENT_CONSTRAINT(0x5d, 0xf0),
>> +	UNCORE_EVENT_CONSTRAINT(0x5e, 0xf0),
>> +	UNCORE_EVENT_CONSTRAINT(0x60, 0xf0),
>> +	UNCORE_EVENT_CONSTRAINT(0x61, 0xf0),
> 
> Could we define a "UNCORE_EVENT_CONSTRAINT_RANGE()" macro just like what
> core PMU does (refer INTEL_EVENT_CONSTRAINT_RANGE macro)? Then we don't
> need to add so many lines.
> 
> Maybe like this,
> 
> diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c
> index 698bcd7fe5a0..bc4367a6628e 100644
> --- a/arch/x86/events/intel/uncore.c
> +++ b/arch/x86/events/intel/uncore.c
> @@ -437,7 +437,7 @@ uncore_get_event_constraint(struct intel_uncore_box
> *box, struct perf_event *eve
> 
>         if (type->constraints) {
>                 for_each_event_constraint(c, type->constraints) {
> -                       if ((event->hw.config & c->cmask) == c->code)
> +                       if (constraint_match(c, event->hw.config))
>                                 return c;
>                 }
>         }
> diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h
> index 338713cd7a7d..f6fcee2a505e 100644
> --- a/arch/x86/events/intel/uncore.h
> +++ b/arch/x86/events/intel/uncore.h
> @@ -32,7 +32,8 @@
>  #define UNCORE_EXTRA_PCI_DEV           0xff
>  #define UNCORE_EXTRA_PCI_DEV_MAX       4
> 
> -#define UNCORE_EVENT_CONSTRAINT(c, n) EVENT_CONSTRAINT(c, n, 0xff)
> +#define UNCORE_EVENT_CONSTRAINT(c, n)          EVENT_CONSTRAINT(c, n, 0xff)
> +#define UNCORE_EVENT_CONSTRAINT_RANGE(c, e, n) EVENT_CONSTRAINT_RANGE(c,
> e, n, 0xff)
> 
>  #define UNCORE_IGNORE_END              -1

Agreed, this is the right way to go.

Patchew 2.1-devel-b67e4c2

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