Add the nodes for the WCSS remoteproc loader on IPQ8074, so that there
a use case for the DT bindings. GCC_WCSSAON_RESET is not implemented
by the GCC reset controller, so use a placeholder value for now. Leave
the node disabled so that remoteproc doesn't start up with the missing
reset.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 79 +++++++++++++++++++++++++++
1 file changed, 79 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 256e12cf6d544..86369fa680553 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -108,6 +108,11 @@ memory@4ac00000 {
reg = <0x0 0x4ac00000 0x0 0x400000>;
no-map;
};
+
+ q6_region: wcnss@4b000000 {
+ reg = <0x0 0x4b000000 0x0 0x03700000>;
+ no-map;
+ };
};
firmware {
@@ -390,6 +395,11 @@ tcsr: syscon@1937000 {
reg = <0x01937000 0x21000>;
};
+ tcsr_q6: syscon@1945000 {
+ compatible = "qcom,tcsr-ipq8074", "syscon";
+ reg = <0x01945000 0xe000>;
+ };
+
spmi_bus: spmi@200f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0200f000 0x001000>,
@@ -1003,6 +1013,50 @@ pcie@0 {
ranges;
};
};
+
+ q6v5_wcss: remoteproc@cd00000 {
+ compatible = "qcom,ipq8074-wcss-pil";
+ reg = <0x0cd00000 0x4040>,
+ <0x004ab000 0x20>;
+ reg-names = "qdsp6",
+ "rmb";
+
+ interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>,
+ <&wcss_smp2p_in 0 0>,
+ <&wcss_smp2p_in 1 0>,
+ <&wcss_smp2p_in 2 0>,
+ <&wcss_smp2p_in 3 0>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack";
+
+ resets = <&gcc 0xffff>, /* GCC_WCSSAON_RESET */
+ <&gcc GCC_WCSS_BCR>,
+ <&gcc GCC_WCSS_Q6_BCR>;
+
+ reset-names = "wcss_aon_reset",
+ "wcss_reset",
+ "wcss_q6_reset";
+
+ memory-region = <&q6_region>;
+ qcom,halt-regs = <&tcsr_q6 0xa000 0xd000 0x0>;
+
+ qcom,smem-states = <&wcss_smp2p_out 0>,
+ <&wcss_smp2p_out 1>;
+ qcom,smem-state-names = "shutdown",
+ "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>;
+ label = "rtr";
+ qcom,remote-pid = <1>;
+ mboxes = <&apcs_glb 8>;
+ };
+ };
};
timer {
@@ -1182,4 +1236,29 @@ wcss-phyb1-crit {
};
};
};
+
+ wcss: smp2p-wcss {
+ compatible = "qcom,smp2p";
+ qcom,smem = <435>, <428>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 322 IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&apcs_glb 9>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ wcss_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ wcss_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
};
--
2.45.1On Tue, Dec 09, 2025 at 06:37:25PM -0600, Alexandru Gagniuc wrote:
> Add the nodes for the WCSS remoteproc loader on IPQ8074, so that there
> a use case for the DT bindings. GCC_WCSSAON_RESET is not implemented
> by the GCC reset controller, so use a placeholder value for now. Leave
> the node disabled so that remoteproc doesn't start up with the missing
> reset.
>
> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
> ---
> arch/arm64/boot/dts/qcom/ipq8074.dtsi | 79 +++++++++++++++++++++++++++
> 1 file changed, 79 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> index 256e12cf6d544..86369fa680553 100644
> --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> @@ -108,6 +108,11 @@ memory@4ac00000 {
> reg = <0x0 0x4ac00000 0x0 0x400000>;
> no-map;
> };
> +
> + q6_region: wcnss@4b000000 {
> + reg = <0x0 0x4b000000 0x0 0x03700000>;
> + no-map;
> + };
> };
>
> firmware {
> @@ -390,6 +395,11 @@ tcsr: syscon@1937000 {
> reg = <0x01937000 0x21000>;
> };
>
> + tcsr_q6: syscon@1945000 {
> + compatible = "qcom,tcsr-ipq8074", "syscon";
> + reg = <0x01945000 0xe000>;
> + };
> +
> spmi_bus: spmi@200f000 {
> compatible = "qcom,spmi-pmic-arb";
> reg = <0x0200f000 0x001000>,
> @@ -1003,6 +1013,50 @@ pcie@0 {
> ranges;
> };
> };
> +
> + q6v5_wcss: remoteproc@cd00000 {
> + compatible = "qcom,ipq8074-wcss-pil";
> + reg = <0x0cd00000 0x4040>,
This node is out of place. it should be sorted by the address, so it
should come after timer device.
> + <0x004ab000 0x20>;
> + reg-names = "qdsp6",
> + "rmb";
> +
> + interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>,
> + <&wcss_smp2p_in 0 0>,
> + <&wcss_smp2p_in 1 0>,
> + <&wcss_smp2p_in 2 0>,
> + <&wcss_smp2p_in 3 0>;
> + interrupt-names = "wdog",
> + "fatal",
> + "ready",
> + "handover",
> + "stop-ack";
> +
> + resets = <&gcc 0xffff>, /* GCC_WCSSAON_RESET */
> + <&gcc GCC_WCSS_BCR>,
> + <&gcc GCC_WCSS_Q6_BCR>;
> +
> + reset-names = "wcss_aon_reset",
> + "wcss_reset",
> + "wcss_q6_reset";
> +
> + memory-region = <&q6_region>;
> + qcom,halt-regs = <&tcsr_q6 0xa000 0xd000 0x0>;
> +
> + qcom,smem-states = <&wcss_smp2p_out 0>,
> + <&wcss_smp2p_out 1>;
> + qcom,smem-state-names = "shutdown",
> + "stop";
> +
> + status = "disabled";
> +
> + glink-edge {
> + interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>;
> + label = "rtr";
> + qcom,remote-pid = <1>;
> + mboxes = <&apcs_glb 8>;
> + };
> + };
> };
>
> timer {
> @@ -1182,4 +1236,29 @@ wcss-phyb1-crit {
> };
> };
> };
> +
> + wcss: smp2p-wcss {
'smp2p-wcss' < 'soc@0'
> + compatible = "qcom,smp2p";
> + qcom,smem = <435>, <428>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <GIC_SPI 322 IRQ_TYPE_EDGE_RISING>;
> +
> + mboxes = <&apcs_glb 9>;
> +
> + qcom,local-pid = <0>;
> + qcom,remote-pid = <1>;
> +
> + wcss_smp2p_out: master-kernel {
> + qcom,entry-name = "master-kernel";
> + #qcom,smem-state-cells = <1>;
> + };
> +
> + wcss_smp2p_in: slave-kernel {
> + qcom,entry-name = "slave-kernel";
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
> };
> --
> 2.45.1
>
--
With best wishes
Dmitry
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