Adjust the vendor extensions to use the same tristate selection as the
standard extensions. This will allow the vendor extensions to use the
same code paths as the standard extensions for discovery and
optimization.

Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com>
---
 arch/riscv/Kconfig.vendor                    | 25 ++++++++++++++++++++++---
 arch/riscv/kernel/vendor_extensions/Makefile | 22 +++++++++++++++-------
 drivers/perf/Kconfig                         |  2 +-
 3 files changed, 38 insertions(+), 11 deletions(-)

diff --git a/arch/riscv/Kconfig.vendor b/arch/riscv/Kconfig.vendor
index 3c1f92e406c3..74155c5b642f 100644
--- a/arch/riscv/Kconfig.vendor
+++ b/arch/riscv/Kconfig.vendor
@@ -14,6 +14,20 @@ config RISCV_ISA_VENDOR_EXT_ANDES
 	  requested by hardware probing to be ignored.
 
 	  If you don't know what to do here, say Y.
+
+config RISCV_ISA_XANDESPMU
+	tristate "xandespmu extension support"
+	depends on NONPORTABLE || m
+	default m
+	help
+	  The Andes cores implement the PMU overflow extension very
+	  similar to the standard Sscofpmf and Smcntrpmf extension.
+
+	  Select "m" for boot-time detection for portability.
+
+	  Select "y" for compile-time detection for optimization. Only available with NONPORTABLE.
+
+	  If you don't know what to do here, say m.
 endmenu
 
 menu "MIPS"
@@ -55,17 +69,22 @@ config RISCV_ISA_VENDOR_EXT_THEAD
 	  If you don't know what to do here, say Y.
 
 config RISCV_ISA_XTHEADVECTOR
-	bool "xtheadvector extension support"
+	tristate "xtheadvector extension support"
 	depends on RISCV_ISA_VENDOR_EXT_THEAD
 	depends on RISCV_ISA_V
 	depends on FPU
-	default y
+	depends on NONPORTABLE || m
+	default m
 	help
 	  Say N here if you want to disable all xtheadvector related procedures
 	  in the kernel. This will disable vector for any T-Head board that
 	  contains xtheadvector rather than the standard vector.
 
-	  If you don't know what to do here, say Y.
+	   Select "m" for boot-time detection for portability.
+
+	   Select "y" for compile-time detection for optimization. Only available with NONPORTABLE.
+
+	   If you don't know what to do here, say m.
 endmenu
 
 endmenu
diff --git a/arch/riscv/kernel/vendor_extensions/Makefile b/arch/riscv/kernel/vendor_extensions/Makefile
index bf116c82b6bd..e5ef5219a050 100644
--- a/arch/riscv/kernel/vendor_extensions/Makefile
+++ b/arch/riscv/kernel/vendor_extensions/Makefile
@@ -1,9 +1,17 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
-obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES)	+= andes.o
-obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_MIPS)  	+= mips.o
-obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_MIPS)  	+= mips_hwprobe.o
-obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE)	+= sifive.o
-obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE)	+= sifive_hwprobe.o
-obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD)	+= thead.o
-obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD)	+= thead_hwprobe.o
+ifneq ($(filter y m,$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES)),)
+obj-y	+= andes.o
+endif
+ifneq ($(filter y m,$(CONFIG_RISCV_ISA_VENDOR_EXT_MIPS)),)
+obj-y  	+= mips.o
+obj-y  	+= mips_hwprobe.o
+endif
+ifneq ($(filter y m,$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE)),)
+obj-y	+= sifive.o
+obj-y	+= sifive_hwprobe.o
+endif
+ifneq ($(filter y m,$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD)),)
+obj-y	+= thead.o
+obj-y	+= thead_hwprobe.o
+endif
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index 638321fc9800..dfbd02d28c3f 100644
--- a/drivers/perf/Kconfig
+++ b/drivers/perf/Kconfig
@@ -117,7 +117,7 @@ config STARFIVE_STARLINK_PMU
 
 config ANDES_CUSTOM_PMU
 	bool "Andes custom PMU support"
-	depends on ARCH_RENESAS && RISCV_ALTERNATIVE && RISCV_PMU_SBI
+	depends on ARCH_RENESAS && RISCV_ALTERNATIVE && RISCV_PMU_SBI && RISCV_ISA_XANDESPMU
 	default y
 	help
 	  The Andes cores implement the PMU overflow extension very

-- 
2.43.0