From: Biju Das <biju.das.jz@bp.renesas.com>

If the assert() fails due to timeout error, set the reset register bit
back to deasserted state. This change is needed especially for handling
assert error in suspend() callback that expect the device to be in
operational state in case of failure.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/clk/renesas/rzv2h-cpg.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
index 3f6299b9fec0..c0ee2dcc858c 100644
--- a/drivers/clk/renesas/rzv2h-cpg.c
+++ b/drivers/clk/renesas/rzv2h-cpg.c
@@ -1366,8 +1366,11 @@ static int __rzv2h_cpg_assert(struct reset_controller_dev *rcdev,
 
 	ret = readl_poll_timeout_atomic(priv->base + reg, value,
 					assert == !!(value & mask), 10, 200);
-	if (ret && !assert) {
+	if (ret) {
 		value = mask << 16;
+		if (assert)
+			value |= mask;
+
 		writel(value, priv->base + GET_RST_OFFSET(priv->resets[id].reset_index));
 	}
 
-- 
2.43.0

On Mo, 2025-12-08 at 10:13 +0000, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
> 
> If the assert() fails due to timeout error, set the reset register bit
> back to deasserted state. This change is needed especially for handling
> assert error in suspend() callback that expect the device to be in
> operational state in case of failure.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>  drivers/clk/renesas/rzv2h-cpg.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
> index 3f6299b9fec0..c0ee2dcc858c 100644
> --- a/drivers/clk/renesas/rzv2h-cpg.c
> +++ b/drivers/clk/renesas/rzv2h-cpg.c
> @@ -1366,8 +1366,11 @@ static int __rzv2h_cpg_assert(struct reset_controller_dev *rcdev,
>  
>  	ret = readl_poll_timeout_atomic(priv->base + reg, value,
>  					assert == !!(value & mask), 10, 200);
> -	if (ret && !assert) {
> +	if (ret) {
>  		value = mask << 16;
> +		if (assert)
> +			value |= mask;
> +
>  		writel(value, priv->base + GET_RST_OFFSET(priv->resets[id].reset_index));

This writel() could reuse

	unsigned int reg = GET_RST_OFFSET(priv->resets[id].reset_index);

>  	}

How does the hardware behave when __rzv2h_cpg_assert() is called on an
already asserted reset? Is it possible for the
readl_poll_timeout_atomic() timeout to trigger, or can this only ever
happen for asserted <-> deasserted transitions? Having a failed
reset_control_assert() deassert the reset if it was previously asserted
would be surprising.

regards
Philipp