VDPU346 is derived from VDPU381 but with a single core and limited
to 4K60 media. It is also limited to H264 L5.1 and omits AV1 and
AVS2 capabilities. It is used with RK3566 and RK3568.
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
.../media/platform/rockchip/rkvdec/rkvdec.c | 110 ++++++++++++++++++
1 file changed, 110 insertions(+)
diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c b/drivers/media/platform/rockchip/rkvdec/rkvdec.c
index a1c02ef3a97c..cf68454b2217 100644
--- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c
+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c
@@ -295,6 +295,62 @@ static const struct rkvdec_ctrls rkvdec_h264_ctrls = {
.num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs),
};
+static const struct rkvdec_ctrl_desc vdpu346_hevc_ctrl_descs[] = {
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS,
+ },
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_SPS,
+ .cfg.ops = &rkvdec_ctrl_ops,
+ },
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_PPS,
+ },
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX,
+ },
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_MODE,
+ .cfg.min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
+ .cfg.max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
+ .cfg.def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
+ },
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_START_CODE,
+ .cfg.min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
+ .cfg.def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
+ .cfg.max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
+ },
+ {
+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,
+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
+ .cfg.menu_skip_mask =
+ BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE),
+ .cfg.def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
+ },
+ {
+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1,
+ },
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_EXT_SPS_ST_RPS,
+ .cfg.ops = &rkvdec_ctrl_ops,
+ .cfg.dims = { 65 },
+ },
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_EXT_SPS_LT_RPS,
+ .cfg.ops = &rkvdec_ctrl_ops,
+ .cfg.dims = { 65 },
+ },
+};
+
+static const struct rkvdec_ctrls vdpu346_hevc_ctrls = {
+ .ctrls = vdpu346_hevc_ctrl_descs,
+ .num_ctrls = ARRAY_SIZE(vdpu346_hevc_ctrl_descs),
+};
+
static const struct rkvdec_ctrl_desc vdpu38x_hevc_ctrl_descs[] = {
{
.cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS,
@@ -449,6 +505,43 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
}
};
+static const struct rkvdec_coded_fmt_desc vdpu346_coded_fmts[] = {
+ {
+ .fourcc = V4L2_PIX_FMT_H264_SLICE,
+ .frmsize = {
+ .min_width = 64,
+ .max_width = 65520,
+ .step_width = 64,
+ .min_height = 64,
+ .max_height = 65520,
+ .step_height = 16,
+ },
+ .ctrls = &rkvdec_h264_ctrls,
+ .ops = &rkvdec_vdpu381_h264_fmt_ops,
+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts),
+ .decoded_fmts = rkvdec_h264_decoded_fmts,
+ .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF,
+ .capability = RKVDEC_CAPABILITY_H264,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_HEVC_SLICE,
+ .frmsize = {
+ .min_width = 64,
+ .max_width = 65472,
+ .step_width = 64,
+ .min_height = 64,
+ .max_height = 65472,
+ .step_height = 16,
+ },
+ .ctrls = &vdpu346_hevc_ctrls,
+ .ops = &rkvdec_vdpu381_hevc_fmt_ops,
+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts),
+ .decoded_fmts = rkvdec_hevc_decoded_fmts,
+ .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF,
+ .capability = RKVDEC_CAPABILITY_HEVC,
+ },
+};
+
static const struct rkvdec_coded_fmt_desc vdpu381_coded_fmts[] = {
{
.fourcc = V4L2_PIX_FMT_H264_SLICE,
@@ -1654,6 +1747,19 @@ static const struct rkvdec_variant rk3399_rkvdec_variant = {
RKVDEC_CAPABILITY_VP9,
};
+static const struct rkvdec_variant rk3568_vdpu346_variant = {
+ .coded_fmts = vdpu346_coded_fmts,
+ .num_coded_fmts = ARRAY_SIZE(vdpu346_coded_fmts),
+ .rcb_sizes = vdpu381_rcb_sizes,
+ .num_rcb_sizes = ARRAY_SIZE(vdpu381_rcb_sizes),
+ .irq_handler = vdpu381_irq_handler,
+ .colmv_size = rkvdec_colmv_size,
+ .flatten_matrices = transpose_and_flatten_matrices,
+ .named_regs = true,
+ .capabilities = RKVDEC_CAPABILITY_H264 |
+ RKVDEC_CAPABILITY_HEVC,
+};
+
static const struct rkvdec_variant rk3588_vdpu381_variant = {
.coded_fmts = vdpu381_coded_fmts,
.num_coded_fmts = ARRAY_SIZE(vdpu381_coded_fmts),
@@ -1693,6 +1799,10 @@ static const struct of_device_id of_rkvdec_match[] = {
.compatible = "rockchip,rk3399-vdec",
.data = &rk3399_rkvdec_variant,
},
+ {
+ .compatible = "rockchip,rk3568-vdec",
+ .data = &rk3568_vdpu346_variant,
+ },
{
.compatible = "rockchip,rk3588-vdec",
.data = &rk3588_vdpu381_variant,
--
2.34.1
Le samedi 06 décembre 2025 à 08:28 +0000, Christian Hewitt a écrit :
> VDPU346 is derived from VDPU381 but with a single core and limited
> to 4K60 media. It is also limited to H264 L5.1 and omits AV1 and
> AVS2 capabilities. It is used with RK3566 and RK3568.
>
> Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Reviewed-by: Nicolas Dufresne <nicolas.collabora@collabora.com>
Please resend whenever there is a dependency update, I believe some of the
variant stuff is being modified. Another note, I tried bigger resolution, but it
only yielded green images, so the 65K max does not actually work and will need
investigation.
Nicolas
> ---
> .../media/platform/rockchip/rkvdec/rkvdec.c | 110 ++++++++++++++++++
> 1 file changed, 110 insertions(+)
>
> diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c
> b/drivers/media/platform/rockchip/rkvdec/rkvdec.c
> index a1c02ef3a97c..cf68454b2217 100644
> --- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c
> +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c
> @@ -295,6 +295,62 @@ static const struct rkvdec_ctrls rkvdec_h264_ctrls = {
> .num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs),
> };
>
> +static const struct rkvdec_ctrl_desc vdpu346_hevc_ctrl_descs[] = {
> + {
> + .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS,
> + },
> + {
> + .cfg.id = V4L2_CID_STATELESS_HEVC_SPS,
> + .cfg.ops = &rkvdec_ctrl_ops,
> + },
> + {
> + .cfg.id = V4L2_CID_STATELESS_HEVC_PPS,
> + },
> + {
> + .cfg.id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX,
> + },
> + {
> + .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_MODE,
> + .cfg.min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
> + .cfg.max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
> + .cfg.def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
> + },
> + {
> + .cfg.id = V4L2_CID_STATELESS_HEVC_START_CODE,
> + .cfg.min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
> + .cfg.def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
> + .cfg.max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
> + },
> + {
> + .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,
> + .cfg.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
> + .cfg.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
> + .cfg.menu_skip_mask =
> + BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE),
> + .cfg.def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
> + },
> + {
> + .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
> + .cfg.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
> + .cfg.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1,
> + },
> + {
> + .cfg.id = V4L2_CID_STATELESS_HEVC_EXT_SPS_ST_RPS,
> + .cfg.ops = &rkvdec_ctrl_ops,
> + .cfg.dims = { 65 },
> + },
> + {
> + .cfg.id = V4L2_CID_STATELESS_HEVC_EXT_SPS_LT_RPS,
> + .cfg.ops = &rkvdec_ctrl_ops,
> + .cfg.dims = { 65 },
> + },
> +};
> +
> +static const struct rkvdec_ctrls vdpu346_hevc_ctrls = {
> + .ctrls = vdpu346_hevc_ctrl_descs,
> + .num_ctrls = ARRAY_SIZE(vdpu346_hevc_ctrl_descs),
> +};
> +
> static const struct rkvdec_ctrl_desc vdpu38x_hevc_ctrl_descs[] = {
> {
> .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS,
> @@ -449,6 +505,43 @@ static const struct rkvdec_coded_fmt_desc
> rkvdec_coded_fmts[] = {
> }
> };
>
> +static const struct rkvdec_coded_fmt_desc vdpu346_coded_fmts[] = {
> + {
> + .fourcc = V4L2_PIX_FMT_H264_SLICE,
> + .frmsize = {
> + .min_width = 64,
> + .max_width = 65520,
> + .step_width = 64,
> + .min_height = 64,
> + .max_height = 65520,
> + .step_height = 16,
> + },
> + .ctrls = &rkvdec_h264_ctrls,
> + .ops = &rkvdec_vdpu381_h264_fmt_ops,
> + .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts),
> + .decoded_fmts = rkvdec_h264_decoded_fmts,
> + .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF,
> + .capability = RKVDEC_CAPABILITY_H264,
> + },
> + {
> + .fourcc = V4L2_PIX_FMT_HEVC_SLICE,
> + .frmsize = {
> + .min_width = 64,
> + .max_width = 65472,
> + .step_width = 64,
> + .min_height = 64,
> + .max_height = 65472,
> + .step_height = 16,
> + },
> + .ctrls = &vdpu346_hevc_ctrls,
> + .ops = &rkvdec_vdpu381_hevc_fmt_ops,
> + .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts),
> + .decoded_fmts = rkvdec_hevc_decoded_fmts,
> + .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF,
> + .capability = RKVDEC_CAPABILITY_HEVC,
> + },
> +};
> +
> static const struct rkvdec_coded_fmt_desc vdpu381_coded_fmts[] = {
> {
> .fourcc = V4L2_PIX_FMT_H264_SLICE,
> @@ -1654,6 +1747,19 @@ static const struct rkvdec_variant
> rk3399_rkvdec_variant = {
> RKVDEC_CAPABILITY_VP9,
> };
>
> +static const struct rkvdec_variant rk3568_vdpu346_variant = {
> + .coded_fmts = vdpu346_coded_fmts,
> + .num_coded_fmts = ARRAY_SIZE(vdpu346_coded_fmts),
> + .rcb_sizes = vdpu381_rcb_sizes,
> + .num_rcb_sizes = ARRAY_SIZE(vdpu381_rcb_sizes),
> + .irq_handler = vdpu381_irq_handler,
> + .colmv_size = rkvdec_colmv_size,
> + .flatten_matrices = transpose_and_flatten_matrices,
> + .named_regs = true,
> + .capabilities = RKVDEC_CAPABILITY_H264 |
> + RKVDEC_CAPABILITY_HEVC,
> +};
> +
> static const struct rkvdec_variant rk3588_vdpu381_variant = {
> .coded_fmts = vdpu381_coded_fmts,
> .num_coded_fmts = ARRAY_SIZE(vdpu381_coded_fmts),
> @@ -1693,6 +1799,10 @@ static const struct of_device_id of_rkvdec_match[] = {
> .compatible = "rockchip,rk3399-vdec",
> .data = &rk3399_rkvdec_variant,
> },
> + {
> + .compatible = "rockchip,rk3568-vdec",
> + .data = &rk3568_vdpu346_variant,
> + },
> {
> .compatible = "rockchip,rk3588-vdec",
> .data = &rk3588_vdpu381_variant,
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