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[PATCH net-next v2] octeon_ep: reset firmware ready status

Vimlesh Kumar posted 1 patch 2 weeks ago 
.../marvell/octeon_ep/octep_cn9k_pf.c         | 22 +++++++++++++++++++
.../marvell/octeon_ep/octep_cnxk_pf.c         |  2 +-
.../marvell/octeon_ep/octep_regs_cn9k_pf.h    | 16 ++++++++++++++
.../marvell/octeon_ep/octep_regs_cnxk_pf.h    |  1 +
4 files changed, 40 insertions(+), 1 deletion(-)
[PATCH net-next v2] octeon_ep: reset firmware ready status
Posted by Vimlesh Kumar 2 weeks ago 
Add support to reset firmware ready status
when the driver is removed(either in unload
or unbind)

Signed-off-by: Sathesh Edara <sedara@marvell.com>
Signed-off-by: Shinas Rasheed <srasheed@marvell.com>
Signed-off-by: Vimlesh Kumar <vimleshk@marvell.com>
---
V2: Use recommended bit manipulation macros.

V1: https://lore.kernel.org/all/20251120112345.649021-2-vimleshk@marvell.com/

 .../marvell/octeon_ep/octep_cn9k_pf.c         | 22 +++++++++++++++++++
 .../marvell/octeon_ep/octep_cnxk_pf.c         |  2 +-
 .../marvell/octeon_ep/octep_regs_cn9k_pf.h    | 16 ++++++++++++++
 .../marvell/octeon_ep/octep_regs_cnxk_pf.h    |  1 +
 4 files changed, 40 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c b/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c
index b5805969404f..6f926e82c17c 100644
--- a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c
+++ b/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c
@@ -637,6 +637,17 @@ static int octep_soft_reset_cn93_pf(struct octep_device *oct)
 
 	octep_write_csr64(oct, CN93_SDP_WIN_WR_MASK_REG, 0xFF);
 
+	/* Firmware status CSR is supposed to be cleared by
+	 * core domain reset, but due to a hw bug, it is not.
+	 * Set it to RUNNING right before reset so that it is not
+	 * left in READY (1) state after a reset.  This is required
+	 * in addition to the early setting to handle the case where
+	 * the OcteonTX is unexpectedly reset, reboots, and then
+	 * the module is removed.
+	 */
+	OCTEP_PCI_WIN_WRITE(oct, CN9K_PEMX_PFX_CSX_PFCFGX(0, 0, CN9K_PCIEEP_VSECST_CTL),
+			    FW_STATUS_DOWNING);
+
 	/* Set core domain reset bit */
 	OCTEP_PCI_WIN_WRITE(oct, CN93_RST_CORE_DOMAIN_W1S, 1);
 	/* Wait for 100ms as Octeon resets. */
@@ -894,4 +905,15 @@ void octep_device_setup_cn93_pf(struct octep_device *oct)
 
 	octep_init_config_cn93_pf(oct);
 	octep_configure_ring_mapping_cn93_pf(oct);
+
+	if (oct->chip_id == OCTEP_PCI_DEVICE_ID_CN98_PF)
+		return;
+
+	/* Firmware status CSR is supposed to be cleared by
+	 * core domain reset, but due to IPBUPEM-38842, it is not.
+	 * Set it to RUNNING early in boot, so that unexpected resets
+	 * leave it in a state that is not READY (1).
+	 */
+	OCTEP_PCI_WIN_WRITE(oct, CN9K_PEMX_PFX_CSX_PFCFGX(0, 0, CN9K_PCIEEP_VSECST_CTL),
+			    FW_STATUS_RUNNING);
 }
diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c b/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c
index 5de0b5ecbc5f..e07264b3dbf8 100644
--- a/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c
+++ b/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c
@@ -660,7 +660,7 @@ static int octep_soft_reset_cnxk_pf(struct octep_device *oct)
 	 * the module is removed.
 	 */
 	OCTEP_PCI_WIN_WRITE(oct, CNXK_PEMX_PFX_CSX_PFCFGX(0, 0, CNXK_PCIEEP_VSECST_CTL),
-			    FW_STATUS_RUNNING);
+			    FW_STATUS_DOWNING);
 
 	/* Set chip domain reset bit */
 	OCTEP_PCI_WIN_WRITE(oct, CNXK_RST_CHIP_DOMAIN_W1S, 1);
diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h b/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
index ca473502d7a0..284959d97ad1 100644
--- a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
+++ b/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
@@ -383,6 +383,22 @@
 /* bit 1 for firmware heartbeat interrupt */
 #define CN93_SDP_EPF_OEI_RINT_DATA_BIT_HBEAT	BIT_ULL(1)
 
+#define FW_STATUS_DOWNING      0ULL
+#define FW_STATUS_RUNNING      2ULL
+
+#define CN9K_PEM_GENMASK BIT_ULL(36)
+#define CN9K_PF_GENMASK GENMASK_ULL(21, 18)
+#define PFX_CSX_PFCFGX_SHADOW_BIT BIT_ULL(16)
+#define CN9K_PEMX_PFX_CSX_PFCFGX(pem, pf, offset)   ((0x8e0000008000 | (uint64_t)\
+						      FIELD_PREP(CN9K_PEM_GENMASK, pem)\
+						      | FIELD_PREP(CN9K_PF_GENMASK, pf)\
+						      | (PFX_CSX_PFCFGX_SHADOW_BIT & (offset))\
+						      | (rounddown((offset), 8)))\
+						      + ((offset) & BIT_ULL(2)))
+
+/* Register defines for use with CN9K_PEMX_PFX_CSX_PFCFGX */
+#define CN9K_PCIEEP_VSECST_CTL  0x4D0
+
 #define CN93_PEM_BAR4_INDEX            7
 #define CN93_PEM_BAR4_INDEX_SIZE       0x400000ULL
 #define CN93_PEM_BAR4_INDEX_OFFSET     (CN93_PEM_BAR4_INDEX * CN93_PEM_BAR4_INDEX_SIZE)
diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h b/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h
index e637d7c8224d..a6b6c9f356de 100644
--- a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h
+++ b/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h
@@ -396,6 +396,7 @@
 #define CNXK_SDP_EPF_OEI_RINT_DATA_BIT_MBOX	BIT_ULL(0)
 /* bit 1 for firmware heartbeat interrupt */
 #define CNXK_SDP_EPF_OEI_RINT_DATA_BIT_HBEAT	BIT_ULL(1)
+#define FW_STATUS_DOWNING      0ULL
 #define FW_STATUS_RUNNING      2ULL
 #define CNXK_PEMX_PFX_CSX_PFCFGX(pem, pf, offset)      ({ typeof(offset) _off = (offset); \
 							  ((0x8e0000008000 | \
-- 
2.47.0
Re: [PATCH net-next v2] octeon_ep: reset firmware ready status
Posted by Simon Horman 1 week, 5 days ago 
On Fri, Dec 05, 2025 at 09:10:44AM +0000, Vimlesh Kumar wrote:
> Add support to reset firmware ready status
> when the driver is removed(either in unload
> or unbind)
> 
> Signed-off-by: Sathesh Edara <sedara@marvell.com>
> Signed-off-by: Shinas Rasheed <srasheed@marvell.com>
> Signed-off-by: Vimlesh Kumar <vimleshk@marvell.com>
> ---
> V2: Use recommended bit manipulation macros.

...

> diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h b/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
> index ca473502d7a0..284959d97ad1 100644
> --- a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
> +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
> @@ -383,6 +383,22 @@
>  /* bit 1 for firmware heartbeat interrupt */
>  #define CN93_SDP_EPF_OEI_RINT_DATA_BIT_HBEAT	BIT_ULL(1)
>  
> +#define FW_STATUS_DOWNING      0ULL
> +#define FW_STATUS_RUNNING      2ULL
> +
> +#define CN9K_PEM_GENMASK BIT_ULL(36)
> +#define CN9K_PF_GENMASK GENMASK_ULL(21, 18)
> +#define PFX_CSX_PFCFGX_SHADOW_BIT BIT_ULL(16)
> +#define CN9K_PEMX_PFX_CSX_PFCFGX(pem, pf, offset)   ((0x8e0000008000 | (uint64_t)\
> +						      FIELD_PREP(CN9K_PEM_GENMASK, pem)\
> +						      | FIELD_PREP(CN9K_PF_GENMASK, pf)\
> +						      | (PFX_CSX_PFCFGX_SHADOW_BIT & (offset))\
> +						      | (rounddown((offset), 8)))\
> +						      + ((offset) & BIT_ULL(2)))

Hi Vimlesh,

Please use a #defines so that 0x8e0000008000 and for BIT_ULL(2) have names.

And please reformat so this is less than 80 columns wide.
I'd do something like this:

define CN9K_PEMX_PFX_CSX_PFCFGX(pem, pf, offset) \
	... \
	...

> +
> +/* Register defines for use with CN9K_PEMX_PFX_CSX_PFCFGX */
> +#define CN9K_PCIEEP_VSECST_CTL  0x4D0
> +
>  #define CN93_PEM_BAR4_INDEX            7
>  #define CN93_PEM_BAR4_INDEX_SIZE       0x400000ULL
>  #define CN93_PEM_BAR4_INDEX_OFFSET     (CN93_PEM_BAR4_INDEX * CN93_PEM_BAR4_INDEX_SIZE)

## Form letter - net-next-closed

The merge window for v6.19 has begun and therefore net-next has closed
for new drivers, features, code refactoring and optimizations. We are
currently accepting bug fixes only.

Please repost when net-next reopens.

Due to a combination of the merge-window, travel commitments of the
maintainers, and the holiday season, net-next will re-open after
2nd January.

RFC patches sent for review only are welcome at any time.

See: https://www.kernel.org/doc/html/next/process/maintainer-netdev.html#development-cycle

-- 
pw-bot: changes-requested
Re: [PATCH net-next v2] octeon_ep: reset firmware ready status
Posted by kernel test robot 1 week, 6 days ago 
Hi Vimlesh,

kernel test robot noticed the following build errors:

[auto build test ERROR on net-next/main]

url:    https://github.com/intel-lab-lkp/linux/commits/Vimlesh-Kumar/octeon_ep-reset-firmware-ready-status/20251205-172517
base:   net-next/main
patch link:    https://lore.kernel.org/r/20251205091045.1655157-1-vimleshk%40marvell.com
patch subject: [PATCH net-next v2] octeon_ep: reset firmware ready status
config: loongarch-randconfig-002-20251206 (https://download.01.org/0day-ci/archive/20251206/202512062026.fpQ6NHC3-lkp@intel.com/config)
compiler: loongarch64-linux-gcc (GCC) 12.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251206/202512062026.fpQ6NHC3-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202512062026.fpQ6NHC3-lkp@intel.com/

All errors (new ones prefixed by >>):

   In file included from drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c:14:
   drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c: In function 'octep_soft_reset_cn93_pf':
>> drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h:393:55: error: implicit declaration of function 'FIELD_PREP' [-Werror=implicit-function-declaration]
     393 |                                                       FIELD_PREP(CN9K_PEM_GENMASK, pem)\
         |                                                       ^~~~~~~~~~
   drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c:648:34: note: in expansion of macro 'CN9K_PEMX_PFX_CSX_PFCFGX'
     648 |         OCTEP_PCI_WIN_WRITE(oct, CN9K_PEMX_PFX_CSX_PFCFGX(0, 0, CN9K_PCIEEP_VSECST_CTL),
         |                                  ^~~~~~~~~~~~~~~~~~~~~~~~
   cc1: some warnings being treated as errors


vim +/FIELD_PREP +393 drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h

   388	
   389	#define CN9K_PEM_GENMASK BIT_ULL(36)
   390	#define CN9K_PF_GENMASK GENMASK_ULL(21, 18)
   391	#define PFX_CSX_PFCFGX_SHADOW_BIT BIT_ULL(16)
   392	#define CN9K_PEMX_PFX_CSX_PFCFGX(pem, pf, offset)   ((0x8e0000008000 | (uint64_t)\
 > 393							      FIELD_PREP(CN9K_PEM_GENMASK, pem)\
   394							      | FIELD_PREP(CN9K_PF_GENMASK, pf)\
   395							      | (PFX_CSX_PFCFGX_SHADOW_BIT & (offset))\
   396							      | (rounddown((offset), 8)))\
   397							      + ((offset) & BIT_ULL(2)))
   398	

-- 
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https://github.com/intel/lkp-tests/wiki

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