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[PATCH WIP v2 3/8] media: qcom: camss: Prepare CSID for C-PHY support

David Heidelberg via B4 Relay posted 8 patches 2 months ago
There is a newer version of this series
[PATCH WIP v2 3/8] media: qcom: camss: Prepare CSID for C-PHY support
Posted by David Heidelberg via B4 Relay 2 months ago 
From: David Heidelberg <david@ixit.cz>

Inherit C-PHY information from CSIPHY, so we can configure CSID
properly.

CSI2_RX_CFG0_PHY_TYPE_SEL must be set to 1, when C-PHY mode is used.

Signed-off-by: David Heidelberg <david@ixit.cz>
---
 drivers/media/platform/qcom/camss/camss-csid-gen2.c | 1 +
 drivers/media/platform/qcom/camss/camss-csid.c      | 1 +
 drivers/media/platform/qcom/camss/camss-csid.h      | 1 +
 3 files changed, 3 insertions(+)

diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen2.c b/drivers/media/platform/qcom/camss/camss-csid-gen2.c
index 2a1746dcc1c5b..033036ae28a4f 100644
--- a/drivers/media/platform/qcom/camss/camss-csid-gen2.c
+++ b/drivers/media/platform/qcom/camss/camss-csid-gen2.c
@@ -183,6 +183,7 @@ static void __csid_configure_rx(struct csid_device *csid,
 	val = (lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES;
 	val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL;
 	val |= phy->csiphy_id << CSI2_RX_CFG0_PHY_NUM_SEL;
+	val |= csid->phy.cphy << CSI2_RX_CFG0_PHY_TYPE_SEL;
 	writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG0);
 
 	val = 1 << CSI2_RX_CFG1_PACKET_ECC_CORRECTION_EN;
diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media/platform/qcom/camss/camss-csid.c
index 5284b5857368c..d9026fd829d61 100644
--- a/drivers/media/platform/qcom/camss/camss-csid.c
+++ b/drivers/media/platform/qcom/camss/camss-csid.c
@@ -1287,6 +1287,7 @@ static int csid_link_setup(struct media_entity *entity,
 		csid->phy.csiphy_id = csiphy->id;
 
 		lane_cfg = &csiphy->cfg.csi2->lane_cfg;
+		csid->phy.cphy = (lane_cfg->phy_cfg == V4L2_MBUS_CSI2_CPHY);
 		csid->phy.lane_cnt = lane_cfg->num_data;
 		csid->phy.lane_assign = csid_get_lane_assign(lane_cfg);
 	}
diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media/platform/qcom/camss/camss-csid.h
index aedc96ed84b2f..a82db31bd2335 100644
--- a/drivers/media/platform/qcom/camss/camss-csid.h
+++ b/drivers/media/platform/qcom/camss/camss-csid.h
@@ -70,6 +70,7 @@ struct csid_phy_config {
 	u32 lane_assign;
 	u32 en_vc;
 	u8 need_vc_update;
+	bool cphy;
 };
 
 struct csid_device;

-- 
2.51.0
Re: [PATCH WIP v2 3/8] media: qcom: camss: Prepare CSID for C-PHY support
Posted by Konrad Dybcio 2 months ago 
On 12/4/25 5:32 PM, David Heidelberg via B4 Relay wrote:
> From: David Heidelberg <david@ixit.cz>
> 
> Inherit C-PHY information from CSIPHY, so we can configure CSID
> properly.
> 
> CSI2_RX_CFG0_PHY_TYPE_SEL must be set to 1, when C-PHY mode is used.
> 
> Signed-off-by: David Heidelberg <david@ixit.cz>
> ---
>  drivers/media/platform/qcom/camss/camss-csid-gen2.c | 1 +
>  drivers/media/platform/qcom/camss/camss-csid.c      | 1 +
>  drivers/media/platform/qcom/camss/camss-csid.h      | 1 +
>  3 files changed, 3 insertions(+)
> 
> diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen2.c b/drivers/media/platform/qcom/camss/camss-csid-gen2.c
> index 2a1746dcc1c5b..033036ae28a4f 100644
> --- a/drivers/media/platform/qcom/camss/camss-csid-gen2.c
> +++ b/drivers/media/platform/qcom/camss/camss-csid-gen2.c
> @@ -183,6 +183,7 @@ static void __csid_configure_rx(struct csid_device *csid,
>  	val = (lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES;
>  	val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL;
>  	val |= phy->csiphy_id << CSI2_RX_CFG0_PHY_NUM_SEL;
> +	val |= csid->phy.cphy << CSI2_RX_CFG0_PHY_TYPE_SEL;

This field is 1-wide, this would be neater:

if (csid->phy.cphy)
	val |= BIT(CSI2_RX_CFG0_PHY_TYPE_SEL);

Konrad
Re: [PATCH WIP v2 3/8] media: qcom: camss: Prepare CSID for C-PHY support
Posted by David Heidelberg 1 month, 4 weeks ago 
On 05/12/2025 10:43, Konrad Dybcio wrote:
> On 12/4/25 5:32 PM, David Heidelberg via B4 Relay wrote:
>> From: David Heidelberg <david@ixit.cz>
>>
>> Inherit C-PHY information from CSIPHY, so we can configure CSID
>> properly.
>>
>> CSI2_RX_CFG0_PHY_TYPE_SEL must be set to 1, when C-PHY mode is used.
>>
>> Signed-off-by: David Heidelberg <david@ixit.cz>
>> ---
>>   drivers/media/platform/qcom/camss/camss-csid-gen2.c | 1 +
>>   drivers/media/platform/qcom/camss/camss-csid.c      | 1 +
>>   drivers/media/platform/qcom/camss/camss-csid.h      | 1 +
>>   3 files changed, 3 insertions(+)
>>
>> diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen2.c b/drivers/media/platform/qcom/camss/camss-csid-gen2.c
>> index 2a1746dcc1c5b..033036ae28a4f 100644
>> --- a/drivers/media/platform/qcom/camss/camss-csid-gen2.c
>> +++ b/drivers/media/platform/qcom/camss/camss-csid-gen2.c
>> @@ -183,6 +183,7 @@ static void __csid_configure_rx(struct csid_device *csid,
>>   	val = (lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES;
>>   	val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL;
>>   	val |= phy->csiphy_id << CSI2_RX_CFG0_PHY_NUM_SEL;
>> +	val |= csid->phy.cphy << CSI2_RX_CFG0_PHY_TYPE_SEL;
> 
> This field is 1-wide, this would be neater:
> 
> if (csid->phy.cphy)
> 	val |= BIT(CSI2_RX_CFG0_PHY_TYPE_SEL);

Hello Konrad,

while your change make sense as we work with 1-bit.
On other hand, due to TYPE_SEL naming, it's not very explicit why we set 
this bit when cphy is on.

Maybe I could propose renaming CSI2_RX_CFG0_PHY_TYPE_SEL to 
CSI2_RX_CFG0_PHY_TYPE_SEL_CPHY, then setting 1 to it would make sense.

Most clean solution to me would be something like

#define TYPE_SEL_DPHY	0
#define TYPE_SEL_CPHY	1

val |= (csid->phy.cphy ? TYPE_SEL_CPHY : TYPE_SEL_DPHY) << 
CSI2_RX_CFG0_PHY_TYPE_SEL

Do I overthinking this? What do you think?

David

> 
> Konrad

-- 
David Heidelberg
Re: [PATCH WIP v2 3/8] media: qcom: camss: Prepare CSID for C-PHY support
Posted by Konrad Dybcio 1 month, 3 weeks ago 
On 12/11/25 4:20 PM, David Heidelberg wrote:
> On 05/12/2025 10:43, Konrad Dybcio wrote:
>> On 12/4/25 5:32 PM, David Heidelberg via B4 Relay wrote:
>>> From: David Heidelberg <david@ixit.cz>
>>>
>>> Inherit C-PHY information from CSIPHY, so we can configure CSID
>>> properly.
>>>
>>> CSI2_RX_CFG0_PHY_TYPE_SEL must be set to 1, when C-PHY mode is used.
>>>
>>> Signed-off-by: David Heidelberg <david@ixit.cz>
>>> ---
>>>   drivers/media/platform/qcom/camss/camss-csid-gen2.c | 1 +
>>>   drivers/media/platform/qcom/camss/camss-csid.c      | 1 +
>>>   drivers/media/platform/qcom/camss/camss-csid.h      | 1 +
>>>   3 files changed, 3 insertions(+)
>>>
>>> diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen2.c b/drivers/media/platform/qcom/camss/camss-csid-gen2.c
>>> index 2a1746dcc1c5b..033036ae28a4f 100644
>>> --- a/drivers/media/platform/qcom/camss/camss-csid-gen2.c
>>> +++ b/drivers/media/platform/qcom/camss/camss-csid-gen2.c
>>> @@ -183,6 +183,7 @@ static void __csid_configure_rx(struct csid_device *csid,
>>>       val = (lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES;
>>>       val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL;
>>>       val |= phy->csiphy_id << CSI2_RX_CFG0_PHY_NUM_SEL;
>>> +    val |= csid->phy.cphy << CSI2_RX_CFG0_PHY_TYPE_SEL;
>>
>> This field is 1-wide, this would be neater:
>>
>> if (csid->phy.cphy)
>>     val |= BIT(CSI2_RX_CFG0_PHY_TYPE_SEL);
> 
> Hello Konrad,
> 
> while your change make sense as we work with 1-bit.
> On other hand, due to TYPE_SEL naming, it's not very explicit why we set this bit when cphy is on.

This is the actual name of the register field

> 
> Maybe I could propose renaming CSI2_RX_CFG0_PHY_TYPE_SEL to CSI2_RX_CFG0_PHY_TYPE_SEL_CPHY, then setting 1 to it would make sense.
> 
> Most clean solution to me would be something like
> 
> #define TYPE_SEL_DPHY    0
> #define TYPE_SEL_CPHY    1
> 
> val |= (csid->phy.cphy ? TYPE_SEL_CPHY : TYPE_SEL_DPHY) << CSI2_RX_CFG0_PHY_TYPE_SEL
> 
> Do I overthinking this? What do you think?

Perhaps just:

/* Set the PHY_TYPE_SEL bit to enable C-PHY mode */
if (csid->phy.cphy)
	val |= BIT(CSI2_RX_CFG0_PHY_TYPE_SEL);

?

Konrad
Re: [PATCH WIP v2 3/8] media: qcom: camss: Prepare CSID for C-PHY support
Posted by David Heidelberg 1 month, 3 weeks ago 
On 17/12/2025 14:31, Konrad Dybcio wrote:

[...]>
> Perhaps just:
> 
> /* Set the PHY_TYPE_SEL bit to enable C-PHY mode */
> if (csid->phy.cphy)
> 	val |= BIT(CSI2_RX_CFG0_PHY_TYPE_SEL);
> 
> ?

Yeah, the comment helps here.

Thanks
David

> 
> Konrad

-- 
David Heidelberg

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