VESA DisplayID fixed DSC BPP value support

[PATCH v7 3/7] drm/edid: MSO should only be used for non-eDP displays

Posted by Yaroslav Bolyukin 2 months, 1 week ago

As per DisplayID v2.1a spec:
If Offset 06h[2:0] is programmed to 001b (External DisplayPort), this
field shall be cleared to 00b (Not supported).

Link: https://lore.kernel.org/lkml/3abc1087618c822e5676e67a3ec2e64e506dc5ec@intel.com/
Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>
---
 drivers/gpu/drm/drm_displayid_internal.h |  4 +++
 drivers/gpu/drm/drm_edid.c               | 36 +++++++++++++++---------
 2 files changed, 27 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/drm_displayid_internal.h b/drivers/gpu/drm/drm_displayid_internal.h
index 5b1b32f73516..72f107ae832f 100644
--- a/drivers/gpu/drm/drm_displayid_internal.h
+++ b/drivers/gpu/drm/drm_displayid_internal.h
@@ -142,9 +142,13 @@ struct displayid_formula_timing_block {
 	struct displayid_formula_timings_9 timings[];
 } __packed;
 
+#define DISPLAYID_VESA_DP_TYPE		GENMASK(2, 0)
 #define DISPLAYID_VESA_MSO_OVERLAP	GENMASK(3, 0)
 #define DISPLAYID_VESA_MSO_MODE		GENMASK(6, 5)
 
+#define DISPLAYID_VESA_DP_TYPE_EDP	0
+#define DISPLAYID_VESA_DP_TYPE_DP	1
+
 struct displayid_vesa_vendor_specific_block {
 	struct displayid_block base;
 	u8 oui[3];
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index a0a6ccf12475..380a9dda275f 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -6533,6 +6533,7 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector,
 	struct displayid_vesa_vendor_specific_block *vesa =
 		(struct displayid_vesa_vendor_specific_block *)block;
 	struct drm_display_info *info = &connector->display_info;
+	int dp_type;
 
 	if (block->num_bytes < 3) {
 		drm_dbg_kms(connector->dev,
@@ -6551,20 +6552,29 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector,
 		return;
 	}
 
-	switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
-	default:
-		drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n",
+	dp_type = FIELD_GET(DISPLAYID_VESA_DP_TYPE, vesa->data_structure_type);
+	if (dp_type > 1) {
+		drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved dp type value\n",
 			    connector->base.id, connector->name);
-		fallthrough;
-	case 0:
-		info->mso_stream_count = 0;
-		break;
-	case 1:
-		info->mso_stream_count = 2; /* 2 or 4 links */
-		break;
-	case 2:
-		info->mso_stream_count = 4; /* 4 links */
-		break;
+	}
+
+	/* MSO is only supported for eDP */
+	if (dp_type == DISPLAYID_VESA_DP_TYPE_EDP) {
+		switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
+		default:
+			drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n",
+				    connector->base.id, connector->name);
+			fallthrough;
+		case 0:
+			info->mso_stream_count = 0;
+			break;
+		case 1:
+			info->mso_stream_count = 2; /* 2 or 4 links */
+			break;
+		case 2:
+			info->mso_stream_count = 4; /* 4 links */
+			break;
+		}
 	}
 
 	if (info->mso_stream_count) {
-- 
2.51.2

Re: [PATCH v7 3/7] drm/edid: MSO should only be used for non-eDP displays

Posted by Jani Nikula 2 months, 1 week ago

On Tue, 02 Dec 2025, Yaroslav Bolyukin <iam@lach.pw> wrote:
> As per DisplayID v2.1a spec:
> If Offset 06h[2:0] is programmed to 001b (External DisplayPort), this
> field shall be cleared to 00b (Not supported).
>
> Link: https://lore.kernel.org/lkml/3abc1087618c822e5676e67a3ec2e64e506dc5ec@intel.com/

The Link: tag is unnecessary. No need to resend for this.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>
> ---
>  drivers/gpu/drm/drm_displayid_internal.h |  4 +++
>  drivers/gpu/drm/drm_edid.c               | 36 +++++++++++++++---------
>  2 files changed, 27 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_displayid_internal.h b/drivers/gpu/drm/drm_displayid_internal.h
> index 5b1b32f73516..72f107ae832f 100644
> --- a/drivers/gpu/drm/drm_displayid_internal.h
> +++ b/drivers/gpu/drm/drm_displayid_internal.h
> @@ -142,9 +142,13 @@ struct displayid_formula_timing_block {
>  	struct displayid_formula_timings_9 timings[];
>  } __packed;
>  
> +#define DISPLAYID_VESA_DP_TYPE		GENMASK(2, 0)
>  #define DISPLAYID_VESA_MSO_OVERLAP	GENMASK(3, 0)
>  #define DISPLAYID_VESA_MSO_MODE		GENMASK(6, 5)
>  
> +#define DISPLAYID_VESA_DP_TYPE_EDP	0
> +#define DISPLAYID_VESA_DP_TYPE_DP	1
> +
>  struct displayid_vesa_vendor_specific_block {
>  	struct displayid_block base;
>  	u8 oui[3];
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index a0a6ccf12475..380a9dda275f 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -6533,6 +6533,7 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector,
>  	struct displayid_vesa_vendor_specific_block *vesa =
>  		(struct displayid_vesa_vendor_specific_block *)block;
>  	struct drm_display_info *info = &connector->display_info;
> +	int dp_type;
>  
>  	if (block->num_bytes < 3) {
>  		drm_dbg_kms(connector->dev,
> @@ -6551,20 +6552,29 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector,
>  		return;
>  	}
>  
> -	switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
> -	default:
> -		drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n",
> +	dp_type = FIELD_GET(DISPLAYID_VESA_DP_TYPE, vesa->data_structure_type);
> +	if (dp_type > 1) {
> +		drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved dp type value\n",
>  			    connector->base.id, connector->name);
> -		fallthrough;
> -	case 0:
> -		info->mso_stream_count = 0;
> -		break;
> -	case 1:
> -		info->mso_stream_count = 2; /* 2 or 4 links */
> -		break;
> -	case 2:
> -		info->mso_stream_count = 4; /* 4 links */
> -		break;
> +	}
> +
> +	/* MSO is only supported for eDP */
> +	if (dp_type == DISPLAYID_VESA_DP_TYPE_EDP) {
> +		switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
> +		default:
> +			drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n",
> +				    connector->base.id, connector->name);
> +			fallthrough;
> +		case 0:
> +			info->mso_stream_count = 0;
> +			break;
> +		case 1:
> +			info->mso_stream_count = 2; /* 2 or 4 links */
> +			break;
> +		case 2:
> +			info->mso_stream_count = 4; /* 4 links */
> +			break;
> +		}
>  	}
>  
>  	if (info->mso_stream_count) {

-- 
Jani Nikula, Intel

[PATCH v7 1/7] drm/edid: rename VESA block parsing functions to more generic name
[PATCH v7 2/7] drm/edid: prepare for VESA vendor-specific data block extension
[PATCH v7 3/7] drm/edid: MSO should only be used for non-eDP displays
[PATCH v7 4/7] drm/edid: parse DSC DPP passthru support flag for mode VII timings
[PATCH v7 5/7] drm/edid: for consistency, use mask everywhere for block rev parsing
[PATCH v7 6/7] drm/edid: parse DRM VESA dsc bpp target
[PATCH v7 7/7] drm/amd: use fixed dsc bits-per-pixel from edid