The mask setting is 5 bits wide for the ad9434
(ref. data sheet register 0x18 FLEX_VREF). Apparently the settings
from ad9265 were copied by mistake when support for the device was added
to the driver.
Fixes: 4606d0f4b05f ("iio: adc: ad9467: add support for AD9434 high-speed ADC")
Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
---
drivers/iio/adc/ad9467.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iio/adc/ad9467.c b/drivers/iio/adc/ad9467.c
index f7a9f46ea0dc405e25f312197df4b2131871b4bc..2d8f8da3671dac61994a1864a82cdbef7f54c1af 100644
--- a/drivers/iio/adc/ad9467.c
+++ b/drivers/iio/adc/ad9467.c
@@ -95,7 +95,7 @@
#define CHIPID_AD9434 0x6A
#define AD9434_DEF_OUTPUT_MODE 0x00
-#define AD9434_REG_VREF_MASK 0xC0
+#define AD9434_REG_VREF_MASK GENMASK(4, 0)
/*
* Analog Devices AD9467 16-Bit, 200/250 MSPS ADC
--
2.47.3
On Tue, Dec 02, 2025 at 12:53:08PM +0000, Tomas Melin wrote: > The mask setting is 5 bits wide for the ad9434 > (ref. data sheet register 0x18 FLEX_VREF). Apparently the settings > from ad9265 were copied by mistake when support for the device was added > to the driver. Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> -- With Best Regards, Andy Shevchenko
On Tue, 2025-12-02 at 12:53 +0000, Tomas Melin wrote:
> The mask setting is 5 bits wide for the ad9434
> (ref. data sheet register 0x18 FLEX_VREF). Apparently the settings
> from ad9265 were copied by mistake when support for the device was added
> to the driver.
>
> Fixes: 4606d0f4b05f ("iio: adc: ad9467: add support for AD9434 high-speed ADC")
> Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
> ---
> drivers/iio/adc/ad9467.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/iio/adc/ad9467.c b/drivers/iio/adc/ad9467.c
> index f7a9f46ea0dc405e25f312197df4b2131871b4bc..2d8f8da3671dac61994a1864a82cdbef7f54c1af 100644
> --- a/drivers/iio/adc/ad9467.c
> +++ b/drivers/iio/adc/ad9467.c
> @@ -95,7 +95,7 @@
>
> #define CHIPID_AD9434 0x6A
> #define AD9434_DEF_OUTPUT_MODE 0x00
> -#define AD9434_REG_VREF_MASK 0xC0
> +#define AD9434_REG_VREF_MASK GENMASK(4, 0)
In theory we should fix it using the same mask style as the other variants and then moving all to
GENMASK(). However, I do not feel strong about it and I can send a follow up. Hence:
Reviewed-by: Nuno Sá <nuno.sa@analog.com>
>
> /*
> * Analog Devices AD9467 16-Bit, 200/250 MSPS ADC
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