From: Biju Das <biju.das.jz@bp.renesas.com>
The RZ/T2H RSCI has 16-stage FIFO. Like other SoCs, set the default
rx_trigger as the fifosize.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v4->v5:
* Updated commit description.
v4:
* New patch.
---
drivers/tty/serial/sh-sci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 53edbf1d8963..28d665a9861a 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -3330,7 +3330,7 @@ static int sci_init_single(struct platform_device *dev,
sci_port->rx_trigger = 8;
break;
case SCI_PORT_RSCI:
- sci_port->rx_trigger = 15;
+ sci_port->rx_trigger = 16;
break;
default:
sci_port->rx_trigger = 1;
--
2.43.0