From: Biju Das <biju.das.jz@bp.renesas.com>
Add documentation for the serial communication interface (RSCI) found on
the Renesas RZ/G3E (R9A09G047) SoC. The RSCI IP on this SoC is identical
to that on the RZ/T2H (R9A09G077) SoC, but it has a 32-stage FIFO compared
to 16 on RZ/T2H. It supports both FIFO and non-FIFO mode operation. RZ/G3E
has 6 clocks(5 module clocks + 1 external clock) compared to 3 clocks
(2 module clocks + 1 external clock) on RZ/T2H, and it has multiple resets.
It has 6 interrupts compared to 4 on RZ/T2H.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v4->v5:
* Updated commit description related to IRQ difference
* Added aed and bfd irqs for RZ/G3E.
* Moved reset: false to RZ/T2H SoC and dropped the else part for RZ/G3E.
* Updated conditional schema with interrupts and interrupts-names.
* Dropped the tag as there are new changes.
v3->v4:
* Dropped separate compatible for non-FIFO mode and instead using single
compatible "renesas,r9a09g047-rsci" as non-FIFO mode can be achieved
by software configuration.
* Renamed clock-names bus->pclk
* Rearranged clock-names tclk{4, 16, 64}
* Retained the tag as the changes are trivial.
v2->v3:
* Dropped 1st and 3rd items from clk-names and added minItems for the
range.
* Added minItems for clk and clk-names for RZ/T2H as the range is 2-3
* Added maxItems for clk and clk-names for RZ/G3E as the range is 5-6
* Retained the tag as it is trivial change.
v1->v2:
* Updated commit message
* Added resets:false for non RZ/G3E SoCs.
---
.../bindings/serial/renesas,rsci.yaml | 99 ++++++++++++++++---
1 file changed, 88 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
index 6b1f827a335b..1f8cee8171de 100644
--- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
@@ -10,46 +10,72 @@ maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
-allOf:
- - $ref: serial.yaml#
-
properties:
compatible:
oneOf:
- - items:
- - const: renesas,r9a09g087-rsci # RZ/N2H
- - const: renesas,r9a09g077-rsci # RZ/T2H
+ - enum:
+ - renesas,r9a09g047-rsci # RZ/G3E
+ - renesas,r9a09g077-rsci # RZ/T2H
- items:
+ - const: renesas,r9a09g087-rsci # RZ/N2H
- const: renesas,r9a09g077-rsci # RZ/T2H
reg:
maxItems: 1
interrupts:
+ minItems: 4
items:
- description: Error interrupt
- description: Receive buffer full interrupt
- description: Transmit buffer empty interrupt
- description: Transmit end interrupt
+ - description: Active edge detection interrupt
+ - description: Break field detection interrupt
interrupt-names:
+ minItems: 4
items:
- const: eri
- const: rxi
- const: txi
- const: tei
+ - const: aed
+ - const: bfd
clocks:
minItems: 2
- maxItems: 3
+ maxItems: 6
clock-names:
- minItems: 2
+ oneOf:
+ - items:
+ - const: operation
+ - const: bus
+ - const: sck # optional external clock input
+
+ minItems: 2
+
+ - items:
+ - const: pclk
+ - const: tclk
+ - const: tclk_div4
+ - const: tclk_div16
+ - const: tclk_div64
+ - const: sck # optional external clock input
+
+ minItems: 5
+
+ resets:
items:
- - const: operation
- - const: bus
- - const: sck # optional external clock input
+ - description: Input for resetting the APB clock
+ - description: Input for resetting TCLK
+
+ reset-names:
+ items:
+ - const: presetn
+ - const: tresetn
power-domains:
maxItems: 1
@@ -62,6 +88,57 @@ required:
- clock-names
- power-domains
+allOf:
+ - $ref: serial.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a09g077-rsci
+ then:
+ properties:
+ interrupts:
+ maxItems: 4
+
+ interrupt-names:
+ maxItems: 4
+
+ clocks:
+ minItems: 2
+ maxItems: 3
+
+ clock-names:
+ minItems: 2
+ maxItems: 3
+
+ resets: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a09g047-rsci
+ then:
+ properties:
+ interrupts:
+ minItems: 6
+
+ interrupt-names:
+ minItems: 6
+
+ clocks:
+ minItems: 5
+ maxItems: 6
+
+ clock-names:
+ minItems: 5
+ maxItems: 6
+
+ required:
+ - resets
+ - reset-names
+
unevaluatedProperties: false
examples:
--
2.43.0On Sat, Nov 29, 2025 at 04:42:57PM +0000, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Add documentation for the serial communication interface (RSCI) found on
> the Renesas RZ/G3E (R9A09G047) SoC. The RSCI IP on this SoC is identical
> to that on the RZ/T2H (R9A09G077) SoC, but it has a 32-stage FIFO compared
> to 16 on RZ/T2H. It supports both FIFO and non-FIFO mode operation. RZ/G3E
> has 6 clocks(5 module clocks + 1 external clock) compared to 3 clocks
> (2 module clocks + 1 external clock) on RZ/T2H, and it has multiple resets.
> It has 6 interrupts compared to 4 on RZ/T2H.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v4->v5:
> * Updated commit description related to IRQ difference
> * Added aed and bfd irqs for RZ/G3E.
> * Moved reset: false to RZ/T2H SoC and dropped the else part for RZ/G3E.
> * Updated conditional schema with interrupts and interrupts-names.
> * Dropped the tag as there are new changes.
> v3->v4:
> * Dropped separate compatible for non-FIFO mode and instead using single
> compatible "renesas,r9a09g047-rsci" as non-FIFO mode can be achieved
> by software configuration.
> * Renamed clock-names bus->pclk
> * Rearranged clock-names tclk{4, 16, 64}
> * Retained the tag as the changes are trivial.
> v2->v3:
> * Dropped 1st and 3rd items from clk-names and added minItems for the
> range.
> * Added minItems for clk and clk-names for RZ/T2H as the range is 2-3
> * Added maxItems for clk and clk-names for RZ/G3E as the range is 5-6
> * Retained the tag as it is trivial change.
> v1->v2:
> * Updated commit message
> * Added resets:false for non RZ/G3E SoCs.
> ---
> .../bindings/serial/renesas,rsci.yaml | 99 ++++++++++++++++---
> 1 file changed, 88 insertions(+), 11 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> index 6b1f827a335b..1f8cee8171de 100644
> --- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> +++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> @@ -10,46 +10,72 @@ maintainers:
> - Geert Uytterhoeven <geert+renesas@glider.be>
> - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> -allOf:
> - - $ref: serial.yaml#
> -
> properties:
> compatible:
> oneOf:
> - - items:
> - - const: renesas,r9a09g087-rsci # RZ/N2H
> - - const: renesas,r9a09g077-rsci # RZ/T2H
> + - enum:
> + - renesas,r9a09g047-rsci # RZ/G3E
> + - renesas,r9a09g077-rsci # RZ/T2H
>
> - items:
> + - const: renesas,r9a09g087-rsci # RZ/N2H
> - const: renesas,r9a09g077-rsci # RZ/T2H
>
> reg:
> maxItems: 1
>
> interrupts:
> + minItems: 4
> items:
> - description: Error interrupt
> - description: Receive buffer full interrupt
> - description: Transmit buffer empty interrupt
> - description: Transmit end interrupt
> + - description: Active edge detection interrupt
> + - description: Break field detection interrupt
>
> interrupt-names:
> + minItems: 4
> items:
> - const: eri
> - const: rxi
> - const: txi
> - const: tei
> + - const: aed
> + - const: bfd
>
> clocks:
> minItems: 2
> - maxItems: 3
> + maxItems: 6
>
> clock-names:
> - minItems: 2
> + oneOf:
> + - items:
> + - const: operation
> + - const: bus
> + - const: sck # optional external clock input
> +
> + minItems: 2
> +
> + - items:
> + - const: pclk
> + - const: tclk
> + - const: tclk_div4
> + - const: tclk_div16
> + - const: tclk_div64
> + - const: sck # optional external clock input
> +
> + minItems: 5
> +
> + resets:
> items:
> - - const: operation
> - - const: bus
> - - const: sck # optional external clock input
> + - description: Input for resetting the APB clock
> + - description: Input for resetting TCLK
> +
> + reset-names:
> + items:
> + - const: presetn
> + - const: tresetn
You did not include lore links, so I cannot check whether we already
talked about this (why you still do not send big patchsets like this
with b4?), but you are mixing here devices with completely different
innputs. This does not make the binding readable.
Split the binding.
Best regards,
Krzysztof
On Sat, 29 Nov 2025 16:42:57 +0000, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Add documentation for the serial communication interface (RSCI) found on
> the Renesas RZ/G3E (R9A09G047) SoC. The RSCI IP on this SoC is identical
> to that on the RZ/T2H (R9A09G077) SoC, but it has a 32-stage FIFO compared
> to 16 on RZ/T2H. It supports both FIFO and non-FIFO mode operation. RZ/G3E
> has 6 clocks(5 module clocks + 1 external clock) compared to 3 clocks
> (2 module clocks + 1 external clock) on RZ/T2H, and it has multiple resets.
> It has 6 interrupts compared to 4 on RZ/T2H.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v4->v5:
> * Updated commit description related to IRQ difference
> * Added aed and bfd irqs for RZ/G3E.
> * Moved reset: false to RZ/T2H SoC and dropped the else part for RZ/G3E.
> * Updated conditional schema with interrupts and interrupts-names.
> * Dropped the tag as there are new changes.
> v3->v4:
> * Dropped separate compatible for non-FIFO mode and instead using single
> compatible "renesas,r9a09g047-rsci" as non-FIFO mode can be achieved
> by software configuration.
> * Renamed clock-names bus->pclk
> * Rearranged clock-names tclk{4, 16, 64}
> * Retained the tag as the changes are trivial.
> v2->v3:
> * Dropped 1st and 3rd items from clk-names and added minItems for the
> range.
> * Added minItems for clk and clk-names for RZ/T2H as the range is 2-3
> * Added maxItems for clk and clk-names for RZ/G3E as the range is 5-6
> * Retained the tag as it is trivial change.
> v1->v2:
> * Updated commit message
> * Added resets:false for non RZ/G3E SoCs.
> ---
> .../bindings/serial/renesas,rsci.yaml | 99 ++++++++++++++++---
> 1 file changed, 88 insertions(+), 11 deletions(-)
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/thermal/thermal-zones.example.dtb: /example-0/soc/thermal-sensor@c263000: failed to match any schema with compatible: ['qcom,sdm845-tsens', 'qcom,tsens-v2']
Documentation/devicetree/bindings/thermal/thermal-zones.example.dtb: /example-0/soc/thermal-sensor@c263000: failed to match any schema with compatible: ['qcom,sdm845-tsens', 'qcom,tsens-v2']
Documentation/devicetree/bindings/thermal/thermal-zones.example.dtb: /example-0/soc/thermal-sensor@c265000: failed to match any schema with compatible: ['qcom,sdm845-tsens', 'qcom,tsens-v2']
Documentation/devicetree/bindings/thermal/thermal-zones.example.dtb: /example-0/soc/thermal-sensor@c265000: failed to match any schema with compatible: ['qcom,sdm845-tsens', 'qcom,tsens-v2']
Documentation/devicetree/bindings/thermal/thermal-sensor.example.dtb: /example-0/soc/thermal-sensor@c263000: failed to match any schema with compatible: ['qcom,sdm845-tsens', 'qcom,tsens-v2']
Documentation/devicetree/bindings/thermal/thermal-sensor.example.dtb: /example-0/soc/thermal-sensor@c263000: failed to match any schema with compatible: ['qcom,sdm845-tsens', 'qcom,tsens-v2']
Documentation/devicetree/bindings/thermal/thermal-sensor.example.dtb: /example-0/soc/thermal-sensor@c265000: failed to match any schema with compatible: ['qcom,sdm845-tsens', 'qcom,tsens-v2']
Documentation/devicetree/bindings/thermal/thermal-sensor.example.dtb: /example-0/soc/thermal-sensor@c265000: failed to match any schema with compatible: ['qcom,sdm845-tsens', 'qcom,tsens-v2']
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20251129164325.209213-2-biju.das.jz@bp.renesas.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
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