.../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 17 +- arch/arm64/boot/dts/qcom/monaco-evk.dts | 85 ++++ arch/arm64/boot/dts/qcom/monaco.dtsi | 374 +++++++++++++++++- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 84 ++++ 4 files changed, 543 insertions(+), 17 deletions(-)
This series adds document, phy, configs support for PCIe in QCS8300.
It also adds 'link_down' reset for sa8775p.
Have follwing changes:
- Add dedicated schema for the PCIe controllers found on QCS8300.
- Add compatible for qcs8300 platform.
- Add configurations in devicetree for PCIe0, including registers, clocks, interrupts and phy setting sequence.
- Add configurations in devicetree for PCIe1, including registers, clocks, interrupts and phy setting sequence.
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
---
Changes in v15:
- rebase patches
- fix incorrect indentation (Dmitry)
- Add patches for monaco-evk enablement
- Link to v14: https://lore.kernel.org/all/20251024095609.48096-1-ziyue.zhang@oss.qualcomm.com/
Changes in v14:
- rebase patches
- Link to v13: https://lore.kernel.org/all/20250908073848.3045957-1-ziyue.zhang@oss.qualcomm.com/
Changes in v13:
- Fix dtb error
- Link to v12: https://lore.kernel.org/all/20250905071448.2034594-1-ziyue.zhang@oss.qualcomm.com/
Changes in v12:
- rebased pcie phy bindings
- Link to v11: https://lore.kernel.org/all/20250826091205.3625138-1-ziyue.zhang@oss.qualcomm.com/
Changes in v11:
- move phy/perst/wake to pcie bridge node (Mani)
- Link to v10: https://lore.kernel.org/all/20250811071131.982983-1-ziyue.zhang@oss.qualcomm.com/
Changes in v10:
- Update PHY max_items (Johan)
- Link to v9: https://lore.kernel.org/all/20250725104037.4054070-1-ziyue.zhang@oss.qualcomm.com/
Changes in v9:
- Fix DTB error (Vinod)
- Link to v8: https://lore.kernel.org/all/20250714081529.3847385-1-ziyue.zhang@oss.qualcomm.com/
Changes in v8:
- rebase sc8280xp-qmp-pcie-phy change to solve conflicts.
- Add Fixes tag to phy change (Johan)
- Link to v7: https://lore.kernel.org/all/20250625092539.762075-1-quic_ziyuzhan@quicinc.com/
Changes in v7:
- rebase qcs8300-ride.dtsi change to solve conflicts.
- Link to v6: https://lore.kernel.org/all/20250529035635.4162149-1-quic_ziyuzhan@quicinc.com/
Changes in v6:
- move the qcs8300 and sa8775p phy compatibility entry into the list of PHYs that require six clocks
- Update QCS8300 and sa8775p phy dt, remove aux clock.
- Fixed compile error found by kernel test robot
- Link to v5: https://lore.kernel.org/all/20250507031019.4080541-1-quic_ziyuzhan@quicinc.com/
Changes in v5:
- Add QCOM PCIe controller version in commit msg (Mani)
- Modify platform dts change subject (Dmitry)
- Fixed compile error found by kernel test robot
- Link to v4: https://lore.kernel.org/linux-phy/20241220055239.2744024-1-quic_ziyuzhan@quicinc.com/
Changes in v4:
- Add received tag
- Fixed compile error found by kernel test robot
- Link to v3: https://lore.kernel.org/lkml/202412211301.bQO6vXpo-lkp@intel.com/T/#mdd63e5be39acbf879218aef91c87b12d4540e0f7
Changes in v3:
- Add received tag(Rob & Dmitry)
- Update pcie_phy in gcc node to soc dtsi(Dmitry & Konrad)
- remove pcieprot0 node(Konrad & Mani)
- Fix format comments(Konrad)
- Update base-commit to tag: next-20241213(Bjorn)
- Corrected of_device_id.data from 1.9.0 to 1.34.0.
- Link to v2: https://lore.kernel.org/all/20241128081056.1361739-1-quic_ziyuzhan@quicinc.com/
Changes in v2:
- Fix some format comments and match the style in x1e80100(Konrad)
- Add global interrupt for PCIe0 and PCIe1(Konrad)
- split the soc dtsi and the platform dts into two changes(Konrad)
- Link to v1: https://lore.kernel.org/all/20241114095409.2682558-1-quic_ziyuzhan@quicinc.com/
Sushrut Shree Trivedi (1):
arm64: dts: qcom: monaco-evk: Enable PCIe0 and PCIe1.
Ziyue Zhang (5):
dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings
for qcs8300
arm64: dts: qcom: qcs8300: enable pcie0
arm64: dts: qcom: qcs8300-ride: enable pcie0 interface
arm64: dts: qcom: qcs8300: enable pcie1
arm64: dts: qcom: qcs8300-ride: enable pcie1 interface
.../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 17 +-
arch/arm64/boot/dts/qcom/monaco-evk.dts | 85 ++++
arch/arm64/boot/dts/qcom/monaco.dtsi | 374 +++++++++++++++++-
arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 84 ++++
4 files changed, 543 insertions(+), 17 deletions(-)
--
2.34.1
On Fri, Nov 28, 2025 at 06:49:22PM +0800, Ziyue Zhang wrote: > This series adds document, phy, configs support for PCIe in QCS8300. > It also adds 'link_down' reset for sa8775p. > > Have follwing changes: > - Add dedicated schema for the PCIe controllers found on QCS8300. > - Add compatible for qcs8300 platform. > - Add configurations in devicetree for PCIe0, including registers, clocks, interrupts and phy setting sequence. > - Add configurations in devicetree for PCIe1, including registers, clocks, interrupts and phy setting sequence. > Vinod, ping on the bindings patch! - Mani > Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> > Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com> > --- > Changes in v15: > - rebase patches > - fix incorrect indentation (Dmitry) > - Add patches for monaco-evk enablement > - Link to v14: https://lore.kernel.org/all/20251024095609.48096-1-ziyue.zhang@oss.qualcomm.com/ > > Changes in v14: > - rebase patches > - Link to v13: https://lore.kernel.org/all/20250908073848.3045957-1-ziyue.zhang@oss.qualcomm.com/ > > Changes in v13: > - Fix dtb error > - Link to v12: https://lore.kernel.org/all/20250905071448.2034594-1-ziyue.zhang@oss.qualcomm.com/ > > Changes in v12: > - rebased pcie phy bindings > - Link to v11: https://lore.kernel.org/all/20250826091205.3625138-1-ziyue.zhang@oss.qualcomm.com/ > > Changes in v11: > - move phy/perst/wake to pcie bridge node (Mani) > - Link to v10: https://lore.kernel.org/all/20250811071131.982983-1-ziyue.zhang@oss.qualcomm.com/ > > Changes in v10: > - Update PHY max_items (Johan) > - Link to v9: https://lore.kernel.org/all/20250725104037.4054070-1-ziyue.zhang@oss.qualcomm.com/ > > Changes in v9: > - Fix DTB error (Vinod) > - Link to v8: https://lore.kernel.org/all/20250714081529.3847385-1-ziyue.zhang@oss.qualcomm.com/ > > Changes in v8: > - rebase sc8280xp-qmp-pcie-phy change to solve conflicts. > - Add Fixes tag to phy change (Johan) > - Link to v7: https://lore.kernel.org/all/20250625092539.762075-1-quic_ziyuzhan@quicinc.com/ > > Changes in v7: > - rebase qcs8300-ride.dtsi change to solve conflicts. > - Link to v6: https://lore.kernel.org/all/20250529035635.4162149-1-quic_ziyuzhan@quicinc.com/ > > Changes in v6: > - move the qcs8300 and sa8775p phy compatibility entry into the list of PHYs that require six clocks > - Update QCS8300 and sa8775p phy dt, remove aux clock. > - Fixed compile error found by kernel test robot > - Link to v5: https://lore.kernel.org/all/20250507031019.4080541-1-quic_ziyuzhan@quicinc.com/ > > Changes in v5: > - Add QCOM PCIe controller version in commit msg (Mani) > - Modify platform dts change subject (Dmitry) > - Fixed compile error found by kernel test robot > - Link to v4: https://lore.kernel.org/linux-phy/20241220055239.2744024-1-quic_ziyuzhan@quicinc.com/ > > Changes in v4: > - Add received tag > - Fixed compile error found by kernel test robot > - Link to v3: https://lore.kernel.org/lkml/202412211301.bQO6vXpo-lkp@intel.com/T/#mdd63e5be39acbf879218aef91c87b12d4540e0f7 > > Changes in v3: > - Add received tag(Rob & Dmitry) > - Update pcie_phy in gcc node to soc dtsi(Dmitry & Konrad) > - remove pcieprot0 node(Konrad & Mani) > - Fix format comments(Konrad) > - Update base-commit to tag: next-20241213(Bjorn) > - Corrected of_device_id.data from 1.9.0 to 1.34.0. > - Link to v2: https://lore.kernel.org/all/20241128081056.1361739-1-quic_ziyuzhan@quicinc.com/ > > Changes in v2: > - Fix some format comments and match the style in x1e80100(Konrad) > - Add global interrupt for PCIe0 and PCIe1(Konrad) > - split the soc dtsi and the platform dts into two changes(Konrad) > - Link to v1: https://lore.kernel.org/all/20241114095409.2682558-1-quic_ziyuzhan@quicinc.com/ > > Sushrut Shree Trivedi (1): > arm64: dts: qcom: monaco-evk: Enable PCIe0 and PCIe1. > > Ziyue Zhang (5): > dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings > for qcs8300 > arm64: dts: qcom: qcs8300: enable pcie0 > arm64: dts: qcom: qcs8300-ride: enable pcie0 interface > arm64: dts: qcom: qcs8300: enable pcie1 > arm64: dts: qcom: qcs8300-ride: enable pcie1 interface > > .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 17 +- > arch/arm64/boot/dts/qcom/monaco-evk.dts | 85 ++++ > arch/arm64/boot/dts/qcom/monaco.dtsi | 374 +++++++++++++++++- > arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 84 ++++ > 4 files changed, 543 insertions(+), 17 deletions(-) > > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம்
On Fri, 28 Nov 2025 18:49:22 +0800, Ziyue Zhang wrote:
> This series adds document, phy, configs support for PCIe in QCS8300.
> It also adds 'link_down' reset for sa8775p.
>
> Have follwing changes:
> - Add dedicated schema for the PCIe controllers found on QCS8300.
> - Add compatible for qcs8300 platform.
> - Add configurations in devicetree for PCIe0, including registers, clocks, interrupts and phy setting sequence.
> - Add configurations in devicetree for PCIe1, including registers, clocks, interrupts and phy setting sequence.
>
> [...]
Applied, thanks!
[1/6] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings for qcs8300
commit: 393e132efcc5e3fc4ef2bd9bbed2a096096c9359
Best regards,
--
~Vinod
On Fri, 28 Nov 2025 18:49:22 +0800, Ziyue Zhang wrote:
> This series adds document, phy, configs support for PCIe in QCS8300.
> It also adds 'link_down' reset for sa8775p.
>
> Have follwing changes:
> - Add dedicated schema for the PCIe controllers found on QCS8300.
> - Add compatible for qcs8300 platform.
> - Add configurations in devicetree for PCIe0, including registers, clocks, interrupts and phy setting sequence.
> - Add configurations in devicetree for PCIe1, including registers, clocks, interrupts and phy setting sequence.
>
> [...]
Applied, thanks!
[2/6] arm64: dts: qcom: qcs8300: enable pcie0
commit: 46a7c01e7e9d296ba09bad579ae0277cfb558b24
[3/6] arm64: dts: qcom: qcs8300-ride: enable pcie0 interface
commit: 33967eadb2153d92ea1de6e9c9ac8ade21c74d86
[4/6] arm64: dts: qcom: qcs8300: enable pcie1
commit: 7565ec0170201aca07c9e1c3b5b6f213c5024599
[5/6] arm64: dts: qcom: qcs8300-ride: enable pcie1 interface
commit: cdb613a84527197f88f8bff3c5ee015e611a8373
[6/6] arm64: dts: qcom: monaco-evk: Enable PCIe0 and PCIe1.
commit: 41e2424651f7c679382bb9e32225d3b541d4aa8d
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
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