.../devicetree/bindings/clock/canaan,k230-clk.yaml | 59 + arch/riscv/boot/dts/canaan/k230-canmv.dts | 11 + arch/riscv/boot/dts/canaan/k230-evb.dts | 11 + arch/riscv/boot/dts/canaan/k230.dtsi | 26 +- drivers/clk/Kconfig | 6 + drivers/clk/Makefile | 1 + drivers/clk/clk-k230.c | 2443 ++++++++++++++++++++ include/dt-bindings/clock/canaan,k230-clk.h | 222 ++ 8 files changed, 2771 insertions(+), 8 deletions(-)
This patch series adds clock controller support for the Canaan Kendryte
K230 SoC. The K230 SoC includes an external 24MHz OSC, 4 internal
PLLs and an external pulse input, with the controller managing these
sources and their derived clocks.
The clock tree and hardware-specific definition can be found in the
vendor's DTS [1],
and this series is based on the K230 initial series [2].
Link: https://github.com/ruyisdk/linux-xuantie-kernel/blob/linux-6.6.36/arch/riscv/boot/dts/canaan/k230_clock_provider.dtsi [1]
Link: https://lore.kernel.org/linux-clk/tencent_F76EB8D731C521C18D5D7C4F8229DAA58E08@qq.com/ [2]
Co-developed-by: Troy Mitchell <TroyMitchell988@gmail.com>
Signed-off-by: Troy Mitchell <TroyMitchell988@gmail.com>
Signed-off-by: Xukai Wang <kingxukai@zohomail.com>
---
Changes in v9:
- Rebase base-commit to v6.18-rc1
- Simplified PLL field extraction with FIELD_GET() macro
- Drop MODULE_DEVICE_TABLE for k230_clk_ids
- Replace k230_clk_find_approximate_mul_div's step with
Rational_best_approximation
- Reorder declaration and defination for clk_ops
- Link to v8: https://lore.kernel.org/r/20250905-b4-k230-clk-v8-0-96caa02d5428@zohomail.com
Changes in v8:
- Rename dts node name "timer_pulse_in" to "clock-50m"
- Drop redundant comment and 'minItems' of hardware in dt-binding.
- Link to v7: https://lore.kernel.org/r/20250730-b4-k230-clk-v7-0-c57d3bb593d3@zohomail.com
Changes in v7:
- Rename K230_PLL_STATUS_MASK to K230_PLL_LOCK_STATUS_MASK
- Add clkdev for PLLs to register lookup
- Add macros to generate repeat variables definition
- Refine the definitions of k230 clocks
- Split composite clks into rate, gate, mux, fixed_factor clk
- Replace k230_clk_hw_onecell_get with of_clk_hw_onecell_get for
clock provider
- Drop k230_sysclk and use clk_mux, clk_gate and clk_fixed_factor
as the data structures.
- Replace one loop registration with individual registration for
each type.
- Link to v6: https://lore.kernel.org/r/20250415-b4-k230-clk-v6-0-7fd89f427250@zohomail.com
Changes in v6:
- Remove some redundant comments in struct declaration.
- Replace the Vendor's code source link with a new one.
- Link to v5: https://lore.kernel.org/r/20250320-b4-k230-clk-v5-0-0e9d089c5488@zohomail.com
Changes in v5:
- Fix incorrect base-commit and add prerequisite-patch-id.
- Replace dummy apb_clk with real ones for UARTs.
- Add IDs of UARTs clock and DMA clocks in the binding header.
- Replace k230_clk_cfgs[] array with corresponding named variables.
- Remove some redundant checks in clk_ops.
- Drop the unnecessary parenthesis and type casts.
- Modify return value handling in probe path to avoid redundant print.
- Link to v4: https://lore.kernel.org/r/20250217-b4-k230-clk-v4-0-5a95a3458691@zohomail.com
Changes in v4:
- Remove redundant onecell_get callback and add_provider function
for pll_divs.
- Modify the base-commit in cover letter.
- Link to v3: https://lore.kernel.org/r/20250203-b4-k230-clk-v3-0-362c79124572@zohomail.com
Changes in v3:
- Reorder the defination and declaration in drivers code.
- Reorder the properties in dts node.
- Replace global variable `k230_sysclk` with dynamic memory allocation.
- Rename the macro K230_NUM_CLKS to K230_CLK_NUM.
- Use dev_err_probe for error handling.
- Remove unused includes.
- Link to v2: https://lore.kernel.org/r/20250108-b4-k230-clk-v2-0-27b30a2ca52d@zohomail.com
Changes in v2:
- Add items and description.
- Rename k230-clk.h to canaan,k230-clk.h
- Link to v1: https://lore.kernel.org/r/20241229-b4-k230-clk-v1-0-221a917e80ed@zohomail.com
---
Xukai Wang (3):
dt-bindings: clock: Add bindings for Canaan K230 clock controller
clk: canaan: Add clock driver for Canaan K230
riscv: dts: canaan: Add clock definition for K230
.../devicetree/bindings/clock/canaan,k230-clk.yaml | 59 +
arch/riscv/boot/dts/canaan/k230-canmv.dts | 11 +
arch/riscv/boot/dts/canaan/k230-evb.dts | 11 +
arch/riscv/boot/dts/canaan/k230.dtsi | 26 +-
drivers/clk/Kconfig | 6 +
drivers/clk/Makefile | 1 +
drivers/clk/clk-k230.c | 2443 ++++++++++++++++++++
include/dt-bindings/clock/canaan,k230-clk.h | 222 ++
8 files changed, 2771 insertions(+), 8 deletions(-)
---
base-commit: 3a8660878839faadb4f1a6dd72c3179c1df56787
change-id: 20241206-b4-k230-clk-925f33fed6c2
prerequisite-patch-id: deda3c472f0000ffd40cddd7cf6d3b5e2d7da7dc
Best regards,
--
Xukai Wang <kingxukai@zohomail.com>
I'm writing to share test results and the corresponding patch for
K230 clock configuration issues, covering critical clock flag
settings and HS/SD subsystem clock adjustments.
1. Critical Clock Protection for CPU Subsystems
I found that cpu0/cpu1 core-related clocks (src/plic/apb/noc_ddrcp4
etc.) had no protection, risking accidental disabling and subsystem
malfunctions. I added the `CLK_IS_CRITICAL` flag to these clock
nodes to block unintended disable operations.
2. HS/SD Clock Setting Fixes
Two hardware-spec mismatches were fixed:
- Adjusted `hs_hclk_src_gate` from register bit1 to bit0, and
updated its parent clock from `hs_hclk_high_src_rate` to
`hs_hclk_high_gate`.
- Corrected `hs_sd_card_src_rate` parent clock from `pll0_div4` to
`hs_sd_card_src_gate`, fixing SD controller clock source
misconfiguration.
3. Test Verification
Post-fix on-board testing confirmed all modified clock nodes align
with K230 hardware specs and the clock tree relationships are
correct.
The CPU core and HS/SD subsystems run stably without any clock-
related errors or anomalies.
The patch modifies `drivers/clk/clk-k230.c` (19 insertions, 19
deletions), with the full diff attached below for your review.
Best regards,
Jiayu Du
---
drivers/clk/clk-k230.c | 38 +++++++++++++++++++-------------------
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/drivers/clk/clk-k230.c b/drivers/clk/clk-k230.c
index 8750e9cbac..43a4e61a0c 100644
--- a/drivers/clk/clk-k230.c
+++ b/drivers/clk/clk-k230.c
@@ -317,7 +317,7 @@ struct clk_fixed_factor *k230_pll_divs[] = {
K230_CLK_GATE_FORMAT(cpu0_src_gate,
K230_CPU0_SRC_GATE,
- 0, 0, 0, 0,
+ 0, 0, CLK_IS_CRITICAL, 0,
&pll0_div2.hw);
K230_CLK_RATE_FORMAT(cpu0_src_rate,
@@ -325,7 +325,7 @@ K230_CLK_RATE_FORMAT(cpu0_src_rate,
1, 16, 1, 0xF,
16, 16, 0, 0x0,
0x0, 31, mul, 0x0,
- false, 0,
+ false, CLK_IS_CRITICAL,
&cpu0_src_gate.clk.hw);
K230_CLK_RATE_FORMAT(cpu0_axi_rate,
@@ -333,12 +333,12 @@ K230_CLK_RATE_FORMAT(cpu0_axi_rate,
1, 1, 0, 0,
1, 8, 6, 0x7,
0x0, 31, div, 0x0,
- 0, 0,
+ 0, CLK_IS_CRITICAL,
&cpu0_src_rate.clk.hw);
K230_CLK_GATE_FORMAT(cpu0_plic_gate,
K230_CPU0_PLIC_GATE,
- 0x0, 9, 0, 0,
+ 0x0, 9, CLK_IS_CRITICAL, 0,
&cpu0_src_rate.clk.hw);
K230_CLK_RATE_FORMAT(cpu0_plic_rate,
@@ -346,17 +346,17 @@ K230_CLK_RATE_FORMAT(cpu0_plic_rate,
1, 1, 0, 0,
1, 8, 10, 0x7,
0x0, 31, div, 0x0,
- false, 0,
+ false, CLK_IS_CRITICAL,
&cpu0_plic_gate.clk.hw);
K230_CLK_GATE_FORMAT(cpu0_noc_ddrcp4_gate,
K230_CPU0_NOC_DDRCP4_GATE,
- 0x60, 7, 0, 0,
+ 0x60, 7, CLK_IS_CRITICAL, 0,
&cpu0_src_rate.clk.hw);
K230_CLK_GATE_FORMAT(cpu0_apb_gate,
K230_CPU0_APB_GATE,
- 0x0, 13, 0, 0,
+ 0x0, 13, CLK_IS_CRITICAL, 0,
&pll0_div4.hw);
K230_CLK_RATE_FORMAT(cpu0_apb_rate,
@@ -364,7 +364,7 @@ K230_CLK_RATE_FORMAT(cpu0_apb_rate,
1, 1, 0, 0,
1, 8, 15, 0x7,
0x0, 31, div, 0x0,
- false, 0,
+ false, CLK_IS_CRITICAL,
&cpu0_apb_gate.clk.hw);
static const struct clk_parent_data k230_cpu1_src_mux_pdata[] = {
@@ -376,12 +376,12 @@ static const struct clk_parent_data k230_cpu1_src_mux_pdata[] = {
K230_CLK_MUX_FORMAT(cpu1_src_mux,
K230_CPU1_SRC_MUX,
0x4, 1, 0x3,
- 0, 0,
+ CLK_IS_CRITICAL, 0,
k230_cpu1_src_mux_pdata);
K230_CLK_GATE_FORMAT(cpu1_src_gate,
K230_CPU1_SRC_GATE,
- 0x4, 0, CLK_IGNORE_UNUSED, 0,
+ 0x4, 0, CLK_IS_CRITICAL, 0,
&cpu1_src_mux.clk.hw);
K230_CLK_RATE_FORMAT(cpu1_src_rate,
@@ -389,7 +389,7 @@ K230_CLK_RATE_FORMAT(cpu1_src_rate,
1, 1, 0, 0,
1, 8, 3, 0x7,
0x4, 31, div, 0x0,
- false, 0,
+ false, CLK_IS_CRITICAL,
&cpu1_src_gate.clk.hw);
K230_CLK_RATE_FORMAT(cpu1_axi_rate,
@@ -397,12 +397,12 @@ K230_CLK_RATE_FORMAT(cpu1_axi_rate,
1, 1, 0, 0,
1, 8, 12, 0x7,
0x4, 31, div, 0x0,
- false, 0,
+ false, CLK_IS_CRITICAL,
&cpu1_src_rate.clk.hw);
K230_CLK_GATE_FORMAT(cpu1_plic_gate,
K230_CPU1_PLIC_GATE,
- 0x4, 15, CLK_IGNORE_UNUSED, 0,
+ 0x4, 15, CLK_IS_CRITICAL, 0,
&cpu1_src_rate.clk.hw);
K230_CLK_RATE_FORMAT(cpu1_plic_rate,
@@ -410,12 +410,12 @@ K230_CLK_RATE_FORMAT(cpu1_plic_rate,
1, 1, 0, 0,
1, 8, 16, 0x7,
0x4, 31, div, 0x0,
- false, 0,
+ false, CLK_IS_CRITICAL,
&cpu1_plic_gate.clk.hw);
K230_CLK_GATE_FORMAT(cpu1_apb_gate,
K230_CPU1_APB_GATE,
- 0x4, 19, 0, 0,
+ 0x4, 19, CLK_IS_CRITICAL, 0,
&pll0_div4.hw);
K230_CLK_RATE_FORMAT(cpu1_apb_rate,
@@ -423,7 +423,7 @@ K230_CLK_RATE_FORMAT(cpu1_apb_rate,
1, 1, 0, 0,
1, 8, 15, 0x7,
0x0, 31, div, 0x0,
- false, 0,
+ false, CLK_IS_CRITICAL,
&cpu1_apb_gate.clk.hw);
K230_CLK_GATE_FORMAT_PNAME(pmu_apb_gate,
@@ -446,8 +446,8 @@ K230_CLK_GATE_FORMAT(hs_hclk_high_gate,
K230_CLK_GATE_FORMAT(hs_hclk_src_gate,
K230_HS_HCLK_SRC_GATE,
- 0x18, 1, 0, 0,
- &hs_hclk_high_src_rate.clk.hw);
+ 0x18, 0, 0, 0,
+ &hs_hclk_high_gate.clk.hw);
K230_CLK_RATE_FORMAT(hs_hclk_src_rate,
K230_HS_HCLK_SRC_RATE,
@@ -560,7 +560,7 @@ K230_CLK_RATE_FORMAT(hs_sd_card_src_rate,
2, 8, 12, 0x7,
0x1C, 31, div, 0x0,
false, 0,
- &pll0_div4.hw);
+ &hs_sd_card_src_gate.clk.hw);
K230_CLK_GATE_FORMAT(hs_sd0_card_gate,
K230_HS_SD0_CARD_GATE,
On Thu, Nov 27, 2025 at 08:45:11PM +0800, Xukai Wang wrote: > This patch series adds clock controller support for the Canaan Kendryte > K230 SoC. The K230 SoC includes an external 24MHz OSC, 4 internal > PLLs and an external pulse input, with the controller managing these > sources and their derived clocks. > > The clock tree and hardware-specific definition can be found in the > vendor's DTS [1], > and this series is based on the K230 initial series [2]. FWIW, I've had this on a branch since 6.9, waiting for the clock driver to replace the fake apb-clk-clock: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/log/?h=k230-basic I'm assuming Stephen will grab patches 1 & 2 if he is happy with what's here, and then I'll pick up the dts patch after that.
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