From: Icenowy Zheng <uwu@icenowy.me>
Verisilicon has a series of display controllers prefixed with DC and
with self-identification facility like their GC series GPUs.
Add a device tree binding for it.
Depends on the specific DC model, it can have either one or two display
outputs, and each display output could be set to DPI signal or "DP"
signal (which seems to be some plain parallel bus to HDMI controllers).
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
---
Changes in v3:
- Added SoC-specific compatible string, and arm the binding with clock /
port checking for the specific SoC (with a 2-output DC).
Changes in v2:
- Fixed misspelt "versilicon" in title.
- Moved minItems in clock properties to be earlier than items.
- Re-aligned multi-line clocks and resets in example.
.../bindings/display/verisilicon,dc.yaml | 146 ++++++++++++++++++
1 file changed, 146 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/verisilicon,dc.yaml
diff --git a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml
new file mode 100644
index 0000000000000..522a544498bea
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml
@@ -0,0 +1,146 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/verisilicon,dc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Verisilicon DC-series display controllers
+
+maintainers:
+ - Icenowy Zheng <uwu@icenowy.me>
+
+properties:
+ $nodename:
+ pattern: "^display@[0-9a-f]+$"
+
+ compatible:
+ items:
+ - enum:
+ - thead,th1520-dc8200
+ - const: verisilicon,dc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 4
+ items:
+ - description: DC Core clock
+ - description: DMA AXI bus clock
+ - description: Configuration AHB bus clock
+ - description: Pixel clock of output 0
+ - description: Pixel clock of output 1
+
+ clock-names:
+ minItems: 4
+ items:
+ - const: core
+ - const: axi
+ - const: ahb
+ - const: pix0
+ - const: pix1
+
+ resets:
+ items:
+ - description: DC Core reset
+ - description: DMA AXI bus reset
+ - description: Configuration AHB bus reset
+
+ reset-names:
+ items:
+ - const: core
+ - const: axi
+ - const: ahb
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: The first output channel , endpoint 0 should be
+ used for DPI format output and endpoint 1 should be used
+ for DP format output.
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: The second output channel if the DC variant
+ supports. Follow the same endpoint addressing rule with
+ the first port.
+
+ required:
+ - port@0
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - ports
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: thead,th1520-dc8200
+ then:
+ properties:
+ clocks:
+ minItems: 5
+ ports:
+ required:
+ - port@0
+ - port@1
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/clock/thead,th1520-clk-ap.h>
+ #include <dt-bindings/reset/thead,th1520-reset.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ display@ffef600000 {
+ compatible = "thead,th1520-dc8200", "verisilicon,dc";
+ reg = <0xff 0xef600000 0x0 0x100000>;
+ interrupts = <93 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_vo CLK_DPU_CCLK>,
+ <&clk_vo CLK_DPU_ACLK>,
+ <&clk_vo CLK_DPU_HCLK>,
+ <&clk_vo CLK_DPU_PIXELCLK0>,
+ <&clk_vo CLK_DPU_PIXELCLK1>;
+ clock-names = "core", "axi", "ahb", "pix0", "pix1";
+ resets = <&rst TH1520_RESET_ID_DPU_CORE>,
+ <&rst TH1520_RESET_ID_DPU_AXI>,
+ <&rst TH1520_RESET_ID_DPU_AHB>;
+ reset-names = "core", "axi", "ahb";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dpu_out_dp1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&hdmi_in>;
+ };
+ };
+ };
+ };
+ };
--
2.52.0On Wed, Nov 26, 2025 at 12:52:26PM +0800, Icenowy Zheng wrote: > From: Icenowy Zheng <uwu@icenowy.me> > > Verisilicon has a series of display controllers prefixed with DC and > with self-identification facility like their GC series GPUs. > > Add a device tree binding for it. > > Depends on the specific DC model, it can have either one or two display > outputs, and each display output could be set to DPI signal or "DP" > signal (which seems to be some plain parallel bus to HDMI controllers). > > Signed-off-by: Icenowy Zheng <uwu@icenowy.me> > Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn> > --- You already received review on this. Don't send the same. Read the review. NAK Best regards, Krzysztof
在 2025-11-26星期三的 09:51 +0100，Krzysztof Kozlowski写道： > On Wed, Nov 26, 2025 at 12:52:26PM +0800, Icenowy Zheng wrote: > > From: Icenowy Zheng <uwu@icenowy.me> > > > > Verisilicon has a series of display controllers prefixed with DC > > and > > with self-identification facility like their GC series GPUs. > > > > Add a device tree binding for it. > > > > Depends on the specific DC model, it can have either one or two > > display > > outputs, and each display output could be set to DPI signal or "DP" > > signal (which seems to be some plain parallel bus to HDMI > > controllers). > > > > Signed-off-by: Icenowy Zheng <uwu@icenowy.me> > > Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn> > > --- > > You already received review on this. Don't send the same. Read the > review. Please see the sender (mail header From) of this time. > > NAK > > Best regards, > Krzysztof >
On 26/11/2025 09:57, Icenowy Zheng wrote: > 在 2025-11-26星期三的 09:51 +0100，Krzysztof Kozlowski写道： >> On Wed, Nov 26, 2025 at 12:52:26PM +0800, Icenowy Zheng wrote: >>> From: Icenowy Zheng <uwu@icenowy.me> >>> >>> Verisilicon has a series of display controllers prefixed with DC >>> and >>> with self-identification facility like their GC series GPUs. >>> >>> Add a device tree binding for it. >>> >>> Depends on the specific DC model, it can have either one or two >>> display >>> outputs, and each display output could be set to DPI signal or "DP" >>> signal (which seems to be some plain parallel bus to HDMI >>> controllers). >>> >>> Signed-off-by: Icenowy Zheng <uwu@icenowy.me> >>> Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn> >>> --- >> >> You already received review on this. Don't send the same. Read the >> review. > > Please see the sender (mail header From) of this time. This improved. I am speaking about the rest of review. Best regards, Krzysztof
在 2025-11-26星期三的 10:37 +0100，Krzysztof Kozlowski写道： > On 26/11/2025 09:57, Icenowy Zheng wrote: > > 在 2025-11-26星期三的 09:51 +0100，Krzysztof Kozlowski写道： > > > On Wed, Nov 26, 2025 at 12:52:26PM +0800, Icenowy Zheng wrote: > > > > From: Icenowy Zheng <uwu@icenowy.me> > > > > > > > > Verisilicon has a series of display controllers prefixed with > > > > DC > > > > and > > > > with self-identification facility like their GC series GPUs. > > > > > > > > Add a device tree binding for it. > > > > > > > > Depends on the specific DC model, it can have either one or two > > > > display > > > > outputs, and each display output could be set to DPI signal or > > > > "DP" > > > > signal (which seems to be some plain parallel bus to HDMI > > > > controllers). > > > > > > > > Signed-off-by: Icenowy Zheng <uwu@icenowy.me> > > > > Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn> > > > > --- > > > > > > You already received review on this. Don't send the same. Read > > > the > > > review. > > > > Please see the sender (mail header From) of this time. > > This improved. I am speaking about the rest of review. Well this is why this is a v3 resend, not v4. I will address these issues in v4. > > Best regards, > Krzysztof
On 26/11/2025 10:41, Icenowy Zheng wrote: > 在 2025-11-26星期三的 10:37 +0100，Krzysztof Kozlowski写道： >> On 26/11/2025 09:57, Icenowy Zheng wrote: >>> 在 2025-11-26星期三的 09:51 +0100，Krzysztof Kozlowski写道： >>>> On Wed, Nov 26, 2025 at 12:52:26PM +0800, Icenowy Zheng wrote: >>>>> From: Icenowy Zheng <uwu@icenowy.me> >>>>> >>>>> Verisilicon has a series of display controllers prefixed with >>>>> DC >>>>> and >>>>> with self-identification facility like their GC series GPUs. >>>>> >>>>> Add a device tree binding for it. >>>>> >>>>> Depends on the specific DC model, it can have either one or two >>>>> display >>>>> outputs, and each display output could be set to DPI signal or >>>>> "DP" >>>>> signal (which seems to be some plain parallel bus to HDMI >>>>> controllers). >>>>> >>>>> Signed-off-by: Icenowy Zheng <uwu@icenowy.me> >>>>> Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn> >>>>> --- >>>> >>>> You already received review on this. Don't send the same. Read >>>> the >>>> review. >>> >>> Please see the sender (mail header From) of this time. >> >> This improved. I am speaking about the rest of review. > > Well this is why this is a v3 resend, not v4. > > I will address these issues in v4. You received review. Do not ever make a resend ignoring the review, even if only parts. Make a posting after addressing COMPLETE review. Otherwise this hides the original review and no one will ever find it. It also is quite disrespectful to my time spent on that review. Best regards, Krzysztof
在 2025-11-26星期三的 11:28 +0100，Krzysztof Kozlowski写道： > On 26/11/2025 10:41, Icenowy Zheng wrote: > > 在 2025-11-26星期三的 10:37 +0100，Krzysztof Kozlowski写道： > > > On 26/11/2025 09:57, Icenowy Zheng wrote: > > > > 在 2025-11-26星期三的 09:51 +0100，Krzysztof Kozlowski写道： > > > > > On Wed, Nov 26, 2025 at 12:52:26PM +0800, Icenowy Zheng > > > > > wrote: > > > > > > From: Icenowy Zheng <uwu@icenowy.me> > > > > > > > > > > > > Verisilicon has a series of display controllers prefixed > > > > > > with > > > > > > DC > > > > > > and > > > > > > with self-identification facility like their GC series > > > > > > GPUs. > > > > > > > > > > > > Add a device tree binding for it. > > > > > > > > > > > > Depends on the specific DC model, it can have either one or > > > > > > two > > > > > > display > > > > > > outputs, and each display output could be set to DPI signal > > > > > > or > > > > > > "DP" > > > > > > signal (which seems to be some plain parallel bus to HDMI > > > > > > controllers). > > > > > > > > > > > > Signed-off-by: Icenowy Zheng <uwu@icenowy.me> > > > > > > Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn> > > > > > > --- > > > > > > > > > > You already received review on this. Don't send the same. > > > > > Read > > > > > the > > > > > review. > > > > > > > > Please see the sender (mail header From) of this time. > > > > > > This improved. I am speaking about the rest of review. > > > > Well this is why this is a v3 resend, not v4. > > > > I will address these issues in v4. > > You received review. Do not ever make a resend ignoring the review, > even > if only parts. Make a posting after addressing COMPLETE review. > > Otherwise this hides the original review and no one will ever find > it. > It also is quite disrespectful to my time spent on that review. Well okay, sorry because I didn't notice the review before... > > Best regards, > Krzysztof
© 2016 - 2025 Red Hat, Inc.