Add the RPMH clocks present in Kaanapali SoC.
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
---
drivers/clk/qcom/clk-rpmh.c | 41 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
index a2185a6f321fb60ddc9272582ed67fa9ada6535e..bb2cbd2961d9aa1e4475d5876c1761dbbffe5338 100644
--- a/drivers/clk/qcom/clk-rpmh.c
+++ b/drivers/clk/qcom/clk-rpmh.c
@@ -395,6 +395,18 @@ DEFINE_CLK_RPMH_VRM(clk4, _a1_e0, "C4A_E0", 1);
DEFINE_CLK_RPMH_VRM(clk5, _a1_e0, "C5A_E0", 1);
DEFINE_CLK_RPMH_VRM(clk8, _a1_e0, "C8A_E0", 1);
+DEFINE_CLK_RPMH_VRM(clk1, _a1_e0, "C1A_E0", 1);
+DEFINE_CLK_RPMH_VRM(clk2, _a1_e0, "C2A_E0", 1);
+
+DEFINE_CLK_RPMH_VRM(clk3, _a2_e0, "C3A_E0", 2);
+DEFINE_CLK_RPMH_VRM(clk4, _a2_e0, "C4A_E0", 2);
+DEFINE_CLK_RPMH_VRM(clk5, _a2_e0, "C5A_E0", 2);
+DEFINE_CLK_RPMH_VRM(clk6, _a2_e0, "C6A_E0", 2);
+DEFINE_CLK_RPMH_VRM(clk7, _a2_e0, "C7A_E0", 2);
+DEFINE_CLK_RPMH_VRM(clk8, _a2_e0, "C8A_E0", 2);
+
+DEFINE_CLK_RPMH_VRM(clk11, _a4_e0, "C11A_E0", 4);
+
DEFINE_CLK_RPMH_BCM(ce, "CE0");
DEFINE_CLK_RPMH_BCM(hwkm, "HK0");
DEFINE_CLK_RPMH_BCM(ipa, "IP0");
@@ -901,6 +913,34 @@ static const struct clk_rpmh_desc clk_rpmh_glymur = {
.num_clks = ARRAY_SIZE(glymur_rpmh_clocks),
};
+static struct clk_hw *kaanapali_rpmh_clocks[] = {
+ [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
+ [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
+ [RPMH_DIV_CLK1] = &clk_rpmh_clk11_a4_e0.hw,
+ [RPMH_LN_BB_CLK1] = &clk_rpmh_clk6_a2_e0.hw,
+ [RPMH_LN_BB_CLK1_A] = &clk_rpmh_clk6_a2_e0_ao.hw,
+ [RPMH_LN_BB_CLK2] = &clk_rpmh_clk7_a2_e0.hw,
+ [RPMH_LN_BB_CLK2_A] = &clk_rpmh_clk7_a2_e0_ao.hw,
+ [RPMH_LN_BB_CLK3] = &clk_rpmh_clk8_a2_e0.hw,
+ [RPMH_LN_BB_CLK3_A] = &clk_rpmh_clk8_a2_e0_ao.hw,
+ [RPMH_RF_CLK1] = &clk_rpmh_clk1_a1_e0.hw,
+ [RPMH_RF_CLK1_A] = &clk_rpmh_clk1_a1_e0_ao.hw,
+ [RPMH_RF_CLK2] = &clk_rpmh_clk2_a1_e0.hw,
+ [RPMH_RF_CLK2_A] = &clk_rpmh_clk2_a1_e0_ao.hw,
+ [RPMH_RF_CLK3] = &clk_rpmh_clk3_a2_e0.hw,
+ [RPMH_RF_CLK3_A] = &clk_rpmh_clk3_a2_e0_ao.hw,
+ [RPMH_RF_CLK4] = &clk_rpmh_clk4_a2_e0.hw,
+ [RPMH_RF_CLK4] = &clk_rpmh_clk4_a2_e0_ao.hw,
+ [RPMH_RF_CLK5_A] = &clk_rpmh_clk5_a2_e0.hw,
+ [RPMH_RF_CLK5_A] = &clk_rpmh_clk5_a2_e0_ao.hw,
+ [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
+};
+
+static const struct clk_rpmh_desc clk_rpmh_kaanapali = {
+ .clks = kaanapali_rpmh_clocks,
+ .num_clks = ARRAY_SIZE(kaanapali_rpmh_clocks),
+};
+
static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
void *data)
{
@@ -991,6 +1031,7 @@ static int clk_rpmh_probe(struct platform_device *pdev)
static const struct of_device_id clk_rpmh_match_table[] = {
{ .compatible = "qcom,glymur-rpmh-clk", .data = &clk_rpmh_glymur},
+ { .compatible = "qcom,kaanapali-rpmh-clk", .data = &clk_rpmh_kaanapali},
{ .compatible = "qcom,milos-rpmh-clk", .data = &clk_rpmh_milos},
{ .compatible = "qcom,qcs615-rpmh-clk", .data = &clk_rpmh_qcs615},
{ .compatible = "qcom,qdu1000-rpmh-clk", .data = &clk_rpmh_qdu1000},
--
2.34.1