From: Jie Zhang <quic_jiezh@quicinc.com>
Add gpu and rgmu nodes for qcs615 chipset.
Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/talos.dtsi | 116 ++++++++++++++++++++++++++++++++++++
1 file changed, 116 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
index 743c840e496d..12d6b296b562 100644
--- a/arch/arm64/boot/dts/qcom/talos.dtsi
+++ b/arch/arm64/boot/dts/qcom/talos.dtsi
@@ -647,6 +647,11 @@ rproc_adsp_mem: rproc-adsp@95900000 {
reg = <0x0 0x95900000 0x0 0x1e00000>;
no-map;
};
+
+ pil_gpu_mem: pil-gpu@97715000 {
+ reg = <0x0 0x97715000 0x0 0x2000>;
+ no-map;
+ };
};
soc: soc@0 {
@@ -1826,6 +1831,117 @@ data-pins {
};
};
+ gpu: gpu@5000000 {
+ compatible = "qcom,adreno-612.0", "qcom,adreno";
+ reg = <0x0 0x05000000 0x0 0x90000>,
+ <0x0 0x0509e000 0x0 0x1000>,
+ <0x0 0x05061000 0x0 0x800>;
+ reg-names = "kgsl_3d0_reg_memory",
+ "cx_mem",
+ "cx_dbgc";
+
+ clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>;
+ clock-names = "core";
+
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+ interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "gfx-mem";
+
+ iommus = <&adreno_smmu 0x0 0x401>;
+
+ operating-points-v2 = <&gpu_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
+
+ qcom,gmu = <&gmu>;
+
+ #cooling-cells = <2>;
+
+ status = "disabled";
+
+ gpu_zap_shader: zap-shader {
+ memory-region = <&pil_gpu_mem>;
+ };
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-845000000 {
+ opp-hz = /bits/ 64 <845000000>;
+ required-opps = <&rpmhpd_opp_turbo>;
+ opp-peak-kBps = <7050000>;
+ };
+
+ opp-745000000 {
+ opp-hz = /bits/ 64 <745000000>;
+ required-opps = <&rpmhpd_opp_nom_l1>;
+ opp-peak-kBps = <6075000>;
+ };
+
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <5287500>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ opp-peak-kBps = <3975000>;
+ };
+
+ opp-435000000 {
+ opp-hz = /bits/ 64 <435000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ opp-peak-kBps = <3000000>;
+ };
+
+ opp-290000000 {
+ opp-hz = /bits/ 64 <290000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <1762500>;
+ };
+ };
+ };
+
+ gmu: gmu@506a000 {
+ compatible = "qcom,adreno-rgmu-612.0", "qcom,adreno-rgmu";
+ reg = <0x0 0x0506a000 0x0 0x34000>;
+
+ clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
+ clock-names = "gmu",
+ "cxo",
+ "axi",
+ "memnoc",
+ "smmu_vote";
+
+ power-domains = <&gpucc CX_GDSC>,
+ <&gpucc GX_GDSC>;
+ power-domain-names = "cx",
+ "gx";
+
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "oob",
+ "gmu";
+
+ operating-points-v2 = <&gmu_opp_table>;
+
+ gmu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+ };
+ };
+
gpucc: clock-controller@5090000 {
compatible = "qcom,qcs615-gpucc";
reg = <0 0x05090000 0 0x9000>;
--
2.51.0On 11/21/25 10:52 PM, Akhil P Oommen wrote:
> From: Jie Zhang <quic_jiezh@quicinc.com>
>
> Add gpu and rgmu nodes for qcs615 chipset.
>
> Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com>
> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> ---
[...]
> + gpu_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-845000000 {
> + opp-hz = /bits/ 64 <845000000>;
> + required-opps = <&rpmhpd_opp_turbo>;
> + opp-peak-kBps = <7050000>;
> + };
I see another speed of 895 @ turbo_l1, perhaps that's for speedbins
or mobile parts specifically?
[...]
> +
> + opp-745000000 {
> + opp-hz = /bits/ 64 <745000000>;
> + required-opps = <&rpmhpd_opp_nom_l1>;
> + opp-peak-kBps = <6075000>;
> + };
> +
> + opp-650000000 {
> + opp-hz = /bits/ 64 <650000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + opp-peak-kBps = <5287500>;
> + };
Here the freq map says 700 MHz
> + opp-500000000 {
> + opp-hz = /bits/ 64 <500000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + opp-peak-kBps = <3975000>;
> + };
550
Konrad
On Sat, Nov 22, 2025 at 03:03:10PM +0100, Konrad Dybcio wrote:
> On 11/21/25 10:52 PM, Akhil P Oommen wrote:
> > From: Jie Zhang <quic_jiezh@quicinc.com>
> >
> > Add gpu and rgmu nodes for qcs615 chipset.
> >
> > Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com>
> > Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> > ---
>
> [...]
>
> > + gpu_opp_table: opp-table {
> > + compatible = "operating-points-v2";
> > +
> > + opp-845000000 {
> > + opp-hz = /bits/ 64 <845000000>;
> > + required-opps = <&rpmhpd_opp_turbo>;
> > + opp-peak-kBps = <7050000>;
> > + };
>
> I see another speed of 895 @ turbo_l1, perhaps that's for speedbins
> or mobile parts specifically?
msm-4.14 defines 7 speedbins for SM6150. Akhil, I don't see any of them
here.
>
> [...]
>
> > +
> > + opp-745000000 {
> > + opp-hz = /bits/ 64 <745000000>;
> > + required-opps = <&rpmhpd_opp_nom_l1>;
> > + opp-peak-kBps = <6075000>;
> > + };
> > +
> > + opp-650000000 {
> > + opp-hz = /bits/ 64 <650000000>;
> > + required-opps = <&rpmhpd_opp_nom>;
> > + opp-peak-kBps = <5287500>;
> > + };
>
> Here the freq map says 700 MHz
>
> > + opp-500000000 {
> > + opp-hz = /bits/ 64 <500000000>;
> > + required-opps = <&rpmhpd_opp_svs_l1>;
> > + opp-peak-kBps = <3975000>;
> > + };
>
> 550
>
> Konrad
--
With best wishes
Dmitry
On Sat, Nov 22, 2025 at 03:22:19AM +0530, Akhil P Oommen wrote: > From: Jie Zhang <quic_jiezh@quicinc.com> > > Add gpu and rgmu nodes for qcs615 chipset. > > Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com> > Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> > --- > arch/arm64/boot/dts/qcom/talos.dtsi | 116 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 116 insertions(+) > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> -- With best wishes Dmitry
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