Some GPUs like A612 doesn't use a named register range resource. This
is because the reg-name property is discouraged when there is just a
single resource.
To address this, retrieve the 'gmu' register range by its index. It is
always guaranteed to be at index 0.
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 5903cd891b49..9662201cd2e9 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -2029,21 +2029,19 @@ static int cxpd_notifier_cb(struct notifier_block *nb,
return 0;
}
-static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
- const char *name, resource_size_t *start)
+static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, resource_size_t *start)
{
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
void __iomem *ret;
- struct resource *res = platform_get_resource_byname(pdev,
- IORESOURCE_MEM, name);
if (!res) {
- DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name);
+ DRM_DEV_ERROR(&pdev->dev, "Unable to find the gmu core registers\n");
return ERR_PTR(-EINVAL);
}
ret = ioremap(res->start, resource_size(res));
if (!ret) {
- DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name);
+ DRM_DEV_ERROR(&pdev->dev, "Unable to map the gmu core registers\n");
return ERR_PTR(-EINVAL);
}
@@ -2085,7 +2083,7 @@ int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
gmu->nr_clocks = ret;
/* Map the GMU registers */
- gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu", &start);
+ gmu->mmio = a6xx_gmu_get_mmio(pdev, &start);
if (IS_ERR(gmu->mmio)) {
ret = PTR_ERR(gmu->mmio);
goto err_mmio;
@@ -2244,7 +2242,7 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
goto err_memory;
/* Map the GMU registers */
- gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu", &start);
+ gmu->mmio = a6xx_gmu_get_mmio(pdev, &start);
if (IS_ERR(gmu->mmio)) {
ret = PTR_ERR(gmu->mmio);
goto err_memory;
--
2.51.0On 11/21/25 10:52 PM, Akhil P Oommen wrote: > Some GPUs like A612 doesn't use a named register range resource. This > is because the reg-name property is discouraged when there is just a > single resource. > > To address this, retrieve the 'gmu' register range by its index. It is > always guaranteed to be at index 0. > > Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> > --- > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 14 ++++++-------- > 1 file changed, 6 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > index 5903cd891b49..9662201cd2e9 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > @@ -2029,21 +2029,19 @@ static int cxpd_notifier_cb(struct notifier_block *nb, > return 0; > } > > -static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, > - const char *name, resource_size_t *start) > +static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, resource_size_t *start) Can we drop this and just use devm_platform_get_and_ioremap_resource()? Konrad
On 11/22/2025 7:08 PM, Konrad Dybcio wrote: > On 11/21/25 10:52 PM, Akhil P Oommen wrote: >> Some GPUs like A612 doesn't use a named register range resource. This >> is because the reg-name property is discouraged when there is just a >> single resource. >> >> To address this, retrieve the 'gmu' register range by its index. It is >> always guaranteed to be at index 0. >> >> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> >> --- >> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 14 ++++++-------- >> 1 file changed, 6 insertions(+), 8 deletions(-) >> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >> index 5903cd891b49..9662201cd2e9 100644 >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >> @@ -2029,21 +2029,19 @@ static int cxpd_notifier_cb(struct notifier_block *nb, >> return 0; >> } >> >> -static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, >> - const char *name, resource_size_t *start) >> +static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, resource_size_t *start) > > Can we drop this and just use devm_platform_get_and_ioremap_resource()? This API seems to lock the io region and fails with -EBUSY if the region is already in use. I am worried it may regress other chipsets. So, I dropped this idea at the last moment. -Akhil > > Konrad
On 12/4/25 2:10 PM, Akhil P Oommen wrote: > On 11/22/2025 7:08 PM, Konrad Dybcio wrote: >> On 11/21/25 10:52 PM, Akhil P Oommen wrote: >>> Some GPUs like A612 doesn't use a named register range resource. This >>> is because the reg-name property is discouraged when there is just a >>> single resource. >>> >>> To address this, retrieve the 'gmu' register range by its index. It is >>> always guaranteed to be at index 0. >>> >>> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> >>> --- >>> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 14 ++++++-------- >>> 1 file changed, 6 insertions(+), 8 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >>> index 5903cd891b49..9662201cd2e9 100644 >>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >>> @@ -2029,21 +2029,19 @@ static int cxpd_notifier_cb(struct notifier_block *nb, >>> return 0; >>> } >>> >>> -static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, >>> - const char *name, resource_size_t *start) >>> +static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, resource_size_t *start) >> >> Can we drop this and just use devm_platform_get_and_ioremap_resource()? > > This API seems to lock the io region and fails with -EBUSY if the region > is already in use. I am worried it may regress other chipsets. So, I > dropped this idea at the last moment. Is there any specific platform where this would be an issue? Konrad
On Thu, Dec 4, 2025 at 5:30 AM Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> wrote: > > On 12/4/25 2:10 PM, Akhil P Oommen wrote: > > On 11/22/2025 7:08 PM, Konrad Dybcio wrote: > >> On 11/21/25 10:52 PM, Akhil P Oommen wrote: > >>> Some GPUs like A612 doesn't use a named register range resource. This > >>> is because the reg-name property is discouraged when there is just a > >>> single resource. > >>> > >>> To address this, retrieve the 'gmu' register range by its index. It is > >>> always guaranteed to be at index 0. > >>> > >>> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> > >>> --- > >>> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 14 ++++++-------- > >>> 1 file changed, 6 insertions(+), 8 deletions(-) > >>> > >>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > >>> index 5903cd891b49..9662201cd2e9 100644 > >>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > >>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > >>> @@ -2029,21 +2029,19 @@ static int cxpd_notifier_cb(struct notifier_block *nb, > >>> return 0; > >>> } > >>> > >>> -static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, > >>> - const char *name, resource_size_t *start) > >>> +static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, resource_size_t *start) > >> > >> Can we drop this and just use devm_platform_get_and_ioremap_resource()? > > > > This API seems to lock the io region and fails with -EBUSY if the region > > is already in use. I am worried it may regress other chipsets. So, I > > dropped this idea at the last moment. > > Is there any specific platform where this would be an issue? IIRC we've had this problem before and ended up reverting a similar change, due to gpucc and gpu overlap BR, -R
On 12/4/25 3:34 PM, Rob Clark wrote: > On Thu, Dec 4, 2025 at 5:30 AM Konrad Dybcio > <konrad.dybcio@oss.qualcomm.com> wrote: >> >> On 12/4/25 2:10 PM, Akhil P Oommen wrote: >>> On 11/22/2025 7:08 PM, Konrad Dybcio wrote: >>>> On 11/21/25 10:52 PM, Akhil P Oommen wrote: >>>>> Some GPUs like A612 doesn't use a named register range resource. This >>>>> is because the reg-name property is discouraged when there is just a >>>>> single resource. >>>>> >>>>> To address this, retrieve the 'gmu' register range by its index. It is >>>>> always guaranteed to be at index 0. >>>>> >>>>> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> >>>>> --- >>>>> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 14 ++++++-------- >>>>> 1 file changed, 6 insertions(+), 8 deletions(-) >>>>> >>>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >>>>> index 5903cd891b49..9662201cd2e9 100644 >>>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >>>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >>>>> @@ -2029,21 +2029,19 @@ static int cxpd_notifier_cb(struct notifier_block *nb, >>>>> return 0; >>>>> } >>>>> >>>>> -static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, >>>>> - const char *name, resource_size_t *start) >>>>> +static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, resource_size_t *start) >>>> >>>> Can we drop this and just use devm_platform_get_and_ioremap_resource()? >>> >>> This API seems to lock the io region and fails with -EBUSY if the region >>> is already in use. I am worried it may regress other chipsets. So, I >>> dropped this idea at the last moment. >> >> Is there any specific platform where this would be an issue? > > IIRC we've had this problem before and ended up reverting a similar > change, due to gpucc and gpu overlap Argh, sm8350.dtsi for example seems to be affected.. Hopefully one day we can fix that.. Konrad
On 11/22/2025 7:08 PM, Konrad Dybcio wrote: > On 11/21/25 10:52 PM, Akhil P Oommen wrote: >> Some GPUs like A612 doesn't use a named register range resource. This >> is because the reg-name property is discouraged when there is just a >> single resource. >> >> To address this, retrieve the 'gmu' register range by its index. It is >> always guaranteed to be at index 0. >> >> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> >> --- >> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 14 ++++++-------- >> 1 file changed, 6 insertions(+), 8 deletions(-) >> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >> index 5903cd891b49..9662201cd2e9 100644 >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >> @@ -2029,21 +2029,19 @@ static int cxpd_notifier_cb(struct notifier_block *nb, >> return 0; >> } >> >> -static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, >> - const char *name, resource_size_t *start) >> +static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, resource_size_t *start) > > Can we drop this and just use devm_platform_get_and_ioremap_resource()? That's better. Nice. -Akhil. > > Konrad
On Sat, Nov 22, 2025 at 03:22:15AM +0530, Akhil P Oommen wrote: > Some GPUs like A612 doesn't use a named register range resource. This > is because the reg-name property is discouraged when there is just a > single resource. > > To address this, retrieve the 'gmu' register range by its index. It is > always guaranteed to be at index 0. > > Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> > --- > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 14 ++++++-------- > 1 file changed, 6 insertions(+), 8 deletions(-) > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> -- With best wishes Dmitry
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