riscv: hwprobe: expose vector register length in bytes

[PATCH] riscv: hwprobe: expose vector register length in bytes

Posted by Sergey Matyukevich 2 months, 2 weeks ago

The vector register length can be obtained from the read-only CSR vlenb.
However reading this CSR may be undesirable in some cases. XTheadVector
extension is one example: existing implementations may not provide this
register. On such platforms, vlenb is specified as device-tree property.
Reading vlenb also initializes the application’s vector context, even
though the application may decide not to use the vector extension based
on the reported length.

Meanwhile the kernel already determines vlenb at boot, either from the
CSR or from the device tree. So add RISCV_HWPROBE_KEY_VECTOR_REG_LENGTH
to expose the vector register length already known to the kernel.

Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com>
---
 Documentation/arch/riscv/hwprobe.rst  | 3 +++
 arch/riscv/include/asm/hwprobe.h      | 2 +-
 arch/riscv/include/uapi/asm/hwprobe.h | 1 +
 arch/riscv/kernel/sys_hwprobe.c       | 6 ++++++
 4 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index 06c5280b728a..14437fe79276 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -379,3 +379,6 @@ The following keys are defined:
 
 * :c:macro:`RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE`: An unsigned int which
   represents the size of the Zicbop block in bytes.
+
+* :c:macro:`RISCV_HWPROBE_KEY_VECTOR_REG_LENGTH`: An unsigned int which
+  represents the vector registers length in bytes.
diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h
index 8c572a464719..b10311c9a44c 100644
--- a/arch/riscv/include/asm/hwprobe.h
+++ b/arch/riscv/include/asm/hwprobe.h
@@ -8,7 +8,7 @@
 
 #include <uapi/asm/hwprobe.h>
 
-#define RISCV_HWPROBE_MAX_KEY 15
+#define RISCV_HWPROBE_MAX_KEY 16
 
 static inline bool riscv_hwprobe_key_is_valid(__s64 key)
 {
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 1edea2331b8b..bd6cd97c81f9 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -110,6 +110,7 @@ struct riscv_hwprobe {
 #define RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0	13
 #define RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0	14
 #define RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE	15
+#define RISCV_HWPROBE_KEY_VECTOR_REG_LENGTH	16
 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
 
 /* Flags */
diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index 0f701ace3bb9..3007432fbdf1 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -328,6 +328,12 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
 		hwprobe_isa_vendor_ext_mips_0(pair, cpus);
 		break;
 
+	case RISCV_HWPROBE_KEY_VECTOR_REG_LENGTH:
+		pair->value = 0;
+		if (has_vector() || has_xtheadvector())
+			pair->value = riscv_v_vsize / 32;
+		break;
+
 	/*
 	 * For forward compatibility, unknown keys don't fail the whole
 	 * call, but get their element key set to -1 and value set to 0
-- 
2.51.2

Re: [PATCH] riscv: hwprobe: expose vector register length in bytes

Posted by Andy Chiu 2 months ago

Hi Sergey,

On Fri, Nov 21, 2025 at 1:37 PM Sergey Matyukevich <geomatsi@gmail.com> wrote:
>
> The vector register length can be obtained from the read-only CSR vlenb.
> However reading this CSR may be undesirable in some cases. XTheadVector
> extension is one example: existing implementations may not provide this
> register. On such platforms, vlenb is specified as device-tree property.

I wonder why a hwprobe entry is needed even in this context. If vlenb
is not available, we can always use a vsetvli and read the destination
register to infer register length. Isn't that also true for Vector
0.7, or are you considering anything else?

> Reading vlenb also initializes the application’s vector context, even
> though the application may decide not to use the vector extension based
> on the reported length.
>
> Meanwhile the kernel already determines vlenb at boot, either from the
> CSR or from the device tree. So add RISCV_HWPROBE_KEY_VECTOR_REG_LENGTH
> to expose the vector register length already known to the kernel.
>
> Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com>
> ---
>  Documentation/arch/riscv/hwprobe.rst  | 3 +++
>  arch/riscv/include/asm/hwprobe.h      | 2 +-
>  arch/riscv/include/uapi/asm/hwprobe.h | 1 +
>  arch/riscv/kernel/sys_hwprobe.c       | 6 ++++++
>  4 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> index 06c5280b728a..14437fe79276 100644
> --- a/Documentation/arch/riscv/hwprobe.rst
> +++ b/Documentation/arch/riscv/hwprobe.rst
> @@ -379,3 +379,6 @@ The following keys are defined:
>
>  * :c:macro:`RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE`: An unsigned int which
>    represents the size of the Zicbop block in bytes.
> +
> +* :c:macro:`RISCV_HWPROBE_KEY_VECTOR_REG_LENGTH`: An unsigned int which
> +  represents the vector registers length in bytes.
> diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h
> index 8c572a464719..b10311c9a44c 100644
> --- a/arch/riscv/include/asm/hwprobe.h
> +++ b/arch/riscv/include/asm/hwprobe.h
> @@ -8,7 +8,7 @@
>
>  #include <uapi/asm/hwprobe.h>
>
> -#define RISCV_HWPROBE_MAX_KEY 15
> +#define RISCV_HWPROBE_MAX_KEY 16
>
>  static inline bool riscv_hwprobe_key_is_valid(__s64 key)
>  {
> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> index 1edea2331b8b..bd6cd97c81f9 100644
> --- a/arch/riscv/include/uapi/asm/hwprobe.h
> +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> @@ -110,6 +110,7 @@ struct riscv_hwprobe {
>  #define RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0  13
>  #define RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0    14
>  #define RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE    15
> +#define RISCV_HWPROBE_KEY_VECTOR_REG_LENGTH    16
>  /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
>
>  /* Flags */
> diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> index 0f701ace3bb9..3007432fbdf1 100644
> --- a/arch/riscv/kernel/sys_hwprobe.c
> +++ b/arch/riscv/kernel/sys_hwprobe.c
> @@ -328,6 +328,12 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
>                 hwprobe_isa_vendor_ext_mips_0(pair, cpus);
>                 break;
>
> +       case RISCV_HWPROBE_KEY_VECTOR_REG_LENGTH:
> +               pair->value = 0;
> +               if (has_vector() || has_xtheadvector())
> +                       pair->value = riscv_v_vsize / 32;
> +               break;
> +
>         /*
>          * For forward compatibility, unknown keys don't fail the whole
>          * call, but get their element key set to -1 and value set to 0
> --
> 2.51.2
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Thanks,
Andy

Re: [PATCH] riscv: hwprobe: expose vector register length in bytes

Posted by Sergey Matyukevich 2 months ago

Hi Andy

On Wed, Dec 03, 2025 at 11:57:06AM -0600, Andy Chiu wrote:
> Hi Sergey,
> 
> On Fri, Nov 21, 2025 at 1:37 PM Sergey Matyukevich <geomatsi@gmail.com> wrote:
> >
> > The vector register length can be obtained from the read-only CSR vlenb.
> > However reading this CSR may be undesirable in some cases. XTheadVector
> > extension is one example: existing implementations may not provide this
> > register. On such platforms, vlenb is specified as device-tree property.
> 
> I wonder why a hwprobe entry is needed even in this context. If vlenb
> is not available, we can always use a vsetvli and read the destination
> register to infer register length. Isn't that also true for Vector
> 0.7, or are you considering anything else?

Sure, reading vsetvli works for XTheadVector as well. The primary reason
for the new hwprobe key is convenience. Vector 1.0 and XTheadVector have
some differences that complicate that sort of autodetection. For instance,
an older encoding for vsetvli. Good examples are vstate save and restore
functions in `arch/riscv/include/asm/vector.h`. Using hwprobe seems more
convenient than using vector-or-xtheadvector logic with custom opcods,
especially since the kernel already has all the necessary information.

> > Reading vlenb also initializes the application’s vector context, even
> > though the application may decide not to use the vector extension based
> > on the reported length.
> >
> > Meanwhile the kernel already determines vlenb at boot, either from the
> > CSR or from the device tree. So add RISCV_HWPROBE_KEY_VECTOR_REG_LENGTH
> > to expose the vector register length already known to the kernel.
> >
> > Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com>
> > ---
> >  Documentation/arch/riscv/hwprobe.rst  | 3 +++
> >  arch/riscv/include/asm/hwprobe.h      | 2 +-
> >  arch/riscv/include/uapi/asm/hwprobe.h | 1 +
> >  arch/riscv/kernel/sys_hwprobe.c       | 6 ++++++
> >  4 files changed, 11 insertions(+), 1 deletion(-)

[snip]...

> Thanks,
> Andy

Regards,
Sergey