Enable the cmu_dpu clock management unit. It feeds some of the display
IPs. Additionally add the sysreg_dpu node which contains the
BUSCOMPONENT_DRCG_EN and MEMCLK registers required by cmu_dpu to enable
dynamic root clock gating of bus components.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index c39ca4c4508f046ca16ae86be42468c7245561b8..ac326db437fa8fe437cf11167bd8c1ce5c2ec186 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -1798,6 +1798,23 @@ pinctrl_gsacore: pinctrl@17a80000 {
status = "disabled";
};
+ cmu_dpu: clock-controller@1c000000 {
+ compatible = "google,gs101-cmu-dpu";
+ reg = <0x1c000000 0x10000>;
+ #clock-cells = <1>;
+
+ clocks = <&ext_24_5m>,
+ <&cmu_top CLK_DOUT_CMU_DPU_BUS>;
+ clock-names = "oscclk", "bus";
+ samsung,sysreg = <&sysreg_dpu>;
+ };
+
+ sysreg_dpu: syscon@1c020000 {
+ compatible = "google,gs101-dpu-sysreg", "syscon";
+ reg = <0x1c020000 0x10000>;
+ clocks = <&cmu_dpu CLK_GOUT_DPU_SYSREG_DPU_PCLK>;
+ };
+
cmu_top: clock-controller@1e080000 {
compatible = "google,gs101-cmu-top";
reg = <0x1e080000 0x10000>;
--
2.52.0.rc2.455.g230fcf2819-goog