riscv: dts: allwinner: d1: fix vlenb property

[PATCH] riscv: dts: allwinner: d1: fix vlenb property

Posted by Sergey Matyukevich 1 week, 5 days ago

According to [1], the C906 vector registers are 128 bits wide.
The 'thead,vlenb' property specifies the vector register length
in bytes, so its value must be set to 16.

[1] https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf

Fixes: ce1daeeba600 ("riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree")
Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com>
---
 arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
index 6367112e614a..a7442a508433 100644
--- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
@@ -28,7 +28,7 @@ cpu0: cpu@0 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
 					       "zifencei", "zihpm", "xtheadvector";
-			thead,vlenb = <128>;
+			thead,vlenb = <16>;
 			#cooling-cells = <2>;
 
 			cpu0_intc: interrupt-controller {
-- 
2.51.2

Re: [PATCH] riscv: dts: allwinner: d1: fix vlenb property

Posted by Chen-Yu Tsai 1 week, 3 days ago

On Wed, 19 Nov 2025 23:35:06 +0300, Sergey Matyukevich wrote:
> According to [1], the C906 vector registers are 128 bits wide.
> The 'thead,vlenb' property specifies the vector register length
> in bytes, so its value must be set to 16.
> 
> [1] https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf
> 
> 
> [...]

Applied to sunxi/fixes-for-6.18 in local tree, thanks!

[1/1] riscv: dts: allwinner: d1: fix vlenb property
      commit: 9f393d8e757f79060baf4b2e703bd6b2d0d8d323

Best regards,
-- 
Chen-Yu Tsai <wens@kernel.org>

Re: [PATCH] riscv: dts: allwinner: d1: fix vlenb property

Posted by Chen-Yu Tsai 1 week, 3 days ago

On Wed, 19 Nov 2025 23:35:06 +0300, Sergey Matyukevich wrote:
> According to [1], the C906 vector registers are 128 bits wide.
> The 'thead,vlenb' property specifies the vector register length
> in bytes, so its value must be set to 16.
> 
> [1] https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf
> 
> 
> [...]

Applied to sunxi/fixes-for-6.18 in local tree, thanks!

[1/1] riscv: dts: allwinner: d1: fix vlenb property
      commit: 57c5543b94d0c0280145a4a7445a2c1ae074879e

Best regards,
-- 
Chen-Yu Tsai <wens@kernel.org>