From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
The Renesas RZ/G3S features a PCIe IP that complies with the PCI Express
Base Specification 4.0 and supports speeds of up to 5 GT/s. It functions
only as a root complex, with a single-lane (x1) configuration. The
controller includes Type 1 configuration registers, as well as IP
specific registers (called AXI registers) required for various adjustments.
Hardware manual can be downloaded from the address in the "Link" section.
The following steps should be followed to access the manual:
1/ Click the "User Manual" button
2/ Click "Confirm"; this will start downloading an archive
3/ Open the downloaded archive
4/ Navigate to r01uh1014ej*-rzg3s-users-manual-hardware -> Deliverables
5/ Open the file r01uh1014ej*-rzg3s.pdf
Link: https://www.renesas.com/en/products/rz-g3s?queryID=695cc067c2d89e3f271d43656ede4d12
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v8:
- in struct rzg3s_pcie_host: moved "struct rzg3s_pcie_port port" near
"struct rzg3s_pcie_msi msi" to avoid any padding, if any
- in rzg3s_pcie_root_write(): propagate the return value of
pci_generic_config_write()
- in rzg3s_pcie_init_msi(): use msi->irq instead of irq in the debug
message
- in rzg3s_pcie_set_max_link_speed(): s/lcs/ls/g to reflect the name
of the read register
- in rzg3s_pcie_host_setup(): s/doamin/domain
Changes in v7:
- rebased on top of v6.18-rc1
Changes in v6:
- split the help message from Kconfig to 80 chars
- dropped unused defines
- dropped dot at the end of short comments
- re-arranged the members of rzg3s_pcie_child_prepare_bus(),
rzg3s_pcie_child_read_conf(), rzg3s_pcie_child_write_conf(),
rzg3s_pcie_root_map_bus() to save few lines
- in rzg3s_pcie_irq_compose_msi_msg() drop drop_mask and use
RZG3S_PCI_MSIRCVWADRL_MASK
- merge INTx and MSI configuration in rzg3s_pcie_init_irqdomain(); with it,
rzg3s_pcie_host_setup() takes now only 2 function pointer for IRQ domain
config and teardown; also, updated the names of other functions to match
the most used pattern accross other drivers:
-- rzg3s_pcie_msi_enable() -> rzg3s_pcie_init_msi()
-- rzg3s_pcie_host_parse_root_port() -> rzg3s_pcie_host_parse_port()
-- rzg3s_pcie_host_init_root_port() -> rzg3s_pcie_host_init_port()
- used dev_fwnode() instead of of_fwnode_handle()
- used fsleep() instead of usleep_range()
- pass "size - 1" to rzg3s_pcie_set_inbound_window() only and keep the
undecremented value in the calling function
- added a comment on top of request_irq() to explain why devm_ variant
was not used
Changes in v5:
- replaced devm action or resets with gotos
- s/writeb/writeb_relaxed/g
- s/readw/readw_relaxed/g
- s/readl/readl_relaxed/g
- s/writel/writel_relaxed/g
- dropped rzg3s_pcie_child_ops::map_bus, rename rzg3s_pcie_child_map_bus()
(that was used to instantiate rzg3s_pcie_child_ops::map_bus) to
rzg3s_pcie_child_prepare_bus() and used it directly in
rzg3s_pcie_child_read_conf() and rzg3s_pcie_child_write_conf()
- convert the 3rd argument of readl_poll_timeout() to microseconds
- set rzg3s_pcie_driver.driver.probe_type = PROBE_PREFER_ASYNCHRONOUS
Changes in v4:
- updated patch title
- drop the option to build the driver as module
- make it dependent on IRQ_MSI_LIB and adjust the code to use this library
- added code to parse and set PCIe port; moved device ID, vendor ID
setup under port configuration; added reference clock setup to the port
(which was missed previously); moved the PHY setup on port specific
setup function
- used of_pci_get_max_link_speed() to get the maximum available link speed
from device tree; with this updated the logic that set the max link speed
- simplified the logic in rzg3s_pcie_child_issue_request()
- set the type of access in rzg3s_pcie_child_write_conf/rzg3s_pcie_child_read_conf()
- added comment on rzg3s_pcie_root_write() about the used lock for serialization
- added RZG3S_PCI_MSIRCVWMSKL_MASK mask and use it properly to set the
MSI size
- fixed typos, dropped "link up" log on probe
- updated the error message on inbound/outbound window failure setup along
with the returning code
- used unsigned int type for the counter in for loops from
rzg3s_soc_pcie_init_phy()
- dropped unnecessary comments
- moved msleep(PCIE_RESET_CONFIG_WAIT_MS) in rzg3s_pcie_host_setup() to
allow resume path to also benefit of it
- drop the power reset de-assert from rzg3s_pcie_resets_prepare(), rename
rzg3s_pcie_resets_prepare() into rzg3s_pcie_resets_prepare_and_get()
to reflect that rzg3s_pcie_resets_prepare_and_get() only allocate memory
for resets and get them; the power resets are now de-asserted outside of
rzg3s_pcie_resets_prepare_and_get()
- add a comment for pm_runtime_resume_and_get() to reflect it is used
to power the clock domain the controller belongs to
Changes in v3:
- updated patch description with link to the hardware manual and steps
to access it
- included <linux/bitfields.h> to solve compilation errors
- used devm_mutex_init()
- used SZ_4K instead of 4096
- dropped PCIe register defines and used the ones from
include/uapi/linux/pci_regs.h; added RZG3S_PCI_CFG_PCIEC as the starting
offset of the capabilities to be used before the host bridge is
registered
- added blank lines around registers and bitfields defines
- kept the defines for bitfies in order (from MSB to LSB)
- dropped timeout defines (except RZG3S_REQ_ISSUE_TIMEOUT_US) and
used the ones from ../pci.h
- dropped rzg3s_pcie_link_speed and used defines from
include/uapi/linux/pci_regs.h
- in rzg3s_pcie_child_write() call directly rzg3s_pcie_child_write_conf()
if size is 4 and print the warning message on in the other cases
- return NULL in rzg3s_pcie_child_map_bus() and added a comment about it
- in rzg3s_pcie_root_write() and rzg3s_soc_pcie_init_phy() added a comment
about the setting done on RZG3S_PCI_PERM register
- register rzg3s_pcie_msi_free_domains(), rzg3s_pcie_msi_teardown(),
rzg3s_pcie_intx_teardown() as devm action or reset functions
- used irq_domain_create_linear() for intx domain
- added the rzg3s_pcie_power_resets_deassert() helper to de-assert the
power domain and wait before doing it
- wait PCIE_RESET_CONFIG_WAIT_MS before registering the host
- made rzg3s_soc_power_resets[] and rzg3s_soc_cfg_resets[] static
- added suppress_bind_attrs = true
- collected tags
Changes in v2:
- dropped the references to other RZ SoCs from patch description
- dropped the dot at the end of single line comments that are not a
sentence
- as a result of v2 rework removed unused macros and definitions
(e.g. RZG3S_PCI_REQISS_TR_TP1_RD, RZG3S_PCI_REQISS_TR_TP1_WR,
enum rzg3s_pcie_cfg_access_type)
- dropped driver specific defines that are for generic PCI
register offsets and used the generic ones
- updated the value of RZG3S_PCI_MSI_INT_NR as on RZ/G3S there
are no more than 32 MSIs (v1 value was due to mistake in the
HW manual)
- added timeout macros to be used by read_poll_timeout() specific
functions
- re-worked the reset handling part by using reset subsystem specific
functions only; with this the struct rzg3s_pcie_soc_data was
added; reference to PHY initialization function was added to this
structure as well
- dropped devres_group_id as the issue it tried to address will
now be fixed in platform bus code (v2 posted [2])
- use 80 columns alignment
- updated function name in the idea of using names similar to
what is used in other drivers
- added rzg3s_pcie_root_ops and rzg3s_pcie_child_ops and populate
bridge->ops, bridge->child_ops with it; from probe:
+ bridge->ops = &rzg3s_pcie_root_ops;
+ bridge->child_ops = &rzg3s_pcie_child_ops;
- print a warning for 32 bit accesses (based on the value of
bus->unsafe_warn as done in the common code)
- dropped dev_dbg() in read/write functions
- added HW manual revision identifier in comments that points to the
statements from manual
- reworked the rzg3s_pcie_intx_setup() as the legacy interrupt DT
node is not used anymore
- in rzg3s_pcie_config_init() do not hardcode anymore the
primary bus, secondary bus, subordinate bus but get this information
from device tree and update HW registers accordingly
- dropped rzg3s_pcie_remove() and added rzg3s_pcie_host_remove_action()
to be used as a devm action or reset function
- s/rzg3s_pcie_suspend/rzg3s_pcie_suspend_noirq,
s/rzg3s_pcie_resume/rzg3s_pcie_resume_noirq
- dropped DEFINE_NOIRQ_DEV_PM_OPS()
- updated driver name (rzg3s-pcie-host) to reflect it is for RZ/G3S
[2] https://lore.kernel.org/all/20250526122054.65532-2-claudiu.beznea.uj@bp.renesas.com
MAINTAINERS | 8 +
drivers/pci/controller/Kconfig | 9 +
drivers/pci/controller/Makefile | 1 +
drivers/pci/controller/pcie-rzg3s-host.c | 1759 ++++++++++++++++++++++
4 files changed, 1777 insertions(+)
create mode 100644 drivers/pci/controller/pcie-rzg3s-host.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 46126ce2f968..b177960aad7f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20007,6 +20007,14 @@ S: Maintained
F: drivers/pci/controller/dwc/pcie-qcom-common.c
F: drivers/pci/controller/dwc/pcie-qcom.c
+PCIE DRIVER FOR RENESAS RZ/G3S SERIES
+M: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
+L: linux-pci@vger.kernel.org
+L: linux-renesas-soc@vger.kernel.org
+S: Supported
+F: Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
+F: drivers/pci/controller/pcie-rzg3s-host.c
+
PCIE DRIVER FOR ROCKCHIP
M: Shawn Lin <shawn.lin@rock-chips.com>
L: linux-pci@vger.kernel.org
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 41748d083b93..8da33077b72a 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -266,6 +266,15 @@ config PCI_RCAR_GEN2
There are 3 internal PCI controllers available with a single
built-in EHCI/OHCI host controller present on each one.
+config PCIE_RENESAS_RZG3S_HOST
+ bool "Renesas RZ/G3S PCIe host controller"
+ depends on ARCH_RENESAS || COMPILE_TEST
+ select MFD_SYSCON
+ select IRQ_MSI_LIB
+ help
+ Say Y here if you want PCIe host controller support on Renesas RZ/G3S
+ SoC.
+
config PCIE_ROCKCHIP
bool
depends on PCI
diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
index 038ccbd9e3ba..229929a945c2 100644
--- a/drivers/pci/controller/Makefile
+++ b/drivers/pci/controller/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
obj-$(CONFIG_PCIE_RCAR_HOST) += pcie-rcar.o pcie-rcar-host.o
obj-$(CONFIG_PCIE_RCAR_EP) += pcie-rcar.o pcie-rcar-ep.o
+obj-$(CONFIG_PCIE_RENESAS_RZG3S_HOST) += pcie-rzg3s-host.o
obj-$(CONFIG_PCI_HOST_COMMON) += pci-host-common.o
obj-$(CONFIG_PCI_HOST_GENERIC) += pci-host-generic.o
obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c
new file mode 100644
index 000000000000..9e15db129d96
--- /dev/null
+++ b/drivers/pci/controller/pcie-rzg3s-host.c
@@ -0,0 +1,1759 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PCIe driver for Renesas RZ/G3S SoCs
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ *
+ * Based on:
+ * drivers/pci/controller/pcie-rcar-host.c
+ * Copyright (C) 2009 - 2011 Paul Mundt
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bitmap.h>
+#include <linux/bitops.h>
+#include <linux/cleanup.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/iopoll.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/irqchip/irq-msi-lib.h>
+#include <linux/irqdomain.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mutex.h>
+#include <linux/msi.h>
+#include <linux/of_irq.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/sizes.h>
+#include <linux/slab.h>
+#include <linux/units.h>
+
+#include "../pci.h"
+
+/* AXI registers */
+#define RZG3S_PCI_REQDATA(id) (0x80 + (id) * 0x4)
+#define RZG3S_PCI_REQRCVDAT 0x8c
+
+#define RZG3S_PCI_REQADR1 0x90
+#define RZG3S_PCI_REQADR1_BUS GENMASK(31, 24)
+#define RZG3S_PCI_REQADR1_DEV GENMASK(23, 19)
+#define RZG3S_PCI_REQADR1_FUNC GENMASK(18, 16)
+#define RZG3S_PCI_REQADR1_REG GENMASK(11, 0)
+
+#define RZG3S_PCI_REQBE 0x98
+#define RZG3S_PCI_REQBE_BYTE_EN GENMASK(3, 0)
+
+#define RZG3S_PCI_REQISS 0x9c
+#define RZG3S_PCI_REQISS_MOR_STATUS GENMASK(18, 16)
+#define RZG3S_PCI_REQISS_TR_TYPE GENMASK(11, 8)
+#define RZG3S_PCI_REQISS_TR_TP0_RD FIELD_PREP(RZG3S_PCI_REQISS_TR_TYPE, 0x4)
+#define RZG3S_PCI_REQISS_TR_TP0_WR FIELD_PREP(RZG3S_PCI_REQISS_TR_TYPE, 0x5)
+#define RZG3S_PCI_REQISS_TR_TP1_RD FIELD_PREP(RZG3S_PCI_REQISS_TR_TYPE, 0x6)
+#define RZG3S_PCI_REQISS_TR_TP1_WR FIELD_PREP(RZG3S_PCI_REQISS_TR_TYPE, 0x7)
+#define RZG3S_PCI_REQISS_REQ_ISSUE BIT(0)
+
+#define RZG3S_PCI_MSIRCVWADRL 0x100
+#define RZG3S_PCI_MSIRCVWADRL_MASK GENMASK(31, 3)
+#define RZG3S_PCI_MSIRCVWADRL_MSG_DATA_ENA BIT(1)
+#define RZG3S_PCI_MSIRCVWADRL_ENA BIT(0)
+
+#define RZG3S_PCI_MSIRCVWADRU 0x104
+
+#define RZG3S_PCI_MSIRCVWMSKL 0x108
+#define RZG3S_PCI_MSIRCVWMSKL_MASK GENMASK(31, 2)
+
+#define RZG3S_PCI_PINTRCVIE 0x110
+#define RZG3S_PCI_PINTRCVIE_INTX(i) BIT(i)
+#define RZG3S_PCI_PINTRCVIE_MSI BIT(4)
+
+#define RZG3S_PCI_PINTRCVIS 0x114
+#define RZG3S_PCI_PINTRCVIS_INTX(i) BIT(i)
+#define RZG3S_PCI_PINTRCVIS_MSI BIT(4)
+
+#define RZG3S_PCI_MSGRCVIE 0x120
+#define RZG3S_PCI_MSGRCVIE_MSG_RCV BIT(24)
+
+#define RZG3S_PCI_MSGRCVIS 0x124
+#define RZG3S_PCI_MSGRCVIS_MRI BIT(24)
+
+#define RZG3S_PCI_PEIE0 0x200
+
+#define RZG3S_PCI_PEIS0 0x204
+#define RZG3S_PCI_PEIS0_RX_DLLP_PM_ENTER BIT(12)
+#define RZG3S_PCI_PEIS0_DL_UPDOWN BIT(9)
+
+#define RZG3S_PCI_PEIE1 0x208
+#define RZG3S_PCI_PEIS1 0x20c
+#define RZG3S_PCI_AMEIS 0x214
+#define RZG3S_PCI_ASEIS1 0x224
+
+#define RZG3S_PCI_PCSTAT1 0x408
+#define RZG3S_PCI_PCSTAT1_LTSSM_STATE GENMASK(14, 10)
+#define RZG3S_PCI_PCSTAT1_DL_DOWN_STS BIT(0)
+
+#define RZG3S_PCI_PCCTRL2 0x410
+#define RZG3S_PCI_PCCTRL2_LS_CHG GENMASK(9, 8)
+#define RZG3S_PCI_PCCTRL2_LS_CHG_REQ BIT(0)
+
+#define RZG3S_PCI_PCSTAT2 0x414
+#define RZG3S_PCI_PCSTAT2_LS_CHG_DONE BIT(28)
+#define RZG3S_PCI_PCSTAT2_SDRIRE GENMASK(7, 1)
+
+#define RZG3S_PCI_PERM 0x300
+#define RZG3S_PCI_PERM_CFG_HWINIT_EN BIT(2)
+#define RZG3S_PCI_PERM_PIPE_PHY_REG_EN BIT(1)
+
+#define RZG3S_PCI_MSIRE(id) (0x600 + (id) * 0x10)
+#define RZG3S_PCI_MSIRE_ENA BIT(0)
+
+#define RZG3S_PCI_MSIRM(id) (0x608 + (id) * 0x10)
+#define RZG3S_PCI_MSIRS(id) (0x60c + (id) * 0x10)
+
+#define RZG3S_PCI_AWBASEL(id) (0x1000 + (id) * 0x20)
+#define RZG3S_PCI_AWBASEL_WIN_ENA BIT(0)
+
+#define RZG3S_PCI_AWBASEU(id) (0x1004 + (id) * 0x20)
+#define RZG3S_PCI_AWMASKL(id) (0x1008 + (id) * 0x20)
+#define RZG3S_PCI_AWMASKU(id) (0x100c + (id) * 0x20)
+#define RZG3S_PCI_ADESTL(id) (0x1010 + (id) * 0x20)
+#define RZG3S_PCI_ADESTU(id) (0x1014 + (id) * 0x20)
+
+#define RZG3S_PCI_PWBASEL(id) (0x1100 + (id) * 0x20)
+#define RZG3S_PCI_PWBASEL_ENA BIT(0)
+
+#define RZG3S_PCI_PWBASEU(id) (0x1104 + (id) * 0x20)
+#define RZG3S_PCI_PDESTL(id) (0x1110 + (id) * 0x20)
+#define RZG3S_PCI_PDESTU(id) (0x1114 + (id) * 0x20)
+#define RZG3S_PCI_PWMASKL(id) (0x1108 + (id) * 0x20)
+#define RZG3S_PCI_PWMASKU(id) (0x110c + (id) * 0x20)
+
+/* PHY control registers */
+#define RZG3S_PCI_PHY_XCFGD(id) (0x2000 + (id) * 0x10)
+#define RZG3S_PCI_PHY_XCFGD_NUM 39
+
+#define RZG3S_PCI_PHY_XCFGA_CMN(id) (0x2400 + (id) * 0x10)
+#define RZG3S_PCI_PHY_XCFGA_CMN_NUM 16
+
+#define RZG3S_PCI_PHY_XCFGA_RX(id) (0x2500 + (id) * 0x10)
+#define RZG3S_PCI_PHY_XCFGA_RX_NUM 13
+
+#define RZG3S_PCI_PHY_XCFGA_TX 0x25d0
+
+#define RZG3S_PCI_PHY_XCFG_CTRL 0x2a20
+#define RZG3S_PCI_PHY_XCFG_CTRL_PHYREG_SEL BIT(0)
+
+/* PCIe registers */
+#define RZG3S_PCI_CFG_BASE 0x6000
+#define RZG3S_PCI_CFG_BARMSK00L 0xa0
+#define RZG3S_PCI_CFG_BARMSK00U 0xa4
+
+#define RZG3S_PCI_CFG_PCIEC 0x60
+
+/* System controller registers */
+#define RZG3S_SYS_PCIE_RST_RSM_B 0xd74
+#define RZG3S_SYS_PCIE_RST_RSM_B_MASK BIT(0)
+
+/* Maximum number of windows */
+#define RZG3S_MAX_WINDOWS 8
+
+/* Number of MSI interrupts per register */
+#define RZG3S_PCI_MSI_INT_PER_REG 32
+/* The number of MSI interrupts */
+#define RZG3S_PCI_MSI_INT_NR RZG3S_PCI_MSI_INT_PER_REG
+
+/* Timeouts experimentally determined */
+#define RZG3S_REQ_ISSUE_TIMEOUT_US 2500
+
+/**
+ * struct rzg3s_pcie_msi - RZ/G3S PCIe MSI data structure
+ * @domain: IRQ domain
+ * @map: bitmap with the allocated MSIs
+ * @dma_addr: address of the allocated MSI window
+ * @window_base: base address of the MSI window
+ * @pages: allocated pages for MSI window mapping
+ * @map_lock: lock for bitmap with the allocated MSIs
+ * @irq: MSI interrupt
+ */
+struct rzg3s_pcie_msi {
+ struct irq_domain *domain;
+ DECLARE_BITMAP(map, RZG3S_PCI_MSI_INT_NR);
+ dma_addr_t dma_addr;
+ dma_addr_t window_base;
+ unsigned long pages;
+ struct mutex map_lock;
+ int irq;
+};
+
+struct rzg3s_pcie_host;
+
+/**
+ * struct rzg3s_pcie_soc_data - SoC specific data
+ * @init_phy: PHY initialization function
+ * @power_resets: array with the resets that need to be de-asserted after
+ * power-on
+ * @cfg_resets: array with the resets that need to be de-asserted after
+ * configuration
+ * @num_power_resets: number of power resets
+ * @num_cfg_resets: number of configuration resets
+ */
+struct rzg3s_pcie_soc_data {
+ int (*init_phy)(struct rzg3s_pcie_host *host);
+ const char * const *power_resets;
+ const char * const *cfg_resets;
+ u8 num_power_resets;
+ u8 num_cfg_resets;
+};
+
+/**
+ * struct rzg3s_pcie_port - RZ/G3S PCIe Root port data structure
+ * @refclk: PCIe reference clock
+ * @vendor_id: Vendor ID
+ * @device_id: Device ID
+ */
+struct rzg3s_pcie_port {
+ struct clk *refclk;
+ u32 vendor_id;
+ u32 device_id;
+};
+
+/**
+ * struct rzg3s_pcie_host - RZ/G3S PCIe data structure
+ * @axi: base address for AXI registers
+ * @pcie: base address for PCIe registers
+ * @dev: struct device
+ * @power_resets: reset control signals that should be set after power up
+ * @cfg_resets: reset control signals that should be set after configuration
+ * @sysc: SYSC regmap
+ * @intx_domain: INTx IRQ domain
+ * @data: SoC specific data
+ * @msi: MSI data structure
+ * @port: PCIe Root port
+ * @hw_lock: lock for access to the HW resources
+ * @intx_irqs: INTx interrupts
+ * @max_link_speed: maximum supported link speed
+ */
+struct rzg3s_pcie_host {
+ void __iomem *axi;
+ void __iomem *pcie;
+ struct device *dev;
+ struct reset_control_bulk_data *power_resets;
+ struct reset_control_bulk_data *cfg_resets;
+ struct regmap *sysc;
+ struct irq_domain *intx_domain;
+ const struct rzg3s_pcie_soc_data *data;
+ struct rzg3s_pcie_msi msi;
+ struct rzg3s_pcie_port port;
+ raw_spinlock_t hw_lock;
+ int intx_irqs[PCI_NUM_INTX];
+ int max_link_speed;
+};
+
+#define rzg3s_msi_to_host(_msi) container_of(_msi, struct rzg3s_pcie_host, msi)
+
+static void rzg3s_pcie_update_bits(void __iomem *base, u32 offset, u32 mask,
+ u32 val)
+{
+ u32 tmp;
+
+ tmp = readl_relaxed(base + offset);
+ tmp &= ~mask;
+ tmp |= val & mask;
+ writel_relaxed(tmp, base + offset);
+}
+
+static int rzg3s_pcie_child_issue_request(struct rzg3s_pcie_host *host)
+{
+ u32 val;
+ int ret;
+
+ rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_REQISS,
+ RZG3S_PCI_REQISS_REQ_ISSUE,
+ RZG3S_PCI_REQISS_REQ_ISSUE);
+ ret = readl_poll_timeout_atomic(host->axi + RZG3S_PCI_REQISS, val,
+ !(val & RZG3S_PCI_REQISS_REQ_ISSUE),
+ 5, RZG3S_REQ_ISSUE_TIMEOUT_US);
+
+ if (val & RZG3S_PCI_REQISS_MOR_STATUS)
+ return -EIO;
+
+ return ret;
+}
+
+static void rzg3s_pcie_child_prepare_bus(struct pci_bus *bus,
+ unsigned int devfn, int where)
+{
+ struct rzg3s_pcie_host *host = bus->sysdata;
+ unsigned int dev, func, reg;
+
+ dev = PCI_SLOT(devfn);
+ func = PCI_FUNC(devfn);
+ reg = where & ~0x3;
+
+ /* Set the destination */
+ writel_relaxed(FIELD_PREP(RZG3S_PCI_REQADR1_BUS, bus->number) |
+ FIELD_PREP(RZG3S_PCI_REQADR1_DEV, dev) |
+ FIELD_PREP(RZG3S_PCI_REQADR1_FUNC, func) |
+ FIELD_PREP(RZG3S_PCI_REQADR1_REG, reg),
+ host->axi + RZG3S_PCI_REQADR1);
+
+ /* Set byte enable */
+ writel_relaxed(RZG3S_PCI_REQBE_BYTE_EN, host->axi + RZG3S_PCI_REQBE);
+}
+
+static int rzg3s_pcie_child_read_conf(struct rzg3s_pcie_host *host,
+ struct pci_bus *bus, unsigned int devfn,
+ int where, u32 *data)
+{
+ bool type0 = pci_is_root_bus(bus->parent) ? true : false;
+ int ret;
+
+ rzg3s_pcie_child_prepare_bus(bus, devfn, where);
+
+ /* Set the type of request */
+ writel_relaxed(type0 ? RZG3S_PCI_REQISS_TR_TP0_RD :
+ RZG3S_PCI_REQISS_TR_TP1_RD,
+ host->axi + RZG3S_PCI_REQISS);
+
+ /* Issue the request and wait to finish */
+ ret = rzg3s_pcie_child_issue_request(host);
+ if (ret)
+ return PCIBIOS_SET_FAILED;
+
+ /* Read the data */
+ *data = readl_relaxed(host->axi + RZG3S_PCI_REQRCVDAT);
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
+static int rzg3s_pcie_child_read(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 *val)
+{
+ struct rzg3s_pcie_host *host = bus->sysdata;
+ int ret;
+
+ ret = rzg3s_pcie_child_read_conf(host, bus, devfn, where, val);
+ if (ret != PCIBIOS_SUCCESSFUL)
+ return ret;
+
+ if (size <= 2)
+ *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int rzg3s_pcie_child_write_conf(struct rzg3s_pcie_host *host,
+ struct pci_bus *bus, unsigned int devfn,
+ int where, u32 data)
+{
+ bool type0 = pci_is_root_bus(bus->parent) ? true : false;
+ int ret;
+
+ rzg3s_pcie_child_prepare_bus(bus, devfn, where);
+
+ /* Set the write data */
+ writel_relaxed(0, host->axi + RZG3S_PCI_REQDATA(0));
+ writel_relaxed(0, host->axi + RZG3S_PCI_REQDATA(1));
+ writel_relaxed(data, host->axi + RZG3S_PCI_REQDATA(2));
+
+ /* Set the type of request */
+ writel_relaxed(type0 ? RZG3S_PCI_REQISS_TR_TP0_WR :
+ RZG3S_PCI_REQISS_TR_TP1_WR,
+ host->axi + RZG3S_PCI_REQISS);
+
+ /* Issue the request and wait to finish */
+ ret = rzg3s_pcie_child_issue_request(host);
+ if (ret)
+ return PCIBIOS_SET_FAILED;
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
+static int rzg3s_pcie_child_write(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 val)
+{
+ struct rzg3s_pcie_host *host = bus->sysdata;
+ u32 data, shift;
+ int ret;
+
+ if (size == 4)
+ return rzg3s_pcie_child_write_conf(host, bus, devfn, where, val);
+
+ /*
+ * Controller does 32 bit accesses. To do byte accesses software need
+ * to do read/modify/write. This may have potential side effects. For
+ * example, software may perform a 16-bit write. If the hardware only
+ * supports 32-bit accesses, we must do a 32-bit read, merge in the 16
+ * bits we intend to write, followed by a 32-bit write. If the 16 bits
+ * we *don't* intend to write happen to have any RW1C
+ * (write-one-to-clear) bits set, we just inadvertently cleared
+ * something we shouldn't have.
+ */
+ if (!bus->unsafe_warn) {
+ dev_warn(&bus->dev, "%d-byte config write to %04x:%02x:%02x.%d offset %#x may corrupt adjacent RW1C bits\n",
+ size, pci_domain_nr(bus), bus->number,
+ PCI_SLOT(devfn), PCI_FUNC(devfn), where);
+ bus->unsafe_warn = 1;
+ }
+
+ ret = rzg3s_pcie_child_read_conf(host, bus, devfn, where, &data);
+ if (ret != PCIBIOS_SUCCESSFUL)
+ return ret;
+
+ if (size == 1) {
+ shift = BITS_PER_BYTE * (where & 3);
+ data &= ~(0xff << shift);
+ data |= ((val & 0xff) << shift);
+ } else if (size == 2) {
+ shift = BITS_PER_BYTE * (where & 2);
+ data &= ~(0xffff << shift);
+ data |= ((val & 0xffff) << shift);
+ } else {
+ data = val;
+ }
+
+ return rzg3s_pcie_child_write_conf(host, bus, devfn, where, data);
+}
+
+static struct pci_ops rzg3s_pcie_child_ops = {
+ .read = rzg3s_pcie_child_read,
+ .write = rzg3s_pcie_child_write,
+};
+
+static void __iomem *rzg3s_pcie_root_map_bus(struct pci_bus *bus,
+ unsigned int devfn, int where)
+{
+ struct rzg3s_pcie_host *host = bus->sysdata;
+
+ if (devfn)
+ return NULL;
+
+ return host->pcie + where;
+}
+
+/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
+static int rzg3s_pcie_root_write(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 val)
+{
+ struct rzg3s_pcie_host *host = bus->sysdata;
+ int ret;
+
+ /* Enable access control to the CFGU */
+ writel_relaxed(RZG3S_PCI_PERM_CFG_HWINIT_EN,
+ host->axi + RZG3S_PCI_PERM);
+
+ ret = pci_generic_config_write(bus, devfn, where, size, val);
+
+ /* Disable access control to the CFGU */
+ writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
+
+ return ret;
+}
+
+static struct pci_ops rzg3s_pcie_root_ops = {
+ .read = pci_generic_config_read,
+ .write = rzg3s_pcie_root_write,
+ .map_bus = rzg3s_pcie_root_map_bus,
+};
+
+static void rzg3s_pcie_intx_irq_handler(struct irq_desc *desc)
+{
+ struct rzg3s_pcie_host *host = irq_desc_get_handler_data(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ unsigned int irq = irq_desc_get_irq(desc);
+ u32 intx = irq - host->intx_irqs[0];
+
+ chained_irq_enter(chip, desc);
+ generic_handle_domain_irq(host->intx_domain, intx);
+ chained_irq_exit(chip, desc);
+}
+
+static irqreturn_t rzg3s_pcie_msi_irq(int irq, void *data)
+{
+ u8 regs = RZG3S_PCI_MSI_INT_NR / RZG3S_PCI_MSI_INT_PER_REG;
+ DECLARE_BITMAP(bitmap, RZG3S_PCI_MSI_INT_NR);
+ struct rzg3s_pcie_host *host = data;
+ struct rzg3s_pcie_msi *msi = &host->msi;
+ unsigned long bit;
+ u32 status;
+
+ status = readl_relaxed(host->axi + RZG3S_PCI_PINTRCVIS);
+ if (!(status & RZG3S_PCI_PINTRCVIS_MSI))
+ return IRQ_NONE;
+
+ /* Clear the MSI */
+ rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIS,
+ RZG3S_PCI_PINTRCVIS_MSI,
+ RZG3S_PCI_PINTRCVIS_MSI);
+ rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSGRCVIS,
+ RZG3S_PCI_MSGRCVIS_MRI, RZG3S_PCI_MSGRCVIS_MRI);
+
+ for (u8 reg_id = 0; reg_id < regs; reg_id++) {
+ status = readl_relaxed(host->axi + RZG3S_PCI_MSIRS(reg_id));
+ bitmap_write(bitmap, status, reg_id * RZG3S_PCI_MSI_INT_PER_REG,
+ RZG3S_PCI_MSI_INT_PER_REG);
+ }
+
+ for_each_set_bit(bit, bitmap, RZG3S_PCI_MSI_INT_NR) {
+ int ret;
+
+ ret = generic_handle_domain_irq(msi->domain, bit);
+ if (ret) {
+ u8 reg_bit = bit % RZG3S_PCI_MSI_INT_PER_REG;
+ u8 reg_id = bit / RZG3S_PCI_MSI_INT_PER_REG;
+
+ /* Unknown MSI, just clear it */
+ writel_relaxed(BIT(reg_bit),
+ host->axi + RZG3S_PCI_MSIRS(reg_id));
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
+static void rzg3s_pcie_msi_irq_ack(struct irq_data *d)
+{
+ struct rzg3s_pcie_msi *msi = irq_data_get_irq_chip_data(d);
+ struct rzg3s_pcie_host *host = rzg3s_msi_to_host(msi);
+ u8 reg_bit = d->hwirq % RZG3S_PCI_MSI_INT_PER_REG;
+ u8 reg_id = d->hwirq / RZG3S_PCI_MSI_INT_PER_REG;
+
+ guard(raw_spinlock_irqsave)(&host->hw_lock);
+
+ writel_relaxed(BIT(reg_bit), host->axi + RZG3S_PCI_MSIRS(reg_id));
+}
+
+static void rzg3s_pcie_msi_irq_mask(struct irq_data *d)
+{
+ struct rzg3s_pcie_msi *msi = irq_data_get_irq_chip_data(d);
+ struct rzg3s_pcie_host *host = rzg3s_msi_to_host(msi);
+ u8 reg_bit = d->hwirq % RZG3S_PCI_MSI_INT_PER_REG;
+ u8 reg_id = d->hwirq / RZG3S_PCI_MSI_INT_PER_REG;
+
+ guard(raw_spinlock_irqsave)(&host->hw_lock);
+
+ rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSIRM(reg_id), BIT(reg_bit),
+ BIT(reg_bit));
+}
+
+static void rzg3s_pcie_msi_irq_unmask(struct irq_data *d)
+{
+ struct rzg3s_pcie_msi *msi = irq_data_get_irq_chip_data(d);
+ struct rzg3s_pcie_host *host = rzg3s_msi_to_host(msi);
+ u8 reg_bit = d->hwirq % RZG3S_PCI_MSI_INT_PER_REG;
+ u8 reg_id = d->hwirq / RZG3S_PCI_MSI_INT_PER_REG;
+
+ guard(raw_spinlock_irqsave)(&host->hw_lock);
+
+ rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSIRM(reg_id), BIT(reg_bit),
+ 0);
+}
+
+static void rzg3s_pcie_irq_compose_msi_msg(struct irq_data *data,
+ struct msi_msg *msg)
+{
+ struct rzg3s_pcie_msi *msi = irq_data_get_irq_chip_data(data);
+ struct rzg3s_pcie_host *host = rzg3s_msi_to_host(msi);
+ u32 lo, hi;
+
+ /*
+ * Enable and msg data enable bits are part of the address lo. Drop
+ * them along with the unused bit.
+ */
+ lo = readl_relaxed(host->axi + RZG3S_PCI_MSIRCVWADRL) &
+ RZG3S_PCI_MSIRCVWADRL_MASK;
+ hi = readl_relaxed(host->axi + RZG3S_PCI_MSIRCVWADRU);
+
+ msg->address_lo = lo;
+ msg->address_hi = hi;
+ msg->data = data->hwirq;
+}
+
+static struct irq_chip rzg3s_pcie_msi_bottom_chip = {
+ .name = "rzg3s-pcie-msi",
+ .irq_ack = rzg3s_pcie_msi_irq_ack,
+ .irq_mask = rzg3s_pcie_msi_irq_mask,
+ .irq_unmask = rzg3s_pcie_msi_irq_unmask,
+ .irq_compose_msi_msg = rzg3s_pcie_irq_compose_msi_msg,
+};
+
+static int rzg3s_pcie_msi_domain_alloc(struct irq_domain *domain,
+ unsigned int virq, unsigned int nr_irqs,
+ void *args)
+{
+ struct rzg3s_pcie_msi *msi = domain->host_data;
+ int hwirq;
+
+ scoped_guard(mutex, &msi->map_lock) {
+ hwirq = bitmap_find_free_region(msi->map, RZG3S_PCI_MSI_INT_NR,
+ order_base_2(nr_irqs));
+ }
+
+ if (hwirq < 0)
+ return -ENOSPC;
+
+ for (unsigned int i = 0; i < nr_irqs; i++) {
+ irq_domain_set_info(domain, virq + i, hwirq + i,
+ &rzg3s_pcie_msi_bottom_chip,
+ domain->host_data, handle_edge_irq, NULL,
+ NULL);
+ }
+
+ return 0;
+}
+
+static void rzg3s_pcie_msi_domain_free(struct irq_domain *domain,
+ unsigned int virq, unsigned int nr_irqs)
+{
+ struct irq_data *d = irq_domain_get_irq_data(domain, virq);
+ struct rzg3s_pcie_msi *msi = domain->host_data;
+
+ guard(mutex)(&msi->map_lock);
+
+ bitmap_release_region(msi->map, d->hwirq, order_base_2(nr_irqs));
+}
+
+static const struct irq_domain_ops rzg3s_pcie_msi_domain_ops = {
+ .alloc = rzg3s_pcie_msi_domain_alloc,
+ .free = rzg3s_pcie_msi_domain_free,
+};
+
+#define RZG3S_PCIE_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \
+ MSI_FLAG_USE_DEF_CHIP_OPS | \
+ MSI_FLAG_NO_AFFINITY | \
+ MSI_FLAG_PCI_MSI_MASK_PARENT)
+
+#define RZG3S_PCIE_MSI_FLAGS_SUPPORTED (MSI_FLAG_MULTI_PCI_MSI | \
+ MSI_GENERIC_FLAGS_MASK)
+
+static const struct msi_parent_ops rzg3s_pcie_msi_parent_ops = {
+ .required_flags = RZG3S_PCIE_MSI_FLAGS_REQUIRED,
+ .supported_flags = RZG3S_PCIE_MSI_FLAGS_SUPPORTED,
+ .bus_select_token = DOMAIN_BUS_PCI_MSI,
+ .chip_flags = MSI_CHIP_FLAG_SET_ACK,
+ .prefix = "RZG3S-",
+ .init_dev_msi_info = msi_lib_init_dev_msi_info,
+};
+
+static int rzg3s_pcie_msi_allocate_domains(struct rzg3s_pcie_msi *msi)
+{
+ struct rzg3s_pcie_host *host = rzg3s_msi_to_host(msi);
+ struct device *dev = host->dev;
+ struct irq_domain_info info = {
+ .fwnode = dev_fwnode(dev),
+ .ops = &rzg3s_pcie_msi_domain_ops,
+ .size = RZG3S_PCI_MSI_INT_NR,
+ .host_data = msi,
+ };
+
+ msi->domain = msi_create_parent_irq_domain(&info,
+ &rzg3s_pcie_msi_parent_ops);
+ if (!msi->domain)
+ return dev_err_probe(dev, -ENOMEM,
+ "failed to create IRQ domain\n");
+
+ return 0;
+}
+
+static int rzg3s_pcie_msi_hw_setup(struct rzg3s_pcie_host *host)
+{
+ u8 regs = RZG3S_PCI_MSI_INT_NR / RZG3S_PCI_MSI_INT_PER_REG;
+ struct rzg3s_pcie_msi *msi = &host->msi;
+
+ /*
+ * Set MSI window size. HW will set the window to
+ * RZG3S_PCI_MSI_INT_NR * 4 bytes.
+ */
+ writel_relaxed(FIELD_PREP(RZG3S_PCI_MSIRCVWMSKL_MASK,
+ RZG3S_PCI_MSI_INT_NR - 1),
+ host->axi + RZG3S_PCI_MSIRCVWMSKL);
+
+ /* Set MSI window address and enable MSI window */
+ writel_relaxed(upper_32_bits(msi->window_base),
+ host->axi + RZG3S_PCI_MSIRCVWADRU);
+ writel_relaxed(lower_32_bits(msi->window_base) |
+ RZG3S_PCI_MSIRCVWADRL_ENA |
+ RZG3S_PCI_MSIRCVWADRL_MSG_DATA_ENA,
+ host->axi + RZG3S_PCI_MSIRCVWADRL);
+
+ /* Set MSI receive enable */
+ for (u8 reg_id = 0; reg_id < regs; reg_id++) {
+ writel_relaxed(RZG3S_PCI_MSIRE_ENA,
+ host->axi + RZG3S_PCI_MSIRE(reg_id));
+ }
+
+ /* Enable message receive interrupts */
+ writel_relaxed(RZG3S_PCI_MSGRCVIE_MSG_RCV,
+ host->axi + RZG3S_PCI_MSGRCVIE);
+
+ /* Enable MSI */
+ rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIE,
+ RZG3S_PCI_PINTRCVIE_MSI,
+ RZG3S_PCI_PINTRCVIE_MSI);
+
+ return 0;
+}
+
+static int rzg3s_pcie_msi_setup(struct rzg3s_pcie_host *host)
+{
+ size_t size = RZG3S_PCI_MSI_INT_NR * sizeof(u32);
+ struct rzg3s_pcie_msi *msi = &host->msi;
+ struct device *dev = host->dev;
+ int id, ret;
+
+ msi->pages = __get_free_pages(GFP_KERNEL | GFP_DMA, 0);
+ if (!msi->pages)
+ return -ENOMEM;
+
+ msi->dma_addr = dma_map_single(dev, (void *)msi->pages, size * 2,
+ DMA_BIDIRECTIONAL);
+ if (dma_mapping_error(dev, msi->dma_addr)) {
+ ret = -ENOMEM;
+ goto free_pages;
+ }
+
+ /*
+ * According to the RZ/G3S HW manual (Rev.1.10, section 34.4.5.2 Setting
+ * the MSI Window) the MSI window needs to fall within one of the
+ * enabled AXI windows. Find an enabled AXI window to setup the MSI
+ * window.
+ */
+ for (id = 0; id < RZG3S_MAX_WINDOWS; id++) {
+ u64 base, basel, baseu;
+ u64 mask, maskl, masku;
+
+ basel = readl_relaxed(host->axi + RZG3S_PCI_AWBASEL(id));
+ /* Skip checking this AXI window if it's not enabled */
+ if (!(basel & RZG3S_PCI_AWBASEL_WIN_ENA))
+ continue;
+
+ baseu = readl_relaxed(host->axi + RZG3S_PCI_AWBASEU(id));
+ base = baseu << 32 | basel;
+
+ maskl = readl_relaxed(host->axi + RZG3S_PCI_AWMASKL(id));
+ masku = readl_relaxed(host->axi + RZG3S_PCI_AWMASKU(id));
+ mask = masku << 32 | maskl;
+
+ if (msi->dma_addr < base || msi->dma_addr > base + mask)
+ continue;
+
+ break;
+ }
+
+ if (id == RZG3S_MAX_WINDOWS) {
+ ret = -EINVAL;
+ goto dma_unmap;
+ }
+
+ /* The MSI base address need to be aligned to the MSI size */
+ msi->window_base = ALIGN(msi->dma_addr, size);
+ if (msi->window_base < msi->dma_addr) {
+ ret = -EINVAL;
+ goto dma_unmap;
+ }
+
+ rzg3s_pcie_msi_hw_setup(host);
+
+ return 0;
+
+dma_unmap:
+ dma_unmap_single(dev, msi->dma_addr, size * 2, DMA_BIDIRECTIONAL);
+free_pages:
+ free_pages(msi->pages, 0);
+ return ret;
+}
+
+static void rzg3s_pcie_msi_hw_teardown(struct rzg3s_pcie_host *host)
+{
+ u8 regs = RZG3S_PCI_MSI_INT_NR / RZG3S_PCI_MSI_INT_PER_REG;
+
+ /* Disable MSI */
+ rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIE,
+ RZG3S_PCI_PINTRCVIE_MSI, 0);
+
+ /* Disable message receive interrupts */
+ rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSGRCVIE,
+ RZG3S_PCI_MSGRCVIE_MSG_RCV, 0);
+
+ /* Disable MSI receive enable */
+ for (u8 reg_id = 0; reg_id < regs; reg_id++)
+ writel_relaxed(0, host->axi + RZG3S_PCI_MSIRE(reg_id));
+
+ /* Disable MSI window */
+ writel_relaxed(0, host->axi + RZG3S_PCI_MSIRCVWADRL);
+}
+
+static void rzg3s_pcie_teardown_msi(struct rzg3s_pcie_host *host)
+{
+ size_t size = RZG3S_PCI_MSI_INT_NR * sizeof(u32);
+ struct rzg3s_pcie_msi *msi = &host->msi;
+
+ rzg3s_pcie_msi_hw_teardown(host);
+
+ free_irq(msi->irq, host);
+ irq_domain_remove(msi->domain);
+
+ /* Free unused memory */
+ dma_unmap_single(host->dev, msi->dma_addr, size * 2, DMA_BIDIRECTIONAL);
+ free_pages(msi->pages, 0);
+}
+
+static int rzg3s_pcie_init_msi(struct rzg3s_pcie_host *host)
+{
+ struct platform_device *pdev = to_platform_device(host->dev);
+ struct rzg3s_pcie_msi *msi = &host->msi;
+ struct device *dev = host->dev;
+ const char *devname;
+ int ret;
+
+ ret = devm_mutex_init(dev, &msi->map_lock);
+ if (ret)
+ return ret;
+
+ msi->irq = platform_get_irq_byname(pdev, "msi");
+ if (msi->irq < 0)
+ return dev_err_probe(dev, msi->irq, "Failed to get MSI IRQ!\n");
+
+ devname = devm_kasprintf(dev, GFP_KERNEL, "%s-msi", dev_name(dev));
+ if (!devname)
+ return -ENOMEM;
+
+ ret = rzg3s_pcie_msi_allocate_domains(msi);
+ if (ret)
+ return ret;
+
+ /*
+ * Don't use devm_request_irq() as the driver uses non-devm helpers
+ * to control clocks. Mixing them may lead to subtle bugs.
+ */
+ ret = request_irq(msi->irq, rzg3s_pcie_msi_irq, 0, devname, host);
+ if (ret) {
+ dev_err_probe(dev, ret, "Failed to request IRQ: %d\n", ret);
+ goto free_domains;
+ }
+
+ ret = rzg3s_pcie_msi_setup(host);
+ if (ret) {
+ dev_err_probe(dev, ret, "Failed to setup MSI!\n");
+ goto free_irq;
+ }
+
+ return 0;
+
+free_irq:
+ free_irq(msi->irq, host);
+free_domains:
+ irq_domain_remove(msi->domain);
+ return ret;
+}
+
+static void rzg3s_pcie_intx_irq_ack(struct irq_data *d)
+{
+ struct rzg3s_pcie_host *host = irq_data_get_irq_chip_data(d);
+
+ guard(raw_spinlock_irqsave)(&host->hw_lock);
+
+ rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIS,
+ RZG3S_PCI_PINTRCVIS_INTX(d->hwirq),
+ RZG3S_PCI_PINTRCVIS_INTX(d->hwirq));
+}
+
+static void rzg3s_pcie_intx_irq_mask(struct irq_data *d)
+{
+ struct rzg3s_pcie_host *host = irq_data_get_irq_chip_data(d);
+
+ guard(raw_spinlock_irqsave)(&host->hw_lock);
+
+ rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIE,
+ RZG3S_PCI_PINTRCVIE_INTX(d->hwirq), 0);
+}
+
+static void rzg3s_pcie_intx_irq_unmask(struct irq_data *d)
+{
+ struct rzg3s_pcie_host *host = irq_data_get_irq_chip_data(d);
+
+ guard(raw_spinlock_irqsave)(&host->hw_lock);
+
+ rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIE,
+ RZG3S_PCI_PINTRCVIE_INTX(d->hwirq),
+ RZG3S_PCI_PINTRCVIE_INTX(d->hwirq));
+}
+
+static struct irq_chip rzg3s_pcie_intx_irq_chip = {
+ .name = "PCIe INTx",
+ .irq_ack = rzg3s_pcie_intx_irq_ack,
+ .irq_mask = rzg3s_pcie_intx_irq_mask,
+ .irq_unmask = rzg3s_pcie_intx_irq_unmask,
+};
+
+static int rzg3s_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
+ irq_hw_number_t hwirq)
+{
+ irq_set_chip_and_handler(irq, &rzg3s_pcie_intx_irq_chip,
+ handle_level_irq);
+ irq_set_chip_data(irq, domain->host_data);
+
+ return 0;
+}
+
+static const struct irq_domain_ops rzg3s_pcie_intx_domain_ops = {
+ .map = rzg3s_pcie_intx_map,
+ .xlate = irq_domain_xlate_onetwocell,
+};
+
+static int rzg3s_pcie_init_irqdomain(struct rzg3s_pcie_host *host)
+{
+ struct device *dev = host->dev;
+ struct platform_device *pdev = to_platform_device(dev);
+
+ for (int i = 0; i < PCI_NUM_INTX; i++) {
+ char irq_name[5] = {0};
+ int irq;
+
+ scnprintf(irq_name, ARRAY_SIZE(irq_name), "int%c", 'a' + i);
+
+ irq = platform_get_irq_byname(pdev, irq_name);
+ if (irq < 0)
+ return dev_err_probe(dev, -EINVAL,
+ "Failed to parse and map INT%c IRQ\n",
+ 'A' + i);
+
+ host->intx_irqs[i] = irq;
+ irq_set_chained_handler_and_data(irq,
+ rzg3s_pcie_intx_irq_handler,
+ host);
+ }
+
+ host->intx_domain = irq_domain_create_linear(dev_fwnode(dev),
+ PCI_NUM_INTX,
+ &rzg3s_pcie_intx_domain_ops,
+ host);
+ if (!host->intx_domain)
+ return dev_err_probe(dev, -EINVAL,
+ "Failed to add irq domain for INTx IRQs\n");
+ irq_domain_update_bus_token(host->intx_domain, DOMAIN_BUS_WIRED);
+
+ if (IS_ENABLED(CONFIG_PCI_MSI)) {
+ int ret = rzg3s_pcie_init_msi(host);
+
+ if (ret) {
+ irq_domain_remove(host->intx_domain);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static void rzg3s_pcie_teardown_irqdomain(struct rzg3s_pcie_host *host)
+{
+ if (IS_ENABLED(CONFIG_PCI_MSI))
+ rzg3s_pcie_teardown_msi(host);
+
+ irq_domain_remove(host->intx_domain);
+}
+
+static int rzg3s_pcie_set_max_link_speed(struct rzg3s_pcie_host *host)
+{
+ u32 remote_supported_link_speeds, max_supported_link_speeds;
+ u32 cs2, tmp, pcie_cap = RZG3S_PCI_CFG_PCIEC;
+ u32 cur_link_speed, link_speed;
+ u8 ltssm_state_l0 = 0xc;
+ int ret;
+ u16 ls;
+
+ /*
+ * According to the RZ/G3S HW manual (Rev.1.10, section 34.6.3 Caution
+ * when Changing the Speed Spontaneously) link speed change can be done
+ * only when the LTSSM is in L0.
+ */
+ ret = readl_poll_timeout(host->axi + RZG3S_PCI_PCSTAT1, tmp,
+ FIELD_GET(RZG3S_PCI_PCSTAT1_LTSSM_STATE, tmp) == ltssm_state_l0,
+ PCIE_LINK_WAIT_SLEEP_MS * MILLI,
+ PCIE_LINK_WAIT_SLEEP_MS * MILLI *
+ PCIE_LINK_WAIT_MAX_RETRIES);
+ if (ret)
+ return ret;
+
+ ls = readw_relaxed(host->pcie + pcie_cap + PCI_EXP_LNKSTA);
+ cs2 = readl_relaxed(host->axi + RZG3S_PCI_PCSTAT2);
+
+ switch (pcie_link_speed[host->max_link_speed]) {
+ case PCIE_SPEED_5_0GT:
+ max_supported_link_speeds = GENMASK(PCI_EXP_LNKSTA_CLS_5_0GB - 1, 0);
+ link_speed = PCI_EXP_LNKCTL2_TLS_5_0GT;
+ break;
+ default:
+ /* Should not happen */
+ return -EINVAL;
+ }
+
+ cur_link_speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, ls);
+ remote_supported_link_speeds = FIELD_GET(RZG3S_PCI_PCSTAT2_SDRIRE, cs2);
+ /* Drop reserved bits */
+ remote_supported_link_speeds &= max_supported_link_speeds;
+
+ /*
+ * Return if max link speed is already set or the connected device
+ * doesn't support it.
+ */
+ if (cur_link_speed == host->max_link_speed ||
+ remote_supported_link_speeds != max_supported_link_speeds)
+ return 0;
+
+ /* Set target Link speed */
+ rzg3s_pcie_update_bits(host->pcie, pcie_cap + PCI_EXP_LNKCTL2,
+ PCI_EXP_LNKCTL2_TLS,
+ FIELD_PREP(PCI_EXP_LNKCTL2_TLS, link_speed));
+
+ /* Request link speed change */
+ rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PCCTRL2,
+ RZG3S_PCI_PCCTRL2_LS_CHG_REQ |
+ RZG3S_PCI_PCCTRL2_LS_CHG,
+ RZG3S_PCI_PCCTRL2_LS_CHG_REQ |
+ FIELD_PREP(RZG3S_PCI_PCCTRL2_LS_CHG,
+ link_speed - 1));
+
+ ret = readl_poll_timeout(host->axi + RZG3S_PCI_PCSTAT2, cs2,
+ (cs2 & RZG3S_PCI_PCSTAT2_LS_CHG_DONE),
+ PCIE_LINK_WAIT_SLEEP_MS * MILLI,
+ PCIE_LINK_WAIT_SLEEP_MS * MILLI *
+ PCIE_LINK_WAIT_MAX_RETRIES);
+
+ /*
+ * According to the RZ/G3S HW manual (Rev.1.10, section 34.6.3 Caution
+ * when Changing the Speed Spontaneously) the PCI_PCCTRL2_LS_CHG_REQ
+ * should be de-asserted after checking for PCI_PCSTAT2_LS_CHG_DONE.
+ */
+ rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PCCTRL2,
+ RZG3S_PCI_PCCTRL2_LS_CHG_REQ, 0);
+
+ return ret;
+}
+
+static int rzg3s_pcie_config_init(struct rzg3s_pcie_host *host)
+{
+ struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host);
+ struct resource_entry *ft;
+ struct resource *bus;
+ u8 subordinate_bus;
+ u8 secondary_bus;
+ u8 primary_bus;
+
+ ft = resource_list_first_type(&bridge->windows, IORESOURCE_BUS);
+ if (!ft)
+ return -ENODEV;
+
+ bus = ft->res;
+ primary_bus = bus->start;
+ secondary_bus = bus->start + 1;
+ subordinate_bus = bus->end;
+
+ /* Enable access control to the CFGU */
+ writel_relaxed(RZG3S_PCI_PERM_CFG_HWINIT_EN,
+ host->axi + RZG3S_PCI_PERM);
+
+ /* HW manual recommends to write 0xffffffff on initialization */
+ writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00L);
+ writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00U);
+
+ /* Update bus info */
+ writeb_relaxed(primary_bus, host->pcie + PCI_PRIMARY_BUS);
+ writeb_relaxed(secondary_bus, host->pcie + PCI_SECONDARY_BUS);
+ writeb_relaxed(subordinate_bus, host->pcie + PCI_SUBORDINATE_BUS);
+
+ /* Disable access control to the CFGU */
+ writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
+
+ return 0;
+}
+
+static void rzg3s_pcie_irq_init(struct rzg3s_pcie_host *host)
+{
+ /*
+ * According to the HW manual of the RZ/G3S (Rev.1.10, sections
+ * corresponding to all registers written with ~0U), the hardware
+ * ignores value written to unused bits. Writing ~0U to these registers
+ * should be safe.
+ */
+
+ /* Clear the link state and PM transitions */
+ writel_relaxed(RZG3S_PCI_PEIS0_DL_UPDOWN |
+ RZG3S_PCI_PEIS0_RX_DLLP_PM_ENTER,
+ host->axi + RZG3S_PCI_PEIS0);
+
+ /* Disable all interrupts */
+ writel_relaxed(0, host->axi + RZG3S_PCI_PEIE0);
+
+ /* Clear all parity and ecc error interrupts */
+ writel_relaxed(~0U, host->axi + RZG3S_PCI_PEIS1);
+
+ /* Disable all parity and ecc error interrupts */
+ writel_relaxed(0, host->axi + RZG3S_PCI_PEIE1);
+
+ /* Clear all AXI master error interrupts */
+ writel_relaxed(~0U, host->axi + RZG3S_PCI_AMEIS);
+
+ /* Clear all AXI slave error interrupts */
+ writel_relaxed(~0U, host->axi + RZG3S_PCI_ASEIS1);
+
+ /* Clear all message receive interrupts */
+ writel_relaxed(~0U, host->axi + RZG3S_PCI_MSGRCVIS);
+}
+
+static int rzg3s_pcie_power_resets_deassert(struct rzg3s_pcie_host *host)
+{
+ const struct rzg3s_pcie_soc_data *data = host->data;
+
+ /*
+ * According to the RZ/G3S HW manual (Rev.1.10, section
+ * 34.5.1.2 De-asserting the Reset) the PCIe IP needs to wait 5ms from
+ * power on to the de-assertion of reset.
+ */
+ fsleep(5000);
+ return reset_control_bulk_deassert(data->num_power_resets,
+ host->power_resets);
+}
+
+static int rzg3s_pcie_resets_prepare_and_get(struct rzg3s_pcie_host *host)
+{
+ const struct rzg3s_pcie_soc_data *data = host->data;
+ int ret;
+
+ host->power_resets = devm_kmalloc_array(host->dev,
+ data->num_power_resets,
+ sizeof(*host->power_resets),
+ GFP_KERNEL);
+ if (!host->power_resets)
+ return -ENOMEM;
+
+ for (unsigned int i = 0; i < data->num_power_resets; i++)
+ host->power_resets[i].id = data->power_resets[i];
+
+ host->cfg_resets = devm_kmalloc_array(host->dev,
+ data->num_cfg_resets,
+ sizeof(*host->cfg_resets),
+ GFP_KERNEL);
+ if (!host->cfg_resets)
+ return -ENOMEM;
+
+ for (unsigned int i = 0; i < data->num_cfg_resets; i++)
+ host->cfg_resets[i].id = data->cfg_resets[i];
+
+ ret = devm_reset_control_bulk_get_exclusive(host->dev,
+ data->num_power_resets,
+ host->power_resets);
+ if (ret)
+ return ret;
+
+ return devm_reset_control_bulk_get_exclusive(host->dev,
+ data->num_cfg_resets,
+ host->cfg_resets);
+}
+
+static int rzg3s_pcie_host_parse_port(struct rzg3s_pcie_host *host)
+{
+ struct device_node *of_port = of_get_next_child(host->dev->of_node, NULL);
+ struct rzg3s_pcie_port *port = &host->port;
+ int ret;
+
+ ret = of_property_read_u32(of_port, "vendor-id", &port->vendor_id);
+ if (ret)
+ return ret;
+
+ ret = of_property_read_u32(of_port, "device-id", &port->device_id);
+ if (ret)
+ return ret;
+
+ port->refclk = of_clk_get_by_name(of_port, "ref");
+ if (IS_ERR(port->refclk))
+ return PTR_ERR(port->refclk);
+
+ return 0;
+}
+
+static int rzg3s_pcie_host_init_port(struct rzg3s_pcie_host *host)
+{
+ struct rzg3s_pcie_port *port = &host->port;
+ struct device *dev = host->dev;
+ int ret;
+
+ /* Enable access control to the CFGU */
+ writel_relaxed(RZG3S_PCI_PERM_CFG_HWINIT_EN,
+ host->axi + RZG3S_PCI_PERM);
+
+ /* Update vendor ID and device ID */
+ writew_relaxed(port->vendor_id, host->pcie + PCI_VENDOR_ID);
+ writew_relaxed(port->device_id, host->pcie + PCI_DEVICE_ID);
+
+ /* Disable access control to the CFGU */
+ writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
+
+ ret = clk_prepare_enable(port->refclk);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to enable refclk!\n");
+
+ /* Set the PHY, if any */
+ if (host->data->init_phy) {
+ ret = host->data->init_phy(host);
+ if (ret) {
+ dev_err_probe(dev, ret, "Failed to set the PHY!\n");
+ goto refclk_disable;
+ }
+ }
+
+ return 0;
+
+refclk_disable:
+ clk_disable_unprepare(port->refclk);
+ return ret;
+}
+
+static int rzg3s_pcie_host_init(struct rzg3s_pcie_host *host)
+{
+ u32 val;
+ int ret;
+
+ /* Initialize the PCIe related registers */
+ ret = rzg3s_pcie_config_init(host);
+ if (ret)
+ return ret;
+
+ ret = rzg3s_pcie_host_init_port(host);
+ if (ret)
+ return ret;
+
+ /* Initialize the interrupts */
+ rzg3s_pcie_irq_init(host);
+
+ ret = reset_control_bulk_deassert(host->data->num_cfg_resets,
+ host->cfg_resets);
+ if (ret)
+ goto disable_port_refclk;
+
+ /* Wait for link up */
+ ret = readl_poll_timeout(host->axi + RZG3S_PCI_PCSTAT1, val,
+ !(val & RZG3S_PCI_PCSTAT1_DL_DOWN_STS),
+ PCIE_LINK_WAIT_SLEEP_MS * MILLI,
+ PCIE_LINK_WAIT_SLEEP_MS * MILLI *
+ PCIE_LINK_WAIT_MAX_RETRIES);
+ if (ret)
+ goto cfg_resets_deassert;
+
+ val = readl_relaxed(host->axi + RZG3S_PCI_PCSTAT2);
+ dev_info(host->dev, "PCIe link status [0x%x]\n", val);
+
+ return 0;
+
+cfg_resets_deassert:
+ reset_control_bulk_assert(host->data->num_cfg_resets,
+ host->cfg_resets);
+disable_port_refclk:
+ clk_disable_unprepare(host->port.refclk);
+ return ret;
+}
+
+static void rzg3s_pcie_set_inbound_window(struct rzg3s_pcie_host *host,
+ u64 cpu_addr, u64 pci_addr, u64 size,
+ int id)
+{
+ /* Set CPU window base address */
+ writel_relaxed(upper_32_bits(cpu_addr),
+ host->axi + RZG3S_PCI_ADESTU(id));
+ writel_relaxed(lower_32_bits(cpu_addr),
+ host->axi + RZG3S_PCI_ADESTL(id));
+
+ /* Set window size */
+ writel_relaxed(upper_32_bits(size), host->axi + RZG3S_PCI_AWMASKU(id));
+ writel_relaxed(lower_32_bits(size), host->axi + RZG3S_PCI_AWMASKL(id));
+
+ /* Set PCIe window base address and enable the window */
+ writel_relaxed(upper_32_bits(pci_addr),
+ host->axi + RZG3S_PCI_AWBASEU(id));
+ writel_relaxed(lower_32_bits(pci_addr) | RZG3S_PCI_AWBASEL_WIN_ENA,
+ host->axi + RZG3S_PCI_AWBASEL(id));
+}
+
+static int rzg3s_pcie_set_inbound_windows(struct rzg3s_pcie_host *host,
+ struct resource_entry *entry,
+ int *index)
+{
+ u64 pci_addr = entry->res->start - entry->offset;
+ u64 cpu_addr = entry->res->start;
+ u64 cpu_end = entry->res->end;
+ u64 size_id = 0;
+ int id = *index;
+ u64 size;
+
+ while (cpu_addr < cpu_end) {
+ if (id >= RZG3S_MAX_WINDOWS)
+ return dev_err_probe(host->dev, -ENOSPC,
+ "Failed to map inbound window for resource (%s)\n",
+ entry->res->name);
+
+ size = resource_size(entry->res) - size_id;
+
+ /*
+ * According to the RZ/G3S HW manual (Rev.1.10,
+ * section 34.3.1.71 AXI Window Mask (Lower) Registers) the min
+ * size is 4K.
+ */
+ size = max(size, SZ_4K);
+
+ /*
+ * According the RZ/G3S HW manual (Rev.1.10, sections:
+ * - 34.3.1.69 AXI Window Base (Lower) Registers
+ * - 34.3.1.71 AXI Window Mask (Lower) Registers
+ * - 34.3.1.73 AXI Destination (Lower) Registers)
+ * the CPU addr, PCIe addr, size should be 4K aligned and be a
+ * power of 2.
+ */
+ size = ALIGN(size, SZ_4K);
+ size = roundup_pow_of_two(size);
+
+ cpu_addr = ALIGN(cpu_addr, SZ_4K);
+ pci_addr = ALIGN(pci_addr, SZ_4K);
+
+ /*
+ * According to the RZ/G3S HW manual (Rev.1.10, section
+ * 34.3.1.71 AXI Window Mask (Lower) Registers) HW expects first
+ * 12 LSB bits to be 0xfff. Subtract 1 from size for this.
+ */
+ rzg3s_pcie_set_inbound_window(host, cpu_addr, pci_addr,
+ size - 1, id);
+
+ pci_addr += size;
+ cpu_addr += size;
+ size_id = size;
+ id++;
+ }
+ *index = id;
+
+ return 0;
+}
+
+static int rzg3s_pcie_parse_map_dma_ranges(struct rzg3s_pcie_host *host)
+{
+ struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host);
+ struct resource_entry *entry;
+ int i = 0, ret;
+
+ resource_list_for_each_entry(entry, &bridge->dma_ranges) {
+ ret = rzg3s_pcie_set_inbound_windows(host, entry, &i);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static void rzg3s_pcie_set_outbound_window(struct rzg3s_pcie_host *host,
+ struct resource_entry *win, int id)
+{
+ struct resource *res = win->res;
+ resource_size_t size = resource_size(res);
+ resource_size_t res_start;
+
+ if (res->flags & IORESOURCE_IO)
+ res_start = pci_pio_to_address(res->start) - win->offset;
+ else
+ res_start = res->start - win->offset;
+
+ /*
+ * According to the RZ/G3S HW manual (Rev.1.10, section 34.3.1.75 PCIe
+ * Window Base (Lower) Registers) the window base address need to be 4K
+ * aligned.
+ */
+ res_start = ALIGN(res_start, SZ_4K);
+
+ size = ALIGN(size, SZ_4K);
+ size = roundup_pow_of_two(size) - 1;
+
+ /* Set PCIe destination */
+ writel_relaxed(upper_32_bits(res_start),
+ host->axi + RZG3S_PCI_PDESTU(id));
+ writel_relaxed(lower_32_bits(res_start),
+ host->axi + RZG3S_PCI_PDESTL(id));
+
+ /* Set PCIe window mask */
+ writel_relaxed(upper_32_bits(size), host->axi + RZG3S_PCI_PWMASKU(id));
+ writel_relaxed(lower_32_bits(size), host->axi + RZG3S_PCI_PWMASKL(id));
+
+ /* Set PCIe window base and enable the window */
+ writel_relaxed(upper_32_bits(res_start),
+ host->axi + RZG3S_PCI_PWBASEU(id));
+ writel_relaxed(lower_32_bits(res_start) | RZG3S_PCI_PWBASEL_ENA,
+ host->axi + RZG3S_PCI_PWBASEL(id));
+}
+
+static int rzg3s_pcie_parse_map_ranges(struct rzg3s_pcie_host *host)
+{
+ struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host);
+ struct resource_entry *win;
+ int i = 0;
+
+ resource_list_for_each_entry(win, &bridge->windows) {
+ struct resource *res = win->res;
+
+ if (i >= RZG3S_MAX_WINDOWS)
+ return dev_err_probe(host->dev, -ENOSPC,
+ "Failed to map outbound window for resource (%s)\n",
+ res->name);
+
+ if (!res->flags)
+ continue;
+
+ switch (resource_type(res)) {
+ case IORESOURCE_IO:
+ case IORESOURCE_MEM:
+ rzg3s_pcie_set_outbound_window(host, win, i);
+ i++;
+ break;
+ }
+ }
+
+ return 0;
+}
+
+static int rzg3s_soc_pcie_init_phy(struct rzg3s_pcie_host *host)
+{
+ static const u32 xcfgd_settings[RZG3S_PCI_PHY_XCFGD_NUM] = {
+ [8] = 0xe0006801, 0x007f7e30, 0x183e0000, 0x978ff500,
+ 0xec000000, 0x009f1400, 0x0000d009,
+ [17] = 0x78000000,
+ [19] = 0x00880000, 0x000005c0, 0x07000000, 0x00780920,
+ 0xc9400ce2, 0x90000c0c, 0x000c1414, 0x00005034,
+ 0x00006000, 0x00000001,
+ };
+ static const u32 xcfga_cmn_settings[RZG3S_PCI_PHY_XCFGA_CMN_NUM] = {
+ 0x00000d10, 0x08310100, 0x00c21404, 0x013c0010, 0x01874440,
+ 0x1a216082, 0x00103440, 0x00000080, 0x00000010, 0x0c1000c1,
+ 0x1000c100, 0x0222000c, 0x00640019, 0x00a00028, 0x01d11228,
+ 0x0201001d,
+ };
+ static const u32 xcfga_rx_settings[RZG3S_PCI_PHY_XCFGA_RX_NUM] = {
+ 0x07d55000, 0x030e3f00, 0x00000288, 0x102c5880, 0x0000000b,
+ 0x04141441, 0x00641641, 0x00d63d63, 0x00641641, 0x01970377,
+ 0x00190287, 0x00190028, 0x00000028,
+ };
+
+ /*
+ * Enable access permission for physical layer control and status
+ * registers.
+ */
+ writel_relaxed(RZG3S_PCI_PERM_PIPE_PHY_REG_EN,
+ host->axi + RZG3S_PCI_PERM);
+
+ for (unsigned int i = 0; i < RZG3S_PCI_PHY_XCFGD_NUM; i++) {
+ writel_relaxed(xcfgd_settings[i],
+ host->axi + RZG3S_PCI_PHY_XCFGD(i));
+ }
+
+ for (unsigned int i = 0; i < RZG3S_PCI_PHY_XCFGA_CMN_NUM; i++) {
+ writel_relaxed(xcfga_cmn_settings[i],
+ host->axi + RZG3S_PCI_PHY_XCFGA_CMN(i));
+ }
+
+ for (unsigned int i = 0; i < RZG3S_PCI_PHY_XCFGA_RX_NUM; i++) {
+ writel_relaxed(xcfga_rx_settings[i],
+ host->axi + RZG3S_PCI_PHY_XCFGA_RX(i));
+ }
+
+ writel_relaxed(0x107, host->axi + RZG3S_PCI_PHY_XCFGA_TX);
+
+ /* Select PHY settings values */
+ writel_relaxed(RZG3S_PCI_PHY_XCFG_CTRL_PHYREG_SEL,
+ host->axi + RZG3S_PCI_PHY_XCFG_CTRL);
+
+ /*
+ * Disable access permission for physical layer control and status
+ * registers.
+ */
+ writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
+
+ return 0;
+}
+
+static int
+rzg3s_pcie_host_setup(struct rzg3s_pcie_host *host,
+ int (*init_irqdomain)(struct rzg3s_pcie_host *host),
+ void (*teardown_irqdomain)(struct rzg3s_pcie_host *host))
+{
+ struct device *dev = host->dev;
+ int ret;
+
+ /* Set inbound windows */
+ ret = rzg3s_pcie_parse_map_dma_ranges(host);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Failed to set inbound windows!\n");
+
+ /* Set outbound windows */
+ ret = rzg3s_pcie_parse_map_ranges(host);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Failed to set outbound windows!\n");
+
+ ret = init_irqdomain(host);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to init IRQ domain\n");
+
+ ret = rzg3s_pcie_host_init(host);
+ if (ret) {
+ dev_err_probe(dev, ret, "Failed to initialize the HW!\n");
+ goto teardown_irqdomain;
+ }
+
+ ret = rzg3s_pcie_set_max_link_speed(host);
+ if (ret)
+ dev_info(dev, "Failed to set max link speed\n");
+
+ msleep(PCIE_RESET_CONFIG_WAIT_MS);
+
+ return 0;
+
+teardown_irqdomain:
+ teardown_irqdomain(host);
+
+ return ret;
+}
+
+static int rzg3s_pcie_probe(struct platform_device *pdev)
+{
+ struct pci_host_bridge *bridge;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct device_node *sysc_np __free(device_node) =
+ of_parse_phandle(np, "renesas,sysc", 0);
+ struct rzg3s_pcie_host *host;
+ int ret;
+
+ bridge = devm_pci_alloc_host_bridge(dev, sizeof(*host));
+ if (!bridge)
+ return -ENOMEM;
+
+ host = pci_host_bridge_priv(bridge);
+ host->dev = dev;
+ host->data = device_get_match_data(dev);
+ platform_set_drvdata(pdev, host);
+
+ host->axi = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(host->axi))
+ return PTR_ERR(host->axi);
+ host->pcie = host->axi + RZG3S_PCI_CFG_BASE;
+
+ host->max_link_speed = of_pci_get_max_link_speed(np);
+ if (host->max_link_speed < 0)
+ host->max_link_speed = 2;
+
+ ret = rzg3s_pcie_host_parse_port(host);
+ if (ret)
+ return ret;
+
+ host->sysc = syscon_node_to_regmap(sysc_np);
+ if (IS_ERR(host->sysc)) {
+ ret = PTR_ERR(host->sysc);
+ goto port_refclk_put;
+ }
+
+ ret = regmap_update_bits(host->sysc, RZG3S_SYS_PCIE_RST_RSM_B,
+ RZG3S_SYS_PCIE_RST_RSM_B_MASK,
+ FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 1));
+ if (ret)
+ goto port_refclk_put;
+
+ ret = rzg3s_pcie_resets_prepare_and_get(host);
+ if (ret)
+ goto sysc_signal_restore;
+
+ ret = rzg3s_pcie_power_resets_deassert(host);
+ if (ret)
+ goto sysc_signal_restore;
+
+ pm_runtime_enable(dev);
+
+ /*
+ * Controller clocks are part of a clock power domain. Enable them
+ * through runtime PM.
+ */
+ ret = pm_runtime_resume_and_get(dev);
+ if (ret)
+ goto rpm_disable;
+
+ raw_spin_lock_init(&host->hw_lock);
+
+ ret = rzg3s_pcie_host_setup(host, rzg3s_pcie_init_irqdomain,
+ rzg3s_pcie_teardown_irqdomain);
+ if (ret)
+ goto rpm_put;
+
+ bridge->sysdata = host;
+ bridge->ops = &rzg3s_pcie_root_ops;
+ bridge->child_ops = &rzg3s_pcie_child_ops;
+ ret = pci_host_probe(bridge);
+ if (ret)
+ goto host_probe_teardown;
+
+ return 0;
+
+host_probe_teardown:
+ rzg3s_pcie_teardown_irqdomain(host);
+ reset_control_bulk_deassert(host->data->num_cfg_resets,
+ host->cfg_resets);
+rpm_put:
+ pm_runtime_put_sync(dev);
+rpm_disable:
+ pm_runtime_disable(dev);
+ reset_control_bulk_assert(host->data->num_power_resets,
+ host->power_resets);
+sysc_signal_restore:
+ /*
+ * SYSC RST_RSM_B signal need to be asserted before turning off the
+ * power to the PHY.
+ */
+ regmap_update_bits(host->sysc, RZG3S_SYS_PCIE_RST_RSM_B,
+ RZG3S_SYS_PCIE_RST_RSM_B_MASK,
+ FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 0));
+port_refclk_put:
+ clk_put(host->port.refclk);
+
+ return ret;
+}
+
+static int rzg3s_pcie_suspend_noirq(struct device *dev)
+{
+ struct rzg3s_pcie_host *host = dev_get_drvdata(dev);
+ const struct rzg3s_pcie_soc_data *data = host->data;
+ struct rzg3s_pcie_port *port = &host->port;
+ struct regmap *sysc = host->sysc;
+ int ret;
+
+ ret = pm_runtime_put_sync(dev);
+ if (ret)
+ return ret;
+
+ clk_disable_unprepare(port->refclk);
+
+ ret = reset_control_bulk_assert(data->num_power_resets,
+ host->power_resets);
+ if (ret)
+ goto refclk_restore;
+
+ ret = reset_control_bulk_assert(data->num_cfg_resets,
+ host->cfg_resets);
+ if (ret)
+ goto power_resets_restore;
+
+ ret = regmap_update_bits(sysc, RZG3S_SYS_PCIE_RST_RSM_B,
+ RZG3S_SYS_PCIE_RST_RSM_B_MASK,
+ FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 0));
+ if (ret)
+ goto cfg_resets_restore;
+
+ return 0;
+
+ /* Restore the previous state if any error happens */
+cfg_resets_restore:
+ reset_control_bulk_deassert(data->num_cfg_resets,
+ host->cfg_resets);
+power_resets_restore:
+ reset_control_bulk_deassert(data->num_power_resets,
+ host->power_resets);
+refclk_restore:
+ clk_prepare_enable(port->refclk);
+ pm_runtime_resume_and_get(dev);
+ return ret;
+}
+
+static int rzg3s_pcie_resume_noirq(struct device *dev)
+{
+ struct rzg3s_pcie_host *host = dev_get_drvdata(dev);
+ const struct rzg3s_pcie_soc_data *data = host->data;
+ struct regmap *sysc = host->sysc;
+ int ret;
+
+ ret = regmap_update_bits(sysc, RZG3S_SYS_PCIE_RST_RSM_B,
+ RZG3S_SYS_PCIE_RST_RSM_B_MASK,
+ FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 1));
+ if (ret)
+ return ret;
+
+ ret = rzg3s_pcie_power_resets_deassert(host);
+ if (ret)
+ goto assert_rst_rsm_b;
+
+ ret = pm_runtime_resume_and_get(dev);
+ if (ret)
+ goto assert_power_resets;
+
+ ret = rzg3s_pcie_host_setup(host, rzg3s_pcie_msi_hw_setup,
+ rzg3s_pcie_msi_hw_teardown);
+ if (ret)
+ goto rpm_put;
+
+ return 0;
+
+ /*
+ * If any error happens there is no way to recover the IP. Put it in the
+ * lowest possible power state.
+ */
+rpm_put:
+ pm_runtime_put_sync(dev);
+assert_power_resets:
+ reset_control_bulk_assert(data->num_power_resets,
+ host->power_resets);
+assert_rst_rsm_b:
+ regmap_update_bits(sysc, RZG3S_SYS_PCIE_RST_RSM_B,
+ RZG3S_SYS_PCIE_RST_RSM_B_MASK,
+ FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 0));
+ return ret;
+}
+
+static const struct dev_pm_ops rzg3s_pcie_pm_ops = {
+ NOIRQ_SYSTEM_SLEEP_PM_OPS(rzg3s_pcie_suspend_noirq,
+ rzg3s_pcie_resume_noirq)
+};
+
+static const char * const rzg3s_soc_power_resets[] = {
+ "aresetn", "rst_cfg_b", "rst_load_b",
+};
+
+static const char * const rzg3s_soc_cfg_resets[] = {
+ "rst_b", "rst_ps_b", "rst_gp_b", "rst_rsm_b",
+};
+
+static const struct rzg3s_pcie_soc_data rzg3s_soc_data = {
+ .power_resets = rzg3s_soc_power_resets,
+ .num_power_resets = ARRAY_SIZE(rzg3s_soc_power_resets),
+ .cfg_resets = rzg3s_soc_cfg_resets,
+ .num_cfg_resets = ARRAY_SIZE(rzg3s_soc_cfg_resets),
+ .init_phy = rzg3s_soc_pcie_init_phy,
+};
+
+static const struct of_device_id rzg3s_pcie_of_match[] = {
+ {
+ .compatible = "renesas,r9a08g045-pcie",
+ .data = &rzg3s_soc_data,
+ },
+ {}
+};
+
+static struct platform_driver rzg3s_pcie_driver = {
+ .driver = {
+ .name = "rzg3s-pcie-host",
+ .of_match_table = rzg3s_pcie_of_match,
+ .pm = pm_ptr(&rzg3s_pcie_pm_ops),
+ .suppress_bind_attrs = true,
+ .probe_type = PROBE_PREFER_ASYNCHRONOUS,
+ },
+ .probe = rzg3s_pcie_probe,
+};
+builtin_platform_driver(rzg3s_pcie_driver);
--
2.43.0On Wed, Nov 19, 2025 at 04:35:19PM +0200, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> The Renesas RZ/G3S features a PCIe IP that complies with the PCI Express
> Base Specification 4.0 and supports speeds of up to 5 GT/s. It functions
> only as a root complex, with a single-lane (x1) configuration. The
> controller includes Type 1 configuration registers, as well as IP
> specific registers (called AXI registers) required for various adjustments.
> +/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
> +static int rzg3s_pcie_root_write(struct pci_bus *bus, unsigned int devfn,
> + int where, int size, u32 val)
> +{
> + struct rzg3s_pcie_host *host = bus->sysdata;
> + int ret;
> +
> + /* Enable access control to the CFGU */
> + writel_relaxed(RZG3S_PCI_PERM_CFG_HWINIT_EN,
> + host->axi + RZG3S_PCI_PERM);
I suppose this has been asked and answered already, but it's curious
that you need this for config writes but not for reads. Obviously it
must *work*, but it's unusual and might warrant a comment. "Access
control" must be a hint, but only means something to experts.
> + ret = pci_generic_config_write(bus, devfn, where, size, val);
> +
> + /* Disable access control to the CFGU */
> + writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
> +
> + return ret;
> +}
> +static irqreturn_t rzg3s_pcie_msi_irq(int irq, void *data)
> +{
> + u8 regs = RZG3S_PCI_MSI_INT_NR / RZG3S_PCI_MSI_INT_PER_REG;
> + DECLARE_BITMAP(bitmap, RZG3S_PCI_MSI_INT_NR);
> + struct rzg3s_pcie_host *host = data;
> + struct rzg3s_pcie_msi *msi = &host->msi;
> + unsigned long bit;
> + u32 status;
> +
> + status = readl_relaxed(host->axi + RZG3S_PCI_PINTRCVIS);
> + if (!(status & RZG3S_PCI_PINTRCVIS_MSI))
> + return IRQ_NONE;
> +
> + /* Clear the MSI */
> + rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIS,
> + RZG3S_PCI_PINTRCVIS_MSI,
> + RZG3S_PCI_PINTRCVIS_MSI);
Other writes to RZG3S_PCI_PINTRCVIS are guarded by host->hw_lock. Is this
one safe without it?
> + rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSGRCVIS,
> + RZG3S_PCI_MSGRCVIS_MRI, RZG3S_PCI_MSGRCVIS_MRI);
> +
> + for (u8 reg_id = 0; reg_id < regs; reg_id++) {
> + status = readl_relaxed(host->axi + RZG3S_PCI_MSIRS(reg_id));
> + bitmap_write(bitmap, status, reg_id * RZG3S_PCI_MSI_INT_PER_REG,
> + RZG3S_PCI_MSI_INT_PER_REG);
> + }
> +
> + for_each_set_bit(bit, bitmap, RZG3S_PCI_MSI_INT_NR) {
> + int ret;
> +
> + ret = generic_handle_domain_irq(msi->domain, bit);
> + if (ret) {
> + u8 reg_bit = bit % RZG3S_PCI_MSI_INT_PER_REG;
> + u8 reg_id = bit / RZG3S_PCI_MSI_INT_PER_REG;
> +
> + /* Unknown MSI, just clear it */
> + writel_relaxed(BIT(reg_bit),
> + host->axi + RZG3S_PCI_MSIRS(reg_id));
Other writes to RZG3S_PCI_MSIRS are guarded by host->hw_lock. Is this
one safe without it?
> + }
> + }
> +
> + return IRQ_HANDLED;
> +}
Hi, Bjorn,
On 11/25/25 20:37, Bjorn Helgaas wrote:
> On Wed, Nov 19, 2025 at 04:35:19PM +0200, Claudiu wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> The Renesas RZ/G3S features a PCIe IP that complies with the PCI Express
>> Base Specification 4.0 and supports speeds of up to 5 GT/s. It functions
>> only as a root complex, with a single-lane (x1) configuration. The
>> controller includes Type 1 configuration registers, as well as IP
>> specific registers (called AXI registers) required for various adjustments.
>
>> +/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
>> +static int rzg3s_pcie_root_write(struct pci_bus *bus, unsigned int devfn,
>> + int where, int size, u32 val)
>> +{
>> + struct rzg3s_pcie_host *host = bus->sysdata;
>> + int ret;
>> +
>> + /* Enable access control to the CFGU */
>> + writel_relaxed(RZG3S_PCI_PERM_CFG_HWINIT_EN,
>> + host->axi + RZG3S_PCI_PERM);
>
> I suppose this has been asked and answered already, but it's curious
> that you need this for config writes but not for reads. Obviously it
> must *work*, but it's unusual and might warrant a comment. "Access
> control" must be a hint, but only means something to experts.
After initialization, some PCI registers are read only. To enable write
access to these registers after initialization, the access control need to
be enabled.
This is the quote from the HW manual: "Some registers with the RO attribute
stated in the PCI Express Base Specification are writable at the time of
initialization.
When writing to these registers, CFG_HWINIT_EN (Permission Register
(offset: H’300) bit[2]) must be set to 1b."
>
>> + ret = pci_generic_config_write(bus, devfn, where, size, val);
>> +
>> + /* Disable access control to the CFGU */
>> + writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
>> +
>> + return ret;
>> +}
>
>> +static irqreturn_t rzg3s_pcie_msi_irq(int irq, void *data)
>> +{
>> + u8 regs = RZG3S_PCI_MSI_INT_NR / RZG3S_PCI_MSI_INT_PER_REG;
>> + DECLARE_BITMAP(bitmap, RZG3S_PCI_MSI_INT_NR);
>> + struct rzg3s_pcie_host *host = data;
>> + struct rzg3s_pcie_msi *msi = &host->msi;
>> + unsigned long bit;
>> + u32 status;
>> +
>> + status = readl_relaxed(host->axi + RZG3S_PCI_PINTRCVIS);
>> + if (!(status & RZG3S_PCI_PINTRCVIS_MSI))
>> + return IRQ_NONE;
>> +
>> + /* Clear the MSI */
>> + rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIS,
>> + RZG3S_PCI_PINTRCVIS_MSI,
>> + RZG3S_PCI_PINTRCVIS_MSI);
>
> Other writes to RZG3S_PCI_PINTRCVIS are guarded by host->hw_lock. Is this
> one safe without it?
It should be safe as RZG3S_PCI_PINTRCVIS is a R/W1C type of register.
HW manual describes R/W1C registers for PCIe as "Write-1-to-clear status
. It can be cleared to 0b by writing 1b with a readable register.
Writing 0b does not change anything."
With this, it should be safe to drop the guard from rzg3s_pcie_intx_irq_ack().
>
>> + rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSGRCVIS,
>> + RZG3S_PCI_MSGRCVIS_MRI, RZG3S_PCI_MSGRCVIS_MRI);
>> +
>> + for (u8 reg_id = 0; reg_id < regs; reg_id++) {
>> + status = readl_relaxed(host->axi + RZG3S_PCI_MSIRS(reg_id));
>> + bitmap_write(bitmap, status, reg_id * RZG3S_PCI_MSI_INT_PER_REG,
>> + RZG3S_PCI_MSI_INT_PER_REG);
>> + }
>> +
>> + for_each_set_bit(bit, bitmap, RZG3S_PCI_MSI_INT_NR) {
>> + int ret;
>> +
>> + ret = generic_handle_domain_irq(msi->domain, bit);
>> + if (ret) {
>> + u8 reg_bit = bit % RZG3S_PCI_MSI_INT_PER_REG;
>> + u8 reg_id = bit / RZG3S_PCI_MSI_INT_PER_REG;
>> +
>> + /* Unknown MSI, just clear it */
>> + writel_relaxed(BIT(reg_bit),
>> + host->axi + RZG3S_PCI_MSIRS(reg_id));
>
> Other writes to RZG3S_PCI_MSIRS are guarded by host->hw_lock. Is this
> one safe without it?
RZG3S_PCI_MSIRS is also a R/W1C type of register. With it, it should be
safe to drop the guard from rzg3s_pcie_msi_irq_ack() as well.
I'm going to prepare a follow up patch to drop the guard on
rzg3s_pcie_intx_irq_ack() and rzg3s_pcie_msi_irq_ack(). Please let me know
if you have something against.
I can also prepare a patch to detail in a comment the "enable access
control to the CFGU" operation in rzg3s_pcie_root_write(), if you prefer.
Thank you for your review,
Claudiu
On Wed, Nov 26, 2025 at 07:22:09PM +0200, Claudiu Beznea wrote:
> On 11/25/25 20:37, Bjorn Helgaas wrote:
> > On Wed, Nov 19, 2025 at 04:35:19PM +0200, Claudiu wrote:
> >> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >>
> >> The Renesas RZ/G3S features a PCIe IP that complies with the PCI Express
> >> Base Specification 4.0 and supports speeds of up to 5 GT/s. It functions
> >> only as a root complex, with a single-lane (x1) configuration. The
> >> controller includes Type 1 configuration registers, as well as IP
> >> specific registers (called AXI registers) required for various adjustments.
> >
> >> +/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
> >> +static int rzg3s_pcie_root_write(struct pci_bus *bus, unsigned int devfn,
> >> + int where, int size, u32 val)
> >> +{
> >> + struct rzg3s_pcie_host *host = bus->sysdata;
> >> + int ret;
> >> +
> >> + /* Enable access control to the CFGU */
> >> + writel_relaxed(RZG3S_PCI_PERM_CFG_HWINIT_EN,
> >> + host->axi + RZG3S_PCI_PERM);
> >
> > I suppose this has been asked and answered already, but it's curious
> > that you need this for config writes but not for reads. Obviously it
> > must *work*, but it's unusual and might warrant a comment. "Access
> > control" must be a hint, but only means something to experts.
>
> After initialization, some PCI registers are read only. To enable write
> access to these registers after initialization, the access control need to
> be enabled.
rzg3s_pcie_root_write() is a config accessor. All the users of this
expect the semantics documented by the PCI/PCIe spec. Registers
documented as read-only *should* be read-only in those situations.
BIOS and native host bridge drivers like this one may need to
initialize registers that are read-only to the OS. Some hardware
supports that initialization via device-specific addresses outside of
normal config space.
It looks like this hardware supports that initialization using the
PCI/PCIe-documented config addresses, but uses RZG3S_PCI_PERM to
control whether things are read-only or not. It's used that way in
rzg3s_pcie_host_init_port(), rzg3s_pcie_config_init(), etc.
That's perfectly fine, as long as this all happens before the OS sees
the devices. If writes to read-only registers happen *after* the OS
starts enumerating devices, then we have a problem because the OS may
cache the values of read-only registers.
Bottom line, I think:
- rzg3s_pcie_root_write() should *not* use RZG3S_PCI_PERM at all.
In fact, it should not exist, and rzg3s_pcie_root_ops.write should
be pci_generic_config_write().
- rzg3s_pcie_config_init() should use RZG3S_PCI_PERM to update
RZG3S_PCI_CFG_BARMSK00, but should *not* need it to update the
bus info because those registers are read/write per spec.
The other users look like they do need RZG3S_PCI_PERM to initialize
the Vendor and Device IDs (which are read-only per spec) and PHY
registers (which are not part of the programming model documented by
the PCIe spec).
rzg3s_pcie_config_init() looks like a problem because it's called from
rzg3s_pcie_resume_noirq(), which happens after the OS owns the PCI
hardware. The OS may have updated the bus numbers, and
rzg3s_pcie_config_init() will overwrite them with whatever it got from
DT. With a single Root Port, it's not *likely* that the OS would
change the secondary or subordinate bus numbers, but you can't assume
they are fixed.
I don't know if the hardware loses the bus numbers when it is
suspended. If it does, I think you would need to capture them during
suspend, save them somewhere like rzg3s_pcie_port, and restore them
during resume.
You should be able to verify that this is a problem by booting the
kernel, decreasing the subordinate bus number via setpci, suspending
and resuming, and checking the subordinate bus number with lspci. I
think you'll see that setpci update lost.
> >> +static irqreturn_t rzg3s_pcie_msi_irq(int irq, void *data)
> >> +{
> >> + u8 regs = RZG3S_PCI_MSI_INT_NR / RZG3S_PCI_MSI_INT_PER_REG;
> >> + DECLARE_BITMAP(bitmap, RZG3S_PCI_MSI_INT_NR);
> >> + struct rzg3s_pcie_host *host = data;
> >> + struct rzg3s_pcie_msi *msi = &host->msi;
> >> + unsigned long bit;
> >> + u32 status;
> >> +
> >> + status = readl_relaxed(host->axi + RZG3S_PCI_PINTRCVIS);
> >> + if (!(status & RZG3S_PCI_PINTRCVIS_MSI))
> >> + return IRQ_NONE;
> >> +
> >> + /* Clear the MSI */
> >> + rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIS,
> >> + RZG3S_PCI_PINTRCVIS_MSI,
> >> + RZG3S_PCI_PINTRCVIS_MSI);
> >
> > Other writes to RZG3S_PCI_PINTRCVIS are guarded by host->hw_lock. Is this
> > one safe without it?
>
> It should be safe as RZG3S_PCI_PINTRCVIS is a R/W1C type of register.
>
> HW manual describes R/W1C registers for PCIe as "Write-1-to-clear status
> . It can be cleared to 0b by writing 1b with a readable register.
> Writing 0b does not change anything."
>
> With this, it should be safe to drop the guard from rzg3s_pcie_intx_irq_ack().
>
> >
> >> + rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSGRCVIS,
> >> + RZG3S_PCI_MSGRCVIS_MRI, RZG3S_PCI_MSGRCVIS_MRI);
> >> +
> >> + for (u8 reg_id = 0; reg_id < regs; reg_id++) {
> >> + status = readl_relaxed(host->axi + RZG3S_PCI_MSIRS(reg_id));
> >> + bitmap_write(bitmap, status, reg_id * RZG3S_PCI_MSI_INT_PER_REG,
> >> + RZG3S_PCI_MSI_INT_PER_REG);
> >> + }
> >> +
> >> + for_each_set_bit(bit, bitmap, RZG3S_PCI_MSI_INT_NR) {
> >> + int ret;
> >> +
> >> + ret = generic_handle_domain_irq(msi->domain, bit);
> >> + if (ret) {
> >> + u8 reg_bit = bit % RZG3S_PCI_MSI_INT_PER_REG;
> >> + u8 reg_id = bit / RZG3S_PCI_MSI_INT_PER_REG;
> >> +
> >> + /* Unknown MSI, just clear it */
> >> + writel_relaxed(BIT(reg_bit),
> >> + host->axi + RZG3S_PCI_MSIRS(reg_id));
> >
> > Other writes to RZG3S_PCI_MSIRS are guarded by host->hw_lock. Is this
> > one safe without it?
>
> RZG3S_PCI_MSIRS is also a R/W1C type of register. With it, it should be
> safe to drop the guard from rzg3s_pcie_msi_irq_ack() as well.
>
> I'm going to prepare a follow up patch to drop the guard on
> rzg3s_pcie_intx_irq_ack() and rzg3s_pcie_msi_irq_ack(). Please let me know
> if you have something against.
Sounds good. Maybe add a comment at RZG3S_PCI_PINTRCVIS and
RZG3S_PCI_MSIRS about them being R/W1C as a hint that they don't need
locking.
> I can also prepare a patch to detail in a comment the "enable access
> control to the CFGU" operation in rzg3s_pcie_root_write(), if you prefer.
I think you should do the patch below.
And also investigate the question about resume and the bus numbers.
If it is an issue, you'll have to figure out how to fix that.
diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c
index 667e6d629474..547cbe676a25 100644
--- a/drivers/pci/controller/pcie-rzg3s-host.c
+++ b/drivers/pci/controller/pcie-rzg3s-host.c
@@ -439,28 +439,9 @@ static void __iomem *rzg3s_pcie_root_map_bus(struct pci_bus *bus,
return host->pcie + where;
}
-/* Serialized by 'pci_lock' */
-static int rzg3s_pcie_root_write(struct pci_bus *bus, unsigned int devfn,
- int where, int size, u32 val)
-{
- struct rzg3s_pcie_host *host = bus->sysdata;
- int ret;
-
- /* Enable access control to the CFGU */
- writel_relaxed(RZG3S_PCI_PERM_CFG_HWINIT_EN,
- host->axi + RZG3S_PCI_PERM);
-
- ret = pci_generic_config_write(bus, devfn, where, size, val);
-
- /* Disable access control to the CFGU */
- writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
-
- return ret;
-}
-
static struct pci_ops rzg3s_pcie_root_ops = {
.read = pci_generic_config_read,
- .write = rzg3s_pcie_root_write,
+ .write = pci_generic_config_write,
.map_bus = rzg3s_pcie_root_map_bus,
};
@@ -1065,14 +1046,14 @@ static int rzg3s_pcie_config_init(struct rzg3s_pcie_host *host)
writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00L);
writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00U);
+ /* Disable access control to the CFGU */
+ writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
+
/* Update bus info */
writeb_relaxed(primary_bus, host->pcie + PCI_PRIMARY_BUS);
writeb_relaxed(secondary_bus, host->pcie + PCI_SECONDARY_BUS);
writeb_relaxed(subordinate_bus, host->pcie + PCI_SUBORDINATE_BUS);
- /* Disable access control to the CFGU */
- writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
-
return 0;
}
Hi, Bjorn,
On 11/26/25 21:19, Bjorn Helgaas wrote:
> On Wed, Nov 26, 2025 at 07:22:09PM +0200, Claudiu Beznea wrote:
>> On 11/25/25 20:37, Bjorn Helgaas wrote:
>>> On Wed, Nov 19, 2025 at 04:35:19PM +0200, Claudiu wrote:
>>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>>>
>>>> The Renesas RZ/G3S features a PCIe IP that complies with the PCI Express
>>>> Base Specification 4.0 and supports speeds of up to 5 GT/s. It functions
>>>> only as a root complex, with a single-lane (x1) configuration. The
>>>> controller includes Type 1 configuration registers, as well as IP
>>>> specific registers (called AXI registers) required for various adjustments.
>>>
>>>> +/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
>>>> +static int rzg3s_pcie_root_write(struct pci_bus *bus, unsigned int devfn,
>>>> + int where, int size, u32 val)
>>>> +{
>>>> + struct rzg3s_pcie_host *host = bus->sysdata;
>>>> + int ret;
>>>> +
>>>> + /* Enable access control to the CFGU */
>>>> + writel_relaxed(RZG3S_PCI_PERM_CFG_HWINIT_EN,
>>>> + host->axi + RZG3S_PCI_PERM);
>>>
>>> I suppose this has been asked and answered already, but it's curious
>>> that you need this for config writes but not for reads. Obviously it
>>> must *work*, but it's unusual and might warrant a comment. "Access
>>> control" must be a hint, but only means something to experts.
>>
>> After initialization, some PCI registers are read only. To enable write
>> access to these registers after initialization, the access control need to
>> be enabled.
>
> rzg3s_pcie_root_write() is a config accessor. All the users of this
> expect the semantics documented by the PCI/PCIe spec. Registers
> documented as read-only *should* be read-only in those situations.
>
> BIOS and native host bridge drivers like this one may need to
> initialize registers that are read-only to the OS. Some hardware
> supports that initialization via device-specific addresses outside of
> normal config space.
>
> It looks like this hardware supports that initialization using the
> PCI/PCIe-documented config addresses, but uses RZG3S_PCI_PERM to
> control whether things are read-only or not. It's used that way in
> rzg3s_pcie_host_init_port(), rzg3s_pcie_config_init(), etc.
>
> That's perfectly fine, as long as this all happens before the OS sees
> the devices. If writes to read-only registers happen *after* the OS
> starts enumerating devices, then we have a problem because the OS may
> cache the values of read-only registers.
>
> Bottom line, I think:
>
> - rzg3s_pcie_root_write() should *not* use RZG3S_PCI_PERM at all.
> In fact, it should not exist, and rzg3s_pcie_root_ops.write should
> be pci_generic_config_write().
I confirm all is good by dropping rzg3s_pcie_root_write() and using
pci_generic_config_write() instead.
>
> - rzg3s_pcie_config_init() should use RZG3S_PCI_PERM to update
> RZG3S_PCI_CFG_BARMSK00, but should *not* need it to update the
> bus info because those registers are read/write per spec.
I confirm adopting this approach lead to no failures on my tests.
>
> The other users look like they do need RZG3S_PCI_PERM to initialize
> the Vendor and Device IDs (which are read-only per spec) and PHY
> registers (which are not part of the programming model documented by
> the PCIe spec).
Indeed.
>
> rzg3s_pcie_config_init() looks like a problem because it's called from
> rzg3s_pcie_resume_noirq(), which happens after the OS owns the PCI
> hardware. The OS may have updated the bus numbers, and
> rzg3s_pcie_config_init() will overwrite them with whatever it got from
> DT. With a single Root Port, it's not *likely* that the OS would
> change the secondary or subordinate bus numbers, but you can't assume
> they are fixed.
>
> I don't know if the hardware loses the bus numbers when it is
> suspended.
It can lose it as in one of the suspend modes the power to most of the SoC
components (including PCIe) is turned off.
> If it does, I think you would need to capture them during
> suspend, save them somewhere like rzg3s_pcie_port, and restore them
> during resume.
>
> You should be able to verify that this is a problem by booting the
> kernel, decreasing the subordinate bus number via setpci, suspending
> and resuming, and checking the subordinate bus number with lspci. I
> think you'll see that setpci update lost.
I updated the code as you suggested and added some prints through the code
to test it. Diff used for this is:
diff --git a/drivers/pci/access.c b/drivers/pci/access.c
index b123da16b63b..4e6198b2d436 100644
--- a/drivers/pci/access.c
+++ b/drivers/pci/access.c
@@ -114,6 +114,8 @@ int pci_generic_config_write(struct pci_bus *bus,
unsigned int devfn,
if (!addr)
return PCIBIOS_DEVICE_NOT_FOUND;
+ if (where == 0x18 || where == 0x19 || where == 0x1a)
+ pr_err("%s(): set %x=%x\n", __func__, where, val);
if (size == 1)
writeb(val, addr);
else if (size == 2)
diff --git a/drivers/pci/controller/pcie-rzg3s-host.c
b/drivers/pci/controller/pcie-rzg3s-host.c
index 667e6d629474..2670907a68d5 100644
--- a/drivers/pci/controller/pcie-rzg3s-host.c
+++ b/drivers/pci/controller/pcie-rzg3s-host.c
@@ -436,31 +436,15 @@ static void __iomem *rzg3s_pcie_root_map_bus(struct
pci_bus *bus,
if (devfn)
return NULL;
- return host->pcie + where;
-}
-
-/* Serialized by 'pci_lock' */
-static int rzg3s_pcie_root_write(struct pci_bus *bus, unsigned int devfn,
- int where, int size, u32 val)
-{
- struct rzg3s_pcie_host *host = bus->sysdata;
- int ret;
+ if (where == 0x18 || where == 0x19 || where == 0x1a)
+ dump_stack();
- /* Enable access control to the CFGU */
- writel_relaxed(RZG3S_PCI_PERM_CFG_HWINIT_EN,
- host->axi + RZG3S_PCI_PERM);
-
- ret = pci_generic_config_write(bus, devfn, where, size, val);
-
- /* Disable access control to the CFGU */
- writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
-
- return ret;
+ return host->pcie + where;
}
static struct pci_ops rzg3s_pcie_root_ops = {
.read = pci_generic_config_read,
- .write = rzg3s_pcie_root_write,
+ .write = pci_generic_config_write,
.map_bus = rzg3s_pcie_root_map_bus,
};
@@ -1065,14 +1049,18 @@ static int rzg3s_pcie_config_init(struct
rzg3s_pcie_host *host)
writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00L);
writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00U);
+ /* Disable access control to the CFGU */
+ writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
+
+ pr_err("%s(): primary=%u, secondary=%u, subordinate=%u\n", __func__,
+ primary_bus, secondary_bus,
+ subordinate_bus);
+
/* Update bus info */
writeb_relaxed(primary_bus, host->pcie + PCI_PRIMARY_BUS);
writeb_relaxed(secondary_bus, host->pcie + PCI_SECONDARY_BUS);
writeb_relaxed(subordinate_bus, host->pcie + PCI_SUBORDINATE_BUS);
- /* Disable access control to the CFGU */
- writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
-
return 0;
}
When resuming, first the RZ/G3S PCIe driver sets the primary, secondary,
subordinate to the values from the DT then pci_restore_state() writes the
values that was set with setpci.
The decoded path on top of v6.18-rc1 is:
[ 140.310728] rzg3s_pcie_root_map_bus
(drivers/pci/controller/pcie-rzg3s-host.c:440)
[ 140.310737] pci_generic_config_write (drivers/pci/access.c:114)
[ 140.310748] pci_bus_write_config_dword (drivers/pci/access.c:79
(discriminator 2))
[ 140.310758] pci_write_config_dword (drivers/pci/access.c:615)
[ 140.310766] pci_restore_config_space_range (drivers/pci/pci.c:1781
drivers/pci/pci.c:1799)
[ 140.310774] pci_restore_state.part.0 (drivers/pci/pci.c:1628
drivers/pci/pci.c:1727 drivers/pci/pci.c:1876)
[ 140.310783] pci_restore_state (drivers/pci/pci.c:1884)
The following is the console output:
root@smarc-rzg3s:~#
root@smarc-rzg3s:~# lspci
[ 28.678299] CPU: 0 UID: 0 PID: 238 Comm: lspci Not tainted
6.18.0-rc1-00007-gbd38f075378c #38 PREEMPT
[ 28.678335] Hardware name: Renesas SMARC EVK version 2 based on
r9a08g045s33 (DT)
[ 28.678342] Call trace:
[ 28.678347] show_stack+0x18/0x24 (C)
[ 28.678369] dump_stack_lvl+0x78/0x90
[ 28.678388] dump_stack+0x18/0x24
[ 28.678398] rzg3s_pcie_root_map_bus+0x44/0x5c
[ 28.678414] pci_generic_config_read+0x24/0xd8
[ 28.678430] pci_user_read_config_dword+0x78/0x11c
[ 28.678439] pci_read_config+0x1e0/0x24c
[ 28.678452] sysfs_kf_bin_read+0x7c/0xbc
[ 28.678465] kernfs_fop_read_iter+0xb0/0x1c4
[ 28.678472] vfs_read+0x214/0x2fc
[ 28.678486] __arm64_sys_pread64+0xa4/0xcc
[ 28.678495] invoke_syscall+0x48/0x10c
[ 28.678509] el0_svc_common.constprop.0+0xc0/0xe0
[ 28.678519] do_el0_svc+0x1c/0x28
[ 28.678529] el0_svc+0x34/0xf0
[ 28.678539] el0t_64_sync_handler+0xa0/0xe4
[ 28.678546] el0t_64_sync+0x198/0x19c
00:00.0 PCI bridge: Renesas Technology Corp. Device 0033
01:00.0 Non-Volatile memory controller: Transcend Information, Inc. NVMe
PCIe SSD 110S/112S/120S/MTE300S/MTE400S/MTE652T2 (DRAM-less) (rev 03)
root@smarc-rzg3s:~#
root@smarc-rzg3s:~#
root@smarc-rzg3s:~#
root@smarc-rzg3s:~#
root@smarc-rzg3s:~#
root@smarc-rzg3s:~# setpci -s 00:00.0 0x1a.b
ff
[ 41.844847] CPU: 0 UID: 0 PID: 239 Comm: setpci Not tainted
6.18.0-rc1-00007-gbd38f075378c #38 PREEMPT
[ 41.844883] Hardware name: Renesas SMARC EVK version 2 based on
r9a08g045s33 (DT)
[ 41.844890] Call trace:
[ 41.844896] show_stack+0x18/0x24 (C)
[ 41.844918] dump_stack_lvl+0x78/0x90
[ 41.844937] dump_stack+0x18/0x24
[ 41.844947] rzg3s_pcie_root_map_bus+0x44/0x5c
[ 41.844963] pci_generic_config_read+0x24/0xd8
[ 41.844980] pci_user_read_config_byte+0x70/0xfc
[ 41.844990] pci_read_config+0xf8/0x24c
[ 41.845002] sysfs_kf_bin_read+0x7c/0xbc
[ 41.845015] kernfs_fop_read_iter+0xb0/0x1c4
[ 41.845023] vfs_read+0x214/0x2fc
[ 41.845036] __arm64_sys_pread64+0xa4/0xcc
[ 41.845046] invoke_syscall+0x48/0x10c
[ 41.845060] el0_svc_common.constprop.0+0xc0/0xe0
[ 41.845070] do_el0_svc+0x1c/0x28
[ 41.845079] el0_svc+0x34/0xf0
[ 41.845089] el0t_64_sync_handler+0xa0/0xe4
[ 41.845096] el0t_64_sync+0x198/0x19c
root@smarc-rzg3s:~# setpci -s 00:00.0 0x1a.b=0x3
[ 46.429192] CPU: 0 UID: 0 PID: 240 Comm: setpci Not tainted
6.18.0-rc1-00007-gbd38f075378c #38 PREEMPT
[ 46.429229] Hardware name: Renesas SMARC EVK version 2 based on
r9a08g045s33 (DT)
[ 46.429236] Call trace:
[ 46.429241] show_stack+0x18/0x24 (C)
[ 46.429263] dump_stack_lvl+0x78/0x90
[ 46.429283] dump_stack+0x18/0x24
[ 46.429293] rzg3s_pcie_root_map_bus+0x44/0x5c
[ 46.429309] pci_generic_config_write+0x2c/0xf0
[ 46.429325] pci_user_write_config_byte+0x58/0xc8
[ 46.429334] pci_write_config+0x1ac/0x234
[ 46.429347] sysfs_kf_bin_write+0x90/0xb8
[ 46.429360] kernfs_fop_write_iter+0x128/0x1b8
[ 46.429368] vfs_write+0x2ac/0x350
[ 46.429381] __arm64_sys_pwrite64+0xa4/0xcc
[ 46.429391] invoke_syscall+0x48/0x10c
[ 46.429404] el0_svc_common.constprop.0+0xc0/0xe0
[ 46.429414] do_el0_svc+0x1c/0x28
[ 46.429423] el0_svc+0x34/0xf0
[ 46.429433] el0t_64_sync_handler+0xa0/0xe4
[ 46.429440] el0t_64_sync+0x198/0x19c
[ 46.429451] pci_generic_config_write(): set 1a=3
root@smarc-rzg3s:~#
root@smarc-rzg3s:~#
root@smarc-rzg3s:~# setpci -s 00:00.0 0x1a.b
03
[ 49.624740] CPU: 0 UID: 0 PID: 241 Comm: setpci Not tainted
6.18.0-rc1-00007-gbd38f075378c #38 PREEMPT
[ 49.624775] Hardware name: Renesas SMARC EVK version 2 based on
r9a08g045s33 (DT)
[ 49.624782] Call trace:
[ 49.624788] show_stack+0x18/0x24 (C)
[ 49.624811] dump_stack_lvl+0x78/0x90
[ 49.624831] dump_stack+0x18/0x24
[ 49.624841] rzg3s_pcie_root_map_bus+0x44/0x5c
[ 49.624857] pci_generic_config_read+0x24/0xd8
[ 49.624873] pci_user_read_config_byte+0x70/0xfc
[ 49.624883] pci_read_config+0xf8/0x24c
[ 49.624895] sysfs_kf_bin_read+0x7c/0xbc
[ 49.624908] kernfs_fop_read_iter+0xb0/0x1c4
[ 49.624915] vfs_read+0x214/0x2fc
[ 49.624928] __arm64_sys_pread64+0xa4/0xcc
[ 49.624937] invoke_syscall+0x48/0x10c
[ 49.624951] el0_svc_common.constprop.0+0xc0/0xe0
[ 49.624962] do_el0_svc+0x1c/0x28
[ 49.624971] el0_svc+0x34/0xf0
[ 49.624983] el0t_64_sync_handler+0xa0/0xe4
[ 49.624990] el0t_64_sync+0x198/0x19c
root@smarc-rzg3s:~#
root@smarc-rzg3s:~#
root@smarc-rzg3s:~#
root@smarc-rzg3s:~# echo mem > /sys/power/state
[ 54.099960] PM: suspend entry (deep)
[ 54.104583] Filesystems sync: 0.000 seconds
[ 54.124099] Freezing user space processes
[ 54.134824] Freezing user space processes completed (elapsed 0.002 seconds)
[ 54.141972] OOM killer disabled.
[ 54.145216] Freezing remaining freezable tasks
[ 54.150975] Freezing remaining freezable tasks completed (elapsed 0.001
seconds)
[ 54.192143] ravb 11c30000.ethernet end0: Link is Down
[ 54.215075] CPU: 0 UID: 0 PID: 12 Comm: kworker/u4:0 Not tainted
6.18.0-rc1-00007-gbd38f075378c #38 PREEMPT
[ 54.215111] Hardware name: Renesas SMARC EVK version 2 based on
r9a08g045s33 (DT)
[ 54.215118] Workqueue: async async_run_entry_fn
[ 54.215150] Call trace:
[ 54.215155] show_stack+0x18/0x24 (C)
[ 54.215170] dump_stack_lvl+0x78/0x90
[ 54.215189] dump_stack+0x18/0x24
[ 54.215199] rzg3s_pcie_root_map_bus+0x44/0x5c
[ 54.215213] pci_generic_config_read+0x24/0xd8
[ 54.215230] pci_bus_read_config_dword+0x7c/0xdc
[ 54.215240] pci_read_config_dword+0x30/0x4c
[ 54.215249] pci_save_state+0x34/0x1b8
[ 54.215259] pci_pm_suspend_noirq+0x1f0/0x26c
[ 54.215268] device_suspend_noirq+0x74/0x248
[ 54.215284] async_suspend_noirq+0x24/0x3c
[ 54.215293] async_run_entry_fn+0x34/0xe0
[ 54.215302] process_one_work+0x150/0x294
[ 54.215317] worker_thread+0x2dc/0x3dc
[ 54.215327] kthread+0x130/0x1fc
[ 54.215338] ret_from_fork+0x10/0x20
[ 54.216286] Disabling non-boot CPUs ...
NOTICE: BL2: v2.7(release):2.7.0/g3s_1.0.0_rc4
NOTICE: BL2: Built : 11:52:53, Feb 29 2024
NOTICE: BL2: Booting BL31
[ 54.314875] rzg3s_pcie_config_init(): primary=0, secondary=1,
subordinate=255
[ 54.412212] rzg3s-pcie-host 11e40000.pcie: PCIe link status [0x100014e]
[ 54.610904] CPU: 0 UID: 0 PID: 73 Comm: kworker/u4:4 Not tainted
6.18.0-rc1-00007-gbd38f075378c #38 PREEMPT
[ 54.610918] Hardware name: Renesas SMARC EVK version 2 based on
r9a08g045s33 (DT)
[ 54.610925] Workqueue: async async_run_entry_fn
[ 54.610956] Call trace:
[ 54.610961] show_stack+0x18/0x24 (C)
[ 54.610975] dump_stack_lvl+0x78/0x90
[ 54.610994] dump_stack+0x18/0x24
[ 54.611003] rzg3s_pcie_root_map_bus+0x44/0x5c
[ 54.611018] pci_generic_config_read+0x24/0xd8
[ 54.611034] pci_bus_read_config_dword+0x7c/0xdc
[ 54.611044] pci_read_config_dword+0x30/0x4c
[ 54.611053] pci_restore_config_space_range+0x78/0x130
[ 54.611063] pci_restore_state.part.0+0x200/0x354
[ 54.611072] pci_restore_state+0x1c/0x28
[ 54.611081] pci_pm_resume_noirq+0x108/0x184
[ 54.611089] device_resume_noirq+0x128/0x244
[ 54.611105] async_resume_noirq+0x24/0x3c
[ 54.611115] async_run_entry_fn+0x34/0xe0
[ 54.611124] process_one_work+0x150/0x294
[ 54.611139] worker_thread+0x2dc/0x3dc
[ 54.611149] kthread+0x130/0x1fc
[ 54.611160] ret_from_fork+0x10/0x20
[ 54.611175] CPU: 0 UID: 0 PID: 73 Comm: kworker/u4:4 Not tainted
6.18.0-rc1-00007-gbd38f075378c #38 PREEMPT
[ 54.611184] Hardware name: Renesas SMARC EVK version 2 based on
r9a08g045s33 (DT)
[ 54.611188] Workqueue: async async_run_entry_fn
[ 54.611197] Call trace:
[ 54.611200] show_stack+0x18/0x24 (C)
[ 54.611207] dump_stack_lvl+0x78/0x90
[ 54.611219] dump_stack+0x18/0x24
[ 54.611228] rzg3s_pcie_root_map_bus+0x44/0x5c
[ 54.611238] pci_generic_config_write+0x2c/0xf0
[ 54.611247] pci_bus_write_config_dword+0x64/0xa8
[ 54.611257] pci_write_config_dword+0x30/0x44
[ 54.611265] pci_restore_config_space_range+0xc8/0x130
[ 54.611274] pci_restore_state.part.0+0x200/0x354
[ 54.611284] pci_restore_state+0x1c/0x28
[ 54.611292] pci_pm_resume_noirq+0x108/0x184
[ 54.611299] device_resume_noirq+0x128/0x244
[ 54.611311] async_resume_noirq+0x24/0x3c
[ 54.611321] async_run_entry_fn+0x34/0xe0
[ 54.611329] process_one_work+0x150/0x294
[ 54.611340] worker_thread+0x2dc/0x3dc
[ 54.611350] kthread+0x130/0x1fc
[ 54.611359] ret_from_fork+0x10/0x20
[ 54.611368] pci_generic_config_write(): set 18=30100
[ 54.854732] nvme nvme0: 1/0/0 default/read/poll queues
[ 54.882178] Microchip KSZ9131 Gigabit PHY 11c30000.ethernet-ffffffff:07:
attached PHY driver (mii_bus:phy_addr=11c30000.ethernet-ffffffff:07, irq=57)
[ 54.966191] Microchip KSZ9131 Gigabit PHY 11c40000.ethernet-ffffffff:07:
attached PHY driver (mii_bus:phy_addr=11c40000.ethernet-ffffffff:07, irq=59)
[ 55.013453] OOM killer enabled.
[ 55.016722] Restarting tasks: Starting
[ 55.027808] Restarting tasks: Done
[ 55.035067] random: crng reseeded on system resumption
[ 55.047140] PM: suspend exit
[ 57.483265] ravb 11c30000.ethernet end0: Link is Up - 1Gbps/Full - flow
control off
root@smarc-rzg3s:~#
root@smarc-rzg3s:~#
root@smarc-rzg3s:~# setpci -s 00:00.0 0x1a.b
[ 61.102675] CPU: 0 UID: 0 PID: 247 Comm: setpci Not tainted
6.18.0-rc1-00007-gbd38f075378c #38 PREEMPT
[ 61.102710] Hardware name: Renesas SMARC EVK version 2 based on
r9a08g045s33 (DT)
[ 61.102717] Call trace:
[ 61.102722] show_stack+0x18/0x24 (C)
[ 61.102745] dump_stack_lvl+0x78/0x90
[ 61.102764] dump_stack+0x18/0x24
[ 61.102774] rzg3s_pcie_root_map_bus+0x44/0x5c
[ 61.102791] pci_generic_config_read+0x24/0xd8
[ 61.102807] pci_user_read_config_byte+0x70/0xfc
[ 61.102817] pci_read_config+0xf8/0x24c
[ 61.102829] sysfs_kf_bin_read+0x7c/0xbc
[ 61.102842] kernfs_fop_read_iter+0xb0/0x1c4
[ 61.102850] vfs_read+0x214/0x2fc
[ 61.102862] __arm64_sys_pread64+0xa4/0xcc
[ 61.102871] invoke_syscall+0x48/0x10c
[ 61.102885] el0_svc_common.constprop.0+0xc0/0xe0
[ 61.102895] do_el0_svc+0x1c/0x28
[ 61.102904] el0_svc+0x34/0xf0
[ 61.102914] el0t_64_sync_handler+0xa0/0xe4
[ 61.102921] el0t_64_sync+0x198/0x19c
03
root@smarc-rzg3s:~#
root@smarc-rzg3s:~#
If saving primary, secondary, subordinate values in suspend with the
following diff (please let me know if you want me to add the content of
struct rzg3s_pcie_suspend to the struct rzg3s_pcie_port) then the write
from pci_restore_config_space_range() is skipped:
diff --git a/drivers/pci/controller/pcie-rzg3s-host.c
b/drivers/pci/controller/pcie-rzg3s-host.c
index 2670907a68d5..0ee8ddd387ec 100644
--- a/drivers/pci/controller/pcie-rzg3s-host.c
+++ b/drivers/pci/controller/pcie-rzg3s-host.c
@@ -223,6 +223,18 @@ struct rzg3s_pcie_port {
u32 device_id;
};
+/**
+ * struct rzg3s_pcie_suspend - RZ/G3S PCIe suspend
+ * @primary_bus: Primary bus that need to restored after suspend
+ * @secondary_bus: Secondary bus that need to be restored after suspend
+ * @subordinate_bus: Subordinate bus that need to be restored after suspend
+ */
+struct rzg3s_pcie_suspend {
+ u8 primary_bus;
+ u8 secondary_bus;
+ u8 subordinate_bus;
+};
+
/**
* struct rzg3s_pcie_host - RZ/G3S PCIe data structure
* @axi: base address for AXI registers
@@ -251,6 +263,7 @@ struct rzg3s_pcie_host {
struct rzg3s_pcie_msi msi;
struct rzg3s_pcie_port port;
raw_spinlock_t hw_lock;
+ struct rzg3s_pcie_suspend suspend;
int intx_irqs[PCI_NUM_INTX];
int max_link_speed;
};
@@ -1026,20 +1039,21 @@ static int rzg3s_pcie_set_max_link_speed(struct
rzg3s_pcie_host *host)
static int rzg3s_pcie_config_init(struct rzg3s_pcie_host *host)
{
struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host);
+ struct rzg3s_pcie_suspend *suspend = &host->suspend;
struct resource_entry *ft;
struct resource *bus;
- u8 subordinate_bus;
- u8 secondary_bus;
- u8 primary_bus;
ft = resource_list_first_type(&bridge->windows, IORESOURCE_BUS);
if (!ft)
return -ENODEV;
bus = ft->res;
- primary_bus = bus->start;
- secondary_bus = bus->start + 1;
- subordinate_bus = bus->end;
+ if (!suspend->primary_bus)
+ suspend->primary_bus = bus->start;
+ if (!suspend->secondary_bus)
+ suspend->secondary_bus = bus->start + 1;
+ if (!suspend->subordinate_bus)
+ suspend->subordinate_bus = bus->end;
/* Enable access control to the CFGU */
writel_relaxed(RZG3S_PCI_PERM_CFG_HWINIT_EN,
@@ -1053,13 +1067,14 @@ static int rzg3s_pcie_config_init(struct
rzg3s_pcie_host *host)
writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
pr_err("%s(): primary=%u, secondary=%u, subordinate=%u\n", __func__,
- primary_bus, secondary_bus,
- subordinate_bus);
+ suspend->primary_bus, suspend->secondary_bus,
+ suspend->subordinate_bus);
/* Update bus info */
- writeb_relaxed(primary_bus, host->pcie + PCI_PRIMARY_BUS);
- writeb_relaxed(secondary_bus, host->pcie + PCI_SECONDARY_BUS);
- writeb_relaxed(subordinate_bus, host->pcie + PCI_SUBORDINATE_BUS);
+ writeb_relaxed(suspend->primary_bus, host->pcie + PCI_PRIMARY_BUS);
+ writeb_relaxed(suspend->secondary_bus, host->pcie + PCI_SECONDARY_BUS);
+ writeb_relaxed(suspend->subordinate_bus,
+ host->pcie + PCI_SUBORDINATE_BUS);
return 0;
}
@@ -1622,10 +1637,15 @@ static int rzg3s_pcie_suspend_noirq(struct device *dev)
{
struct rzg3s_pcie_host *host = dev_get_drvdata(dev);
const struct rzg3s_pcie_soc_data *data = host->data;
+ struct rzg3s_pcie_suspend *suspend = &host->suspend;
struct rzg3s_pcie_port *port = &host->port;
struct regmap *sysc = host->sysc;
int ret;
+ suspend->primary_bus = readl_relaxed(host->pcie + PCI_PRIMARY_BUS);
+ suspend->secondary_bus = readb_relaxed(host->pcie + PCI_SECONDARY_BUS);
+ suspend->subordinate_bus = readb_relaxed(host->pcie +
PCI_SUBORDINATE_BUS);
+
ret = pm_runtime_put_sync(dev);
if (ret)
return ret;
With this the write from pci_restore_config_space_range() is skipped as it
was already updated by the driver. Below is the console output:
root@smarc-rzg3s:~# lspci
[ 42.932043] CPU: 0 UID: 0 PID: 240 Comm: lspci Not tainted
6.18.0-rc1-00008-gcb1b33f1dd58 #39 PREEMPT
[ 42.932080] Hardware name: Renesas SMARC EVK version 2 based on
r9a08g045s33 (DT)
[ 42.932086] Call trace:
[ 42.932091] show_stack+0x18/0x24 (C)
[ 42.932113] dump_stack_lvl+0x78/0x90
[ 42.932132] dump_stack+0x18/0x24
[ 42.932142] rzg3s_pcie_root_map_bus+0x44/0x5c
[ 42.932158] pci_generic_config_read+0x24/0xd8
[ 42.932174] pci_user_read_config_dword+0x78/0x11c
[ 42.932184] pci_read_config+0x1e0/0x24c
[ 42.932197] sysfs_kf_bin_read+0x7c/0xbc
[ 42.932209] kernfs_fop_read_iter+0xb0/0x1c4
[ 42.932217] vfs_read+0x214/0x2fc
[ 42.932230] __arm64_sys_pread64+0xa4/0xcc
[ 42.932239] invoke_syscall+0x48/0x10c
[ 42.932253] el0_svc_common.constprop.0+0xc0/0xe0
[ 42.932263] do_el0_svc+0x1c/0x28
[ 42.932273] el0_svc+0x34/0xf0
[ 42.932283] el0t_64_sync_handler+0xa0/0xe4
[ 42.932290] el0t_64_sync+0x198/0x19c
00:00.0 PCI bridge: Renesas Technology Corp. Device 0033
01:00.0 Non-Volatile memory controller: Transcend Information, Inc. NVMe
PCIe SSD 110S/112S/120S/MTE300S/MTE400S/MTE652T2 (DRAM-less) (rev 03)
root@smarc-rzg3s:~#
root@smarc-rzg3s:~#
root@smarc-rzg3s:~#
root@smarc-rzg3s:~#
root@smarc-rzg3s:~# setpci -s 00:00.0 0x1a.b
ff
[ 45.989548] CPU: 0 UID: 0 PID: 241 Comm: setpci Not tainted
6.18.0-rc1-00008-gcb1b33f1dd58 #39 PREEMPT
[ 45.989584] Hardware name: Renesas SMARC EVK version 2 based on
r9a08g045s33 (DT)
[ 45.989590] Call trace:
[ 45.989596] show_stack+0x18/0x24 (C)
[ 45.989619] dump_stack_lvl+0x78/0x90
[ 45.989638] dump_stack+0x18/0x24
[ 45.989648] rzg3s_pcie_root_map_bus+0x44/0x5c
[ 45.989664] pci_generic_config_read+0x24/0xd8
[ 45.989680] pci_user_read_config_byte+0x70/0xfc
[ 45.989690] pci_read_config+0xf8/0x24c
[ 45.989703] sysfs_kf_bin_read+0x7c/0xbc
[ 45.989715] kernfs_fop_read_iter+0xb0/0x1c4
[ 45.989723] vfs_read+0x214/0x2fc
[ 45.989736] __arm64_sys_pread64+0xa4/0xcc
[ 45.989745] invoke_syscall+0x48/0x10c
[ 45.989758] el0_svc_common.constprop.0+0xc0/0xe0
[ 45.989768] do_el0_svc+0x1c/0x28
[ 45.989777] el0_svc+0x34/0xf0
[ 45.989787] el0t_64_sync_handler+0xa0/0xe4
[ 45.989795] el0t_64_sync+0x198/0x19c
root@smarc-rzg3s:~#
root@smarc-rzg3s:~#
root@smarc-rzg3s:~#
root@smarc-rzg3s:~# setpci -s 00:00.0 0x1a.b=0x3
[ 51.231700] CPU: 0 UID: 0 PID: 242 Comm: setpci Not tainted
6.18.0-rc1-00008-gcb1b33f1dd58 #39 PREEMPT
[ 51.231736] Hardware name: Renesas SMARC EVK version 2 based on
r9a08g045s33 (DT)
[ 51.231743] Call trace:
[ 51.231747] show_stack+0x18/0x24 (C)
[ 51.231770] dump_stack_lvl+0x78/0x90
[ 51.231789] dump_stack+0x18/0x24
[ 51.231799] rzg3s_pcie_root_map_bus+0x44/0x5c
[ 51.231815] pci_generic_config_write+0x2c/0xf0
[ 51.231832] pci_user_write_config_byte+0x58/0xc8
[ 51.231841] pci_write_config+0x1ac/0x234
[ 51.231854] sysfs_kf_bin_write+0x90/0xb8
[ 51.231866] kernfs_fop_write_iter+0x128/0x1b8
[ 51.231874] vfs_write+0x2ac/0x350
[ 51.231886] __arm64_sys_pwrite64+0xa4/0xcc
[ 51.231896] invoke_syscall+0x48/0x10c
[ 51.231909] el0_svc_common.constprop.0+0xc0/0xe0
[ 51.231919] do_el0_svc+0x1c/0x28
[ 51.231929] el0_svc+0x34/0xf0
[ 51.231939] el0t_64_sync_handler+0xa0/0xe4
[ 51.231947] el0t_64_sync+0x198/0x19c
[ 51.231957] pci_generic_config_write(): set 1a=3
root@smarc-rzg3s:~#
root@smarc-rzg3s:~#
root@smarc-rzg3s:~#
root@smarc-rzg3s:~# setpci -s 00:00.0 0x1a.b
03
[ 81.058526] CPU: 0 UID: 0 PID: 243 Comm: setpci Not tainted
6.18.0-rc1-00008-gcb1b33f1dd58 #39 PREEMPT
[ 81.058563] Hardware name: Renesas SMARC EVK version 2 based on
r9a08g045s33 (DT)
[ 81.058570] Call trace:
[ 81.058574] show_stack+0x18/0x24 (C)
[ 81.058598] dump_stack_lvl+0x78/0x90
[ 81.058617] dump_stack+0x18/0x24
[ 81.058626] rzg3s_pcie_root_map_bus+0x44/0x5c
[ 81.058642] pci_generic_config_read+0x24/0xd8
[ 81.058658] pci_user_read_config_byte+0x70/0xfc
[ 81.058668] pci_read_config+0xf8/0x24c
[ 81.058680] sysfs_kf_bin_read+0x7c/0xbc
[ 81.058692] kernfs_fop_read_iter+0xb0/0x1c4
[ 81.058700] vfs_read+0x214/0x2fc
[ 81.058712] __arm64_sys_pread64+0xa4/0xcc
[ 81.058721] invoke_syscall+0x48/0x10c
[ 81.058735] el0_svc_common.constprop.0+0xc0/0xe0
[ 81.058745] do_el0_svc+0x1c/0x28
[ 81.058755] el0_svc+0x34/0xf0
[ 81.058764] el0t_64_sync_handler+0xa0/0xe4
[ 81.058771] el0t_64_sync+0x198/0x19c
root@smarc-rzg3s:~#
root@smarc-rzg3s:~#
root@smarc-rzg3s:~#
root@smarc-rzg3s:~#
root@smarc-rzg3s:~# echo mem > /sys/power/state
[ 93.245556] PM: suspend entry (deep)
[ 93.254834] Filesystems sync: 0.005 seconds
[ 93.271372] Freezing user space processes
[ 93.277350] Freezing user space processes completed (elapsed 0.005 seconds)
[ 93.284385] OOM killer disabled.
[ 93.287641] Freezing remaining freezable tasks
[ 93.293449] Freezing remaining freezable tasks completed (elapsed 0.001
seconds)
[ 93.338170] ravb 11c30000.ethernet end0: Link is Down
[ 93.361712] CPU: 0 UID: 0 PID: 12 Comm: kworker/u4:0 Not tainted
6.18.0-rc1-00008-gcb1b33f1dd58 #39 PREEMPT
[ 93.361748] Hardware name: Renesas SMARC EVK version 2 based on
r9a08g045s33 (DT)
[ 93.361755] Workqueue: async async_run_entry_fn
[ 93.361787] Call trace:
[ 93.361792] show_stack+0x18/0x24 (C)
[ 93.361807] dump_stack_lvl+0x78/0x90
[ 93.361826] dump_stack+0x18/0x24
[ 93.361836] rzg3s_pcie_root_map_bus+0x44/0x5c
[ 93.361851] pci_generic_config_read+0x24/0xd8
[ 93.361868] pci_bus_read_config_dword+0x7c/0xdc
[ 93.361877] pci_read_config_dword+0x30/0x4c
[ 93.361886] pci_save_state+0x34/0x1b8
[ 93.361897] pci_pm_suspend_noirq+0x1f0/0x26c
[ 93.361905] device_suspend_noirq+0x74/0x248
[ 93.361922] async_suspend_noirq+0x24/0x3c
[ 93.361931] async_run_entry_fn+0x34/0xe0
[ 93.361941] process_one_work+0x150/0x294
[ 93.361956] worker_thread+0x2dc/0x3dc
[ 93.361965] kthread+0x130/0x1fc
[ 93.361977] ret_from_fork+0x10/0x20
[ 93.450364] Disabling non-boot CPUs ...
NOTICE: BL2: v2.7(release):2.7.0/g3s_1.0.0_rc4
NOTICE: BL2: Built : 11:52:53, Feb 29 2024
NOTICE: BL2: Booting BL31
[ 93.462060] rzg3s_pcie_config_init(): primary=0, secondary=1, subordinate=3
[ 93.559227] rzg3s-pcie-host 11e40000.pcie: PCIe link status [0x100014e]
[ 93.758234] CPU: 0 UID: 0 PID: 76 Comm: kworker/u4:5 Not tainted
6.18.0-rc1-00008-gcb1b33f1dd58 #39 PREEMPT
[ 93.758248] Hardware name: Renesas SMARC EVK version 2 based on
r9a08g045s33 (DT)
[ 93.758256] Workqueue: async async_run_entry_fn
[ 93.758287] Call trace:
[ 93.758292] show_stack+0x18/0x24 (C)
[ 93.758306] dump_stack_lvl+0x78/0x90
[ 93.758325] dump_stack+0x18/0x24
[ 93.758335] rzg3s_pcie_root_map_bus+0x44/0x5c
[ 93.758350] pci_generic_config_read+0x24/0xd8
[ 93.758366] pci_bus_read_config_dword+0x7c/0xdc
[ 93.758375] pci_read_config_dword+0x30/0x4c
[ 93.758384] pci_restore_config_space_range+0x78/0x130
[ 93.758394] pci_restore_state.part.0+0x200/0x354
[ 93.758403] pci_restore_state+0x1c/0x28
[ 93.758411] pci_pm_resume_noirq+0x108/0x184
[ 93.758420] device_resume_noirq+0x128/0x244
[ 93.758435] async_resume_noirq+0x24/0x3c
[ 93.758445] async_run_entry_fn+0x34/0xe0
[ 93.758454] process_one_work+0x150/0x294
[ 93.758469] worker_thread+0x2dc/0x3dc
[ 93.758479] kthread+0x130/0x1fc
[ 93.758490] ret_from_fork+0x10/0x20
[ 93.900233] nvme nvme0: 1/0/0 default/read/poll queues
[ 93.929276] Microchip KSZ9131 Gigabit PHY 11c30000.ethernet-ffffffff:07:
attached PHY driver (mii_bus:phy_addr=11c30000.ethernet-ffffffff:07, irq=57)
[ 94.013294] Microchip KSZ9131 Gigabit PHY 11c40000.ethernet-ffffffff:07:
attached PHY driver (mii_bus:phy_addr=11c40000.ethernet-ffffffff:07, irq=59)
[ 94.060633] OOM killer enabled.
[ 94.063832] Restarting tasks: Starting
[ 94.074838] Restarting tasks: Done
[ 94.082174] random: crng reseeded on system resumption
[ 94.094271] PM: suspend exit
[ 96.530340] ravb 11c30000.ethernet end0: Link is Up - 1Gbps/Full - flow
control off
root@smarc-rzg3s:~#
root@smarc-rzg3s:~#
root@smarc-rzg3s:~#
root@smarc-rzg3s:~# setpci -s 00:00.0 0x1a.b
03[ 104.629484] CPU: 0 UID: 0 PID: 249 Comm: setpci Not tainted
6.18.0-rc1-00008-gcb1b33f1dd58 #39 PREEMPT
[ 104.629521] Hardware name: Renesas SMARC EVK version 2 based on
r9a08g045s33 (DT)
[ 104.629529] Call trace:
[ 104.629534] show_stack+0x18/0x24 (C)
[ 104.629557] dump_stack_lvl+0x78/0x90
[ 104.629576] dump_stack+0x18/0x24
[ 104.629586] rzg3s_pcie_root_map_bus+0x44/0x5c
[ 104.629602] pci_generic_config_read+0x24/0xd8
[ 104.629618] pci_user_read_config_byte+0x70/0xfc
[ 104.629627] pci_read_config+0xf8/0x24c
[ 104.629640] sysfs_kf_bin_read+0x7c/0xbc
[ 104.629652] kernfs_fop_read_iter+0xb0/0x1c4
[ 104.629660] vfs_read+0x214/0x2fc
[ 104.629673] __arm64_sys_pread64+0xa4/0xcc
[ 104.629683] invoke_syscall+0x48/0x10c
[ 104.629696] el0_svc_common.constprop.0+0xc0/0xe0
[ 104.629706] do_el0_svc+0x1c/0x28
[ 104.629716] el0_svc+0x34/0xf0
[ 104.629725] el0t_64_sync_handler+0xa0/0xe4
[ 104.629733] el0t_64_sync+0x198/0x19c
root@smarc-rzg3s:~#
root@smarc-rzg3s:~#
root@smarc-rzg3s:~#
root@smarc-rzg3s:~# setpci -s 00:00.0 0x1a.b
03
[ 107.216490] CPU: 0 UID: 0 PID: 250 Comm: setpci Not tainted
6.18.0-rc1-00008-gcb1b33f1dd58 #39 PREEMPT
[ 107.216527] Hardware name: Renesas SMARC EVK version 2 based on
r9a08g045s33 (DT)
[ 107.216534] Call trace:
[ 107.216538] show_stack+0x18/0x24 (C)
[ 107.216562] dump_stack_lvl+0x78/0x90
[ 107.216581] dump_stack+0x18/0x24
[ 107.216591] rzg3s_pcie_root_map_bus+0x44/0x5c
[ 107.216607] pci_generic_config_read+0x24/0xd8
[ 107.216623] pci_user_read_config_byte+0x70/0xfc
[ 107.216633] pci_read_config+0xf8/0x24c
[ 107.216645] sysfs_kf_bin_read+0x7c/0xbc
[ 107.216658] kernfs_fop_read_iter+0xb0/0x1c4
[ 107.216666] vfs_read+0x214/0x2fc
[ 107.216679] __arm64_sys_pread64+0xa4/0xcc
[ 107.216688] invoke_syscall+0x48/0x10c
[ 107.216702] el0_svc_common.constprop.0+0xc0/0xe0
[ 107.216712] do_el0_svc+0x1c/0x28
[ 107.216721] el0_svc+0x34/0xf0
[ 107.216731] el0t_64_sync_handler+0xa0/0xe4
[ 107.216739] el0t_64_sync+0x198/0x19c
root@smarc-rzg3s:~#
root@smarc-rzg3s:~#
Could you please let me know if we should rely on pci_restore_state() to
restore this data or we should do it in driver?
>
>>>> +static irqreturn_t rzg3s_pcie_msi_irq(int irq, void *data)
>>>> +{
>>>> + u8 regs = RZG3S_PCI_MSI_INT_NR / RZG3S_PCI_MSI_INT_PER_REG;
>>>> + DECLARE_BITMAP(bitmap, RZG3S_PCI_MSI_INT_NR);
>>>> + struct rzg3s_pcie_host *host = data;
>>>> + struct rzg3s_pcie_msi *msi = &host->msi;
>>>> + unsigned long bit;
>>>> + u32 status;
>>>> +
>>>> + status = readl_relaxed(host->axi + RZG3S_PCI_PINTRCVIS);
>>>> + if (!(status & RZG3S_PCI_PINTRCVIS_MSI))
>>>> + return IRQ_NONE;
>>>> +
>>>> + /* Clear the MSI */
>>>> + rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIS,
>>>> + RZG3S_PCI_PINTRCVIS_MSI,
>>>> + RZG3S_PCI_PINTRCVIS_MSI);
>>>
>>> Other writes to RZG3S_PCI_PINTRCVIS are guarded by host->hw_lock. Is this
>>> one safe without it?
>>
>> It should be safe as RZG3S_PCI_PINTRCVIS is a R/W1C type of register.
>>
>> HW manual describes R/W1C registers for PCIe as "Write-1-to-clear status
>> . It can be cleared to 0b by writing 1b with a readable register.
>> Writing 0b does not change anything."
>>
>> With this, it should be safe to drop the guard from rzg3s_pcie_intx_irq_ack().
>>
>>>
>>>> + rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSGRCVIS,
>>>> + RZG3S_PCI_MSGRCVIS_MRI, RZG3S_PCI_MSGRCVIS_MRI);
>>>> +
>>>> + for (u8 reg_id = 0; reg_id < regs; reg_id++) {
>>>> + status = readl_relaxed(host->axi + RZG3S_PCI_MSIRS(reg_id));
>>>> + bitmap_write(bitmap, status, reg_id * RZG3S_PCI_MSI_INT_PER_REG,
>>>> + RZG3S_PCI_MSI_INT_PER_REG);
>>>> + }
>>>> +
>>>> + for_each_set_bit(bit, bitmap, RZG3S_PCI_MSI_INT_NR) {
>>>> + int ret;
>>>> +
>>>> + ret = generic_handle_domain_irq(msi->domain, bit);
>>>> + if (ret) {
>>>> + u8 reg_bit = bit % RZG3S_PCI_MSI_INT_PER_REG;
>>>> + u8 reg_id = bit / RZG3S_PCI_MSI_INT_PER_REG;
>>>> +
>>>> + /* Unknown MSI, just clear it */
>>>> + writel_relaxed(BIT(reg_bit),
>>>> + host->axi + RZG3S_PCI_MSIRS(reg_id));
>>>
>>> Other writes to RZG3S_PCI_MSIRS are guarded by host->hw_lock. Is this
>>> one safe without it?
>>
>> RZG3S_PCI_MSIRS is also a R/W1C type of register. With it, it should be
>> safe to drop the guard from rzg3s_pcie_msi_irq_ack() as well.
>>
>> I'm going to prepare a follow up patch to drop the guard on
>> rzg3s_pcie_intx_irq_ack() and rzg3s_pcie_msi_irq_ack(). Please let me know
>> if you have something against.
>
> Sounds good. Maybe add a comment at RZG3S_PCI_PINTRCVIS and
> RZG3S_PCI_MSIRS about them being R/W1C as a hint that they don't need
> locking.
Sure!
>
>> I can also prepare a patch to detail in a comment the "enable access
>> control to the CFGU" operation in rzg3s_pcie_root_write(), if you prefer.
>
> I think you should do the patch below.
Sure!
Thank you for your review,
Claudiu
>
> And also investigate the question about resume and the bus numbers.
> If it is an issue, you'll have to figure out how to fix that.
>
> diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c
> index 667e6d629474..547cbe676a25 100644
> --- a/drivers/pci/controller/pcie-rzg3s-host.c
> +++ b/drivers/pci/controller/pcie-rzg3s-host.c
> @@ -439,28 +439,9 @@ static void __iomem *rzg3s_pcie_root_map_bus(struct pci_bus *bus,
> return host->pcie + where;
> }
>
> -/* Serialized by 'pci_lock' */
> -static int rzg3s_pcie_root_write(struct pci_bus *bus, unsigned int devfn,
> - int where, int size, u32 val)
> -{
> - struct rzg3s_pcie_host *host = bus->sysdata;
> - int ret;
> -
> - /* Enable access control to the CFGU */
> - writel_relaxed(RZG3S_PCI_PERM_CFG_HWINIT_EN,
> - host->axi + RZG3S_PCI_PERM);
> -
> - ret = pci_generic_config_write(bus, devfn, where, size, val);
> -
> - /* Disable access control to the CFGU */
> - writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
> -
> - return ret;
> -}
> -
> static struct pci_ops rzg3s_pcie_root_ops = {
> .read = pci_generic_config_read,
> - .write = rzg3s_pcie_root_write,
> + .write = pci_generic_config_write,
> .map_bus = rzg3s_pcie_root_map_bus,
> };
>
> @@ -1065,14 +1046,14 @@ static int rzg3s_pcie_config_init(struct rzg3s_pcie_host *host)
> writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00L);
> writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00U);
>
> + /* Disable access control to the CFGU */
> + writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
> +
> /* Update bus info */
> writeb_relaxed(primary_bus, host->pcie + PCI_PRIMARY_BUS);
> writeb_relaxed(secondary_bus, host->pcie + PCI_SECONDARY_BUS);
> writeb_relaxed(subordinate_bus, host->pcie + PCI_SUBORDINATE_BUS);
>
> - /* Disable access control to the CFGU */
> - writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
> -
> return 0;
> }
>
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