arch/arm/boot/dts/microchip/lan966x-pcb8290.dts | 1 + 1 file changed, 1 insertion(+)
The problem is that the MDIO controller can't detect any of the PHYs.
The reason is that the lan966x is not pulling high the GPIO 53 that is
connected to the PHYs reset GPIO. Without doing this the PHYs are kept
in reset. The mdio controller framework has the possiblity to control a
GPIO to release the reset of the PHYs. So take advantage of this and set
line to be high before accessing the PHYs.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
---
arch/arm/boot/dts/microchip/lan966x-pcb8290.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/microchip/lan966x-pcb8290.dts b/arch/arm/boot/dts/microchip/lan966x-pcb8290.dts
index 3b7577e48b467..50bd29572f3ed 100644
--- a/arch/arm/boot/dts/microchip/lan966x-pcb8290.dts
+++ b/arch/arm/boot/dts/microchip/lan966x-pcb8290.dts
@@ -54,6 +54,7 @@ udc_pins: ucd-pins {
&mdio0 {
pinctrl-0 = <&miim_a_pins>;
pinctrl-names = "default";
+ reset-gpios = <&gpio 53 GPIO_ACTIVE_LOW>;
status = "okay";
ext_phy0: ethernet-phy@7 {
--
2.34.1
On 11/19/25 15:47, Horatiu Vultur wrote: > The problem is that the MDIO controller can't detect any of the PHYs. > The reason is that the lan966x is not pulling high the GPIO 53 that is > connected to the PHYs reset GPIO. Without doing this the PHYs are kept > in reset. The mdio controller framework has the possiblity to control a > GPIO to release the reset of the PHYs. So take advantage of this and set > line to be high before accessing the PHYs. > > Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Applied to at91-fixes, thanks!
On 11/19/25 15:47, Horatiu Vultur wrote:
> The problem is that the MDIO controller can't detect any of the PHYs.
> The reason is that the lan966x is not pulling high the GPIO 53 that is
> connected to the PHYs reset GPIO. Without doing this the PHYs are kept
> in reset. The mdio controller framework has the possiblity to control a
s/possiblity/possibility
I can adjust it while applying
> GPIO to release the reset of the PHYs. So take advantage of this and set
> line to be high before accessing the PHYs.
>
> Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
> ---
> arch/arm/boot/dts/microchip/lan966x-pcb8290.dts | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/boot/dts/microchip/lan966x-pcb8290.dts b/arch/arm/boot/dts/microchip/lan966x-pcb8290.dts
> index 3b7577e48b467..50bd29572f3ed 100644
> --- a/arch/arm/boot/dts/microchip/lan966x-pcb8290.dts
> +++ b/arch/arm/boot/dts/microchip/lan966x-pcb8290.dts
> @@ -54,6 +54,7 @@ udc_pins: ucd-pins {
> &mdio0 {
> pinctrl-0 = <&miim_a_pins>;
> pinctrl-names = "default";
> + reset-gpios = <&gpio 53 GPIO_ACTIVE_LOW>;
> status = "okay";
>
> ext_phy0: ethernet-phy@7 {
On Wed, Nov 19, 2025 at 02:47:50PM +0100, Horatiu Vultur wrote:
> The problem is that the MDIO controller can't detect any of the PHYs.
> The reason is that the lan966x is not pulling high the GPIO 53 that is
> connected to the PHYs reset GPIO. Without doing this the PHYs are kept
> in reset. The mdio controller framework has the possiblity to control a
> GPIO to release the reset of the PHYs. So take advantage of this and set
> line to be high before accessing the PHYs.
>
> Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
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