Each ENETC has a set of external MDIO registers to access its external
PHY based on its port EMDIO bus, these registers are used for MDIO bus
access, such as setting the PHY address, PHY register address and value,
read or write operations, C22 or C45 format, etc. The base address of
this set of registers has been modified in ENETC v4 and is different
from that in ENETC v1. So the base address needs to be updated so that
ENETC v4 can use port MDIO to manage its own external PHY.

Additionally, if ENETC has the PCS layer, it also has a set of internal
MDIO registers for managing its on-die PHY (PCS/Serdes). The base address
of this set of registers is also different from that of ENETC v1, so the
base address also needs to be updated so that ENETC v4 can support the
management of on-die PHY through the internal MDIO bus.

Signed-off-by: Wei Fang <wei.fang@nxp.com>
---
 drivers/net/ethernet/freescale/enetc/enetc4_hw.h   |  6 ++++++
 .../net/ethernet/freescale/enetc/enetc_pf_common.c | 14 ++++++++++++--
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/freescale/enetc/enetc4_hw.h b/drivers/net/ethernet/freescale/enetc/enetc4_hw.h
index ebea4298791c..3ed0f7a02767 100644
--- a/drivers/net/ethernet/freescale/enetc/enetc4_hw.h
+++ b/drivers/net/ethernet/freescale/enetc/enetc4_hw.h
@@ -170,6 +170,9 @@
 /* Port MAC 0/1 Maximum Frame Length Register */
 #define ENETC4_PM_MAXFRM(mac)		(0x5014 + (mac) * 0x400)
 
+/* Port internal MDIO base address, use to access PCS */
+#define ENETC4_PM_IMDIO_BASE		0x5030
+
 /* Port MAC 0/1 Pause Quanta Register */
 #define ENETC4_PM_PAUSE_QUANTA(mac)	(0x5054 + (mac) * 0x400)
 
@@ -198,6 +201,9 @@
 #define   SSP_1G			2
 #define  PM_IF_MODE_ENA			BIT(15)
 
+/* Port external MDIO Base address, use to access off-chip PHY */
+#define ENETC4_EMDIO_BASE		0x5c00
+
 /**********************ENETC Pseudo MAC port registers************************/
 /* Port pseudo MAC receive octets counter (64-bit) */
 #define ENETC4_PPMROCR			0x5080
diff --git a/drivers/net/ethernet/freescale/enetc/enetc_pf_common.c b/drivers/net/ethernet/freescale/enetc/enetc_pf_common.c
index 9c634205e2a7..76263b8566bb 100644
--- a/drivers/net/ethernet/freescale/enetc/enetc_pf_common.c
+++ b/drivers/net/ethernet/freescale/enetc/enetc_pf_common.c
@@ -176,7 +176,12 @@ static int enetc_mdio_probe(struct enetc_pf *pf, struct device_node *np)
 	bus->parent = dev;
 	mdio_priv = bus->priv;
 	mdio_priv->hw = &pf->si->hw;
-	mdio_priv->mdio_base = ENETC_EMDIO_BASE;
+
+	if (is_enetc_rev1(pf->si))
+		mdio_priv->mdio_base = ENETC_EMDIO_BASE;
+	else
+		mdio_priv->mdio_base = ENETC4_EMDIO_BASE;
+
 	snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(dev));
 
 	err = of_mdiobus_register(bus, np);
@@ -221,7 +226,12 @@ static int enetc_imdio_create(struct enetc_pf *pf)
 	bus->phy_mask = ~0;
 	mdio_priv = bus->priv;
 	mdio_priv->hw = &pf->si->hw;
-	mdio_priv->mdio_base = ENETC_PM_IMDIO_BASE;
+
+	if (is_enetc_rev1(pf->si))
+		mdio_priv->mdio_base = ENETC_PM_IMDIO_BASE;
+	else
+		mdio_priv->mdio_base = ENETC4_PM_IMDIO_BASE;
+
 	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev));
 
 	err = mdiobus_register(bus);
-- 
2.34.1

On 11/19/25 11:25 AM, Wei Fang wrote:
> Each ENETC has a set of external MDIO registers to access its external
> PHY based on its port EMDIO bus, these registers are used for MDIO bus
> access, such as setting the PHY address, PHY register address and value,
> read or write operations, C22 or C45 format, etc. The base address of
> this set of registers has been modified in ENETC v4 and is different
> from that in ENETC v1. So the base address needs to be updated so that
> ENETC v4 can use port MDIO to manage its own external PHY.
> 
> Additionally, if ENETC has the PCS layer, it also has a set of internal
> MDIO registers for managing its on-die PHY (PCS/Serdes). The base address
> of this set of registers is also different from that of ENETC v1, so the
> base address also needs to be updated so that ENETC v4 can support the
> management of on-die PHY through the internal MDIO bus.
> 
> Signed-off-by: Wei Fang <wei.fang@nxp.com>

Andrew, it's not clear to me if you are with the current patch version,
could you please chime-in?

Thanks,

Paolo

On Tue, Nov 25, 2025 at 11:05:06AM +0100, Paolo Abeni wrote:
> On 11/19/25 11:25 AM, Wei Fang wrote:
> > Each ENETC has a set of external MDIO registers to access its external
> > PHY based on its port EMDIO bus, these registers are used for MDIO bus
> > access, such as setting the PHY address, PHY register address and value,
> > read or write operations, C22 or C45 format, etc. The base address of
> > this set of registers has been modified in ENETC v4 and is different
> > from that in ENETC v1. So the base address needs to be updated so that
> > ENETC v4 can use port MDIO to manage its own external PHY.
> > 
> > Additionally, if ENETC has the PCS layer, it also has a set of internal
> > MDIO registers for managing its on-die PHY (PCS/Serdes). The base address
> > of this set of registers is also different from that of ENETC v1, so the
> > base address also needs to be updated so that ENETC v4 can support the
> > management of on-die PHY through the internal MDIO bus.
> > 
> > Signed-off-by: Wei Fang <wei.fang@nxp.com>
> 
> Andrew, it's not clear to me if you are with the current patch version,
> could you please chime-in?

I say merge it. I'm not sure it is the best of architectures, but i
don't have time to dig into all the details in order to suggest
something better.

	Andrew