drivers/clk/renesas/r9a09g077-cpg.c | 189 +++++++++++++++++++++++++++- 1 file changed, 188 insertions(+), 1 deletion(-)
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add core clocks and module clock definitions required by the xSPI
(Expanded SPI) IP on the R9A09G077 SoC.
Define the new SCKCR fields FSELXSPI0/FSELXSPI1 and DIVSEL_XSPI0/1 and
add two new core clocks XSPI_CLK0 and XSPI_CLK1. The xSPI block uses
PCLKH as its bus clock (use as module clock parent) while the operation
clock (XSPI_CLKn) is derived from PLL4. To support this arrangement
provide mux/div selectors and divider tables for the supported
XSPI operating rates.
Add CLK_TYPE_RZT2H_FSELXSPI to implement a custom divider/mux clock
where the determine_rate() callback enforces the hardware constraint:
when the parent output is 600MHz only dividers 8 and 16 are valid,
whereas for 800MHz operation the full divider set (6,8,16,32,64) may
be used. The custom determine_rate() picks the best parent/divider pair
to match the requested rate and programs the appropriate SCKCR fields.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Note this patch was originally part of series [0] as rest of the series
is already merged into linux-next, sending only this patch as v3.
[0] https://lore.kernel.org/all/20251028165127.991351-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
v2->v3:
- Dropped check for 800/600 MHz in
r9a09g077_cpg_fselxspi_determine_rate() instead compared divider values 3/4.
- Sorted pll4d1_div3/pll4d1_div4 definitions to be with other pll4d1 dividers.
- Dropped u64 caset in DIV_ROUND_UP_ULL()
- Hardcoded the maxdiv when no dividers are found
- Rebaesed to latest -next
v1->v2:
- Added custom divider clock type for XSPI clocks to enforce hardware
constraints on supported operating rates.
---
drivers/clk/renesas/r9a09g077-cpg.c | 189 +++++++++++++++++++++++++++-
1 file changed, 188 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a09g077-cpg.c
index fb6cc94d08a1..7367a713991d 100644
--- a/drivers/clk/renesas/r9a09g077-cpg.c
+++ b/drivers/clk/renesas/r9a09g077-cpg.c
@@ -11,6 +11,8 @@
#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>
+#include <linux/math.h>
+#include <linux/types.h>
#include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
#include <dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h>
@@ -58,11 +60,16 @@
#define DIVSCI3ASYNC CONF_PACK(SCKCR3, 12, 2)
#define DIVSCI4ASYNC CONF_PACK(SCKCR3, 14, 2)
+#define FSELXSPI0 CONF_PACK(SCKCR, 0, 3)
+#define FSELXSPI1 CONF_PACK(SCKCR, 8, 3)
+#define DIVSEL_XSPI0 CONF_PACK(SCKCR, 6, 1)
+#define DIVSEL_XSPI1 CONF_PACK(SCKCR, 14, 1)
#define SEL_PLL CONF_PACK(SCKCR, 22, 1)
enum rzt2h_clk_types {
CLK_TYPE_RZT2H_DIV = CLK_TYPE_CUSTOM, /* Clock with divider */
CLK_TYPE_RZT2H_MUX, /* Clock with clock source selector */
+ CLK_TYPE_RZT2H_FSELXSPI, /* Clock with FSELXSPIn source selector */
};
#define DEF_DIV(_name, _id, _parent, _conf, _dtable) \
@@ -72,10 +79,13 @@ enum rzt2h_clk_types {
DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_MUX, .conf = _conf, \
.parent_names = _parent_names, .num_parents = _num_parents, \
.flag = 0, .mux_flags = _mux_flags)
+#define DEF_DIV_FSELXSPI(_name, _id, _parent, _conf, _dtable) \
+ DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_FSELXSPI, .conf = _conf, \
+ .parent = _parent, .dtable = _dtable, .flag = 0)
enum clk_ids {
/* Core Clock Outputs exported to DT */
- LAST_DT_CORE_CLK = R9A09G077_ETCLKE,
+ LAST_DT_CORE_CLK = R9A09G077_XSPI_CLK1,
/* External Input Clocks */
CLK_EXTAL,
@@ -91,6 +101,8 @@ enum clk_ids {
CLK_SEL_CLK_PLL2,
CLK_SEL_CLK_PLL4,
CLK_PLL4D1,
+ CLK_PLL4D1_DIV3,
+ CLK_PLL4D1_DIV4,
CLK_SCI0ASYNC,
CLK_SCI1ASYNC,
CLK_SCI2ASYNC,
@@ -101,6 +113,8 @@ enum clk_ids {
CLK_SPI1ASYNC,
CLK_SPI2ASYNC,
CLK_SPI3ASYNC,
+ CLK_DIVSELXSPI0_SCKCR,
+ CLK_DIVSELXSPI1_SCKCR,
/* Module Clocks */
MOD_CLK_BASE,
@@ -112,6 +126,15 @@ static const struct clk_div_table dtable_1_2[] = {
{0, 0},
};
+static const struct clk_div_table dtable_6_8_16_32_64[] = {
+ {6, 64},
+ {5, 32},
+ {4, 16},
+ {3, 8},
+ {2, 6},
+ {0, 0},
+};
+
static const struct clk_div_table dtable_24_25_30_32[] = {
{0, 32},
{1, 30},
@@ -126,6 +149,7 @@ static const char * const sel_clk_pll0[] = { ".loco", ".pll0" };
static const char * const sel_clk_pll1[] = { ".loco", ".pll1" };
static const char * const sel_clk_pll2[] = { ".loco", ".pll2" };
static const char * const sel_clk_pll4[] = { ".loco", ".pll4" };
+static const char * const sel_clk_pll4d1_div3_div4[] = { ".pll4d1_div3", ".pll4d1_div4" };
static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = {
/* External Clock Inputs */
@@ -148,6 +172,8 @@ static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = {
sel_clk_pll4, ARRAY_SIZE(sel_clk_pll4), CLK_MUX_READ_ONLY),
DEF_FIXED(".pll4d1", CLK_PLL4D1, CLK_SEL_CLK_PLL4, 1, 1),
+ DEF_FIXED(".pll4d1_div3", CLK_PLL4D1_DIV3, CLK_PLL4D1, 3, 1),
+ DEF_FIXED(".pll4d1_div4", CLK_PLL4D1_DIV4, CLK_PLL4D1, 4, 1),
DEF_DIV(".sci0async", CLK_SCI0ASYNC, CLK_PLL4D1, DIVSCI0ASYNC,
dtable_24_25_30_32),
DEF_DIV(".sci1async", CLK_SCI1ASYNC, CLK_PLL4D1, DIVSCI1ASYNC,
@@ -170,6 +196,13 @@ static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = {
DEF_DIV(".spi3async", CLK_SPI3ASYNC, CLK_PLL4D1, DIVSPI3ASYNC,
dtable_24_25_30_32),
+ DEF_MUX(".divselxspi0", CLK_DIVSELXSPI0_SCKCR, DIVSEL_XSPI0,
+ sel_clk_pll4d1_div3_div4,
+ ARRAY_SIZE(sel_clk_pll4d1_div3_div4), 0),
+ DEF_MUX(".divselxspi1", CLK_DIVSELXSPI1_SCKCR, DIVSEL_XSPI1,
+ sel_clk_pll4d1_div3_div4,
+ ARRAY_SIZE(sel_clk_pll4d1_div3_div4), 0),
+
/* Core output clk */
DEF_DIV("CA55C0", R9A09G077_CLK_CA55C0, CLK_SEL_CLK_PLL0, DIVCA55C0,
dtable_1_2),
@@ -194,9 +227,15 @@ static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = {
DEF_FIXED("ETCLKC", R9A09G077_ETCLKC, CLK_SEL_CLK_PLL1, 10, 1),
DEF_FIXED("ETCLKD", R9A09G077_ETCLKD, CLK_SEL_CLK_PLL1, 20, 1),
DEF_FIXED("ETCLKE", R9A09G077_ETCLKE, CLK_SEL_CLK_PLL1, 40, 1),
+ DEF_DIV_FSELXSPI("XSPI_CLK0", R9A09G077_XSPI_CLK0, CLK_DIVSELXSPI0_SCKCR,
+ FSELXSPI0, dtable_6_8_16_32_64),
+ DEF_DIV_FSELXSPI("XSPI_CLK1", R9A09G077_XSPI_CLK1, CLK_DIVSELXSPI1_SCKCR,
+ FSELXSPI1, dtable_6_8_16_32_64),
};
static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = {
+ DEF_MOD("xspi0", 4, R9A09G077_CLK_PCLKH),
+ DEF_MOD("xspi1", 5, R9A09G077_CLK_PCLKH),
DEF_MOD("sci0fck", 8, CLK_SCI0ASYNC),
DEF_MOD("sci1fck", 9, CLK_SCI1ASYNC),
DEF_MOD("sci2fck", 10, CLK_SCI2ASYNC),
@@ -284,6 +323,152 @@ r9a09g077_cpg_mux_clk_register(struct device *dev,
return clk_hw->clk;
}
+static unsigned int r9a09g077_cpg_fselxspi_get_divider(struct clk_hw *hw, unsigned long rate,
+ unsigned int num_parents)
+{
+ struct clk_fixed_factor *ff;
+ struct clk_hw *parent_hw;
+ unsigned long best_rate;
+ unsigned int i;
+
+ for (i = 0; i < num_parents; i++) {
+ parent_hw = clk_hw_get_parent_by_index(hw, i);
+ best_rate = clk_hw_round_rate(parent_hw, rate);
+
+ if (best_rate == rate) {
+ ff = to_clk_fixed_factor(parent_hw);
+ return ff->div;
+ }
+ }
+
+ /* No parent could provide the exact rate - this should not happen */
+ return 0;
+}
+
+static int r9a09g077_cpg_fselxspi_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+ unsigned long parent_rate, best = 0, now;
+ const struct clk_div_table *clkt;
+ unsigned long rate = req->rate;
+ unsigned int num_parents;
+ unsigned int divselxspi;
+ unsigned int div = 0;
+
+ if (!rate)
+ rate = 1;
+
+ /* Get the number of parents for FSELXSPIn */
+ num_parents = clk_hw_get_num_parents(req->best_parent_hw);
+
+ for (clkt = divider->table; clkt->div; clkt++) {
+ parent_rate = clk_hw_round_rate(req->best_parent_hw, rate * clkt->div);
+ /* Skip if parent can't provide any valid rate */
+ if (!parent_rate)
+ continue;
+
+ /* Determine which DIVSELXSPIn divider (3 or 4) provides this parent_rate */
+ divselxspi = r9a09g077_cpg_fselxspi_get_divider(req->best_parent_hw, parent_rate,
+ num_parents);
+ if (!divselxspi)
+ continue;
+
+ /*
+ * DIVSELXSPIx supports 800MHz and 600MHz operation.
+ * When divselxspi is 4 (600MHz operation), only FSELXSPIn dividers of 8 and 16
+ * are supported. Otherwise, when divselxspi is 3 (800MHz operation),
+ * dividers of 6, 8, 16, 32, and 64 are supported. This check ensures that
+ * FSELXSPIx is set correctly based on hardware limitations.
+ */
+ if (divselxspi == 4 && (clkt->div != 8 && clkt->div != 16))
+ continue;
+ now = DIV_ROUND_UP_ULL(parent_rate, clkt->div);
+ if (abs(rate - now) < abs(rate - best)) {
+ div = clkt->div;
+ best = now;
+ req->best_parent_rate = parent_rate;
+ }
+ }
+
+ if (!div) {
+ req->best_parent_rate = clk_hw_round_rate(req->best_parent_hw, 1);
+ divselxspi = r9a09g077_cpg_fselxspi_get_divider(req->best_parent_hw,
+ req->best_parent_rate,
+ num_parents);
+ /* default to divider 3 which will result DIVSELXSPIn = 800 MHz */
+ if (!divselxspi)
+ divselxspi = 3;
+ /*
+ * Use the maximum divider based on the parent clock rate:
+ * - 64 when DIVSELXSPIx is 800 MHz (divider = 3)
+ * - 16 when DIVSELXSPIx is 600 MHz (divider = 4)
+ */
+ if (divselxspi == 3)
+ div = 64;
+ else
+ div = 16;
+ }
+
+ req->rate = DIV_ROUND_UP_ULL(req->best_parent_rate, div);
+
+ return 0;
+}
+
+static struct clk * __init
+r9a09g077_cpg_fselxspi_div_clk_register(struct device *dev,
+ const struct cpg_core_clk *core,
+ void __iomem *addr,
+ struct cpg_mssr_pub *pub)
+{
+ static struct clk_ops *xspi_div_ops;
+ struct clk_init_data init = {};
+ const struct clk *parent;
+ const char *parent_name;
+ struct clk_divider *div;
+ struct clk_hw *hw;
+ int ret;
+
+ parent = pub->clks[core->parent];
+ if (IS_ERR(parent))
+ return ERR_CAST(parent);
+
+ div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
+ if (!div)
+ return ERR_PTR(-ENOMEM);
+
+ if (!xspi_div_ops) {
+ xspi_div_ops = devm_kzalloc(dev, sizeof(*xspi_div_ops), GFP_KERNEL);
+ if (!xspi_div_ops)
+ return ERR_PTR(-ENOMEM);
+ memcpy(xspi_div_ops, &clk_divider_ops,
+ sizeof(const struct clk_ops));
+ xspi_div_ops->determine_rate = r9a09g077_cpg_fselxspi_determine_rate;
+ }
+
+ parent_name = __clk_get_name(parent);
+ init.name = core->name;
+ init.ops = xspi_div_ops;
+ init.flags = CLK_SET_RATE_PARENT;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+
+ div->reg = addr;
+ div->shift = GET_SHIFT(core->conf);
+ div->width = GET_WIDTH(core->conf);
+ div->flags = core->flag;
+ div->lock = &pub->rmw_lock;
+ div->hw.init = &init;
+ div->table = core->dtable;
+
+ hw = &div->hw;
+ ret = devm_clk_hw_register(dev, hw);
+ if (ret)
+ return ERR_PTR(ret);
+
+ return hw->clk;
+}
+
static struct clk * __init
r9a09g077_cpg_clk_register(struct device *dev, const struct cpg_core_clk *core,
const struct cpg_mssr_info *info,
@@ -298,6 +483,8 @@ r9a09g077_cpg_clk_register(struct device *dev, const struct cpg_core_clk *core,
return r9a09g077_cpg_div_clk_register(dev, core, addr, pub);
case CLK_TYPE_RZT2H_MUX:
return r9a09g077_cpg_mux_clk_register(dev, core, addr, pub);
+ case CLK_TYPE_RZT2H_FSELXSPI:
+ return r9a09g077_cpg_fselxspi_div_clk_register(dev, core, addr, pub);
default:
return ERR_PTR(-EINVAL);
}
--
2.51.2Hi Prabhakar,
On Mon, 17 Nov 2025 at 21:57, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add core clocks and module clock definitions required by the xSPI
> (Expanded SPI) IP on the R9A09G077 SoC.
>
> Define the new SCKCR fields FSELXSPI0/FSELXSPI1 and DIVSEL_XSPI0/1 and
> add two new core clocks XSPI_CLK0 and XSPI_CLK1. The xSPI block uses
> PCLKH as its bus clock (use as module clock parent) while the operation
> clock (XSPI_CLKn) is derived from PLL4. To support this arrangement
> provide mux/div selectors and divider tables for the supported
> XSPI operating rates.
>
> Add CLK_TYPE_RZT2H_FSELXSPI to implement a custom divider/mux clock
> where the determine_rate() callback enforces the hardware constraint:
> when the parent output is 600MHz only dividers 8 and 16 are valid,
> whereas for 800MHz operation the full divider set (6,8,16,32,64) may
> be used. The custom determine_rate() picks the best parent/divider pair
> to match the requested rate and programs the appropriate SCKCR fields.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> Note this patch was originally part of series [0] as rest of the series
> is already merged into linux-next, sending only this patch as v3.
> [0] https://lore.kernel.org/all/20251028165127.991351-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
>
> v2->v3:
> - Dropped check for 800/600 MHz in
> r9a09g077_cpg_fselxspi_determine_rate() instead compared divider values 3/4.
> - Sorted pll4d1_div3/pll4d1_div4 definitions to be with other pll4d1 dividers.
> - Dropped u64 caset in DIV_ROUND_UP_ULL()
> - Hardcoded the maxdiv when no dividers are found
> - Rebaesed to latest -next
Thanks for the update!
> --- a/drivers/clk/renesas/r9a09g077-cpg.c
> +++ b/drivers/clk/renesas/r9a09g077-cpg.c
> @@ -58,11 +60,16 @@
> #define DIVSCI3ASYNC CONF_PACK(SCKCR3, 12, 2)
> #define DIVSCI4ASYNC CONF_PACK(SCKCR3, 14, 2)
>
> +#define FSELXSPI0 CONF_PACK(SCKCR, 0, 3)
> +#define FSELXSPI1 CONF_PACK(SCKCR, 8, 3)
> +#define DIVSEL_XSPI0 CONF_PACK(SCKCR, 6, 1)
> +#define DIVSEL_XSPI1 CONF_PACK(SCKCR, 14, 1)
> #define SEL_PLL CONF_PACK(SCKCR, 22, 1)
Moving all of these up while applying, so SCKCR comes before SCKCR2.
>
> enum rzt2h_clk_types {
> CLK_TYPE_RZT2H_DIV = CLK_TYPE_CUSTOM, /* Clock with divider */
> CLK_TYPE_RZT2H_MUX, /* Clock with clock source selector */
> + CLK_TYPE_RZT2H_FSELXSPI, /* Clock with FSELXSPIn source selector */
> };
>
> #define DEF_DIV(_name, _id, _parent, _conf, _dtable) \
> @@ -148,6 +172,8 @@ static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = {
> sel_clk_pll4, ARRAY_SIZE(sel_clk_pll4), CLK_MUX_READ_ONLY),
>
> DEF_FIXED(".pll4d1", CLK_PLL4D1, CLK_SEL_CLK_PLL4, 1, 1),
> + DEF_FIXED(".pll4d1_div3", CLK_PLL4D1_DIV3, CLK_PLL4D1, 3, 1),
> + DEF_FIXED(".pll4d1_div4", CLK_PLL4D1_DIV4, CLK_PLL4D1, 4, 1),
Inserting a blank line.
> DEF_DIV(".sci0async", CLK_SCI0ASYNC, CLK_PLL4D1, DIVSCI0ASYNC,
> dtable_24_25_30_32),
> DEF_DIV(".sci1async", CLK_SCI1ASYNC, CLK_PLL4D1, DIVSCI1ASYNC,
> +static int r9a09g077_cpg_fselxspi_determine_rate(struct clk_hw *hw,
> + struct clk_rate_request *req)
> +{
> + struct clk_divider *divider = to_clk_divider(hw);
> + unsigned long parent_rate, best = 0, now;
> + const struct clk_div_table *clkt;
> + unsigned long rate = req->rate;
> + unsigned int num_parents;
> + unsigned int divselxspi;
> + unsigned int div = 0;
> +
> + if (!rate)
> + rate = 1;
> +
> + /* Get the number of parents for FSELXSPIn */
> + num_parents = clk_hw_get_num_parents(req->best_parent_hw);
> +
> + for (clkt = divider->table; clkt->div; clkt++) {
> + parent_rate = clk_hw_round_rate(req->best_parent_hw, rate * clkt->div);
> + /* Skip if parent can't provide any valid rate */
> + if (!parent_rate)
> + continue;
> +
> + /* Determine which DIVSELXSPIn divider (3 or 4) provides this parent_rate */
> + divselxspi = r9a09g077_cpg_fselxspi_get_divider(req->best_parent_hw, parent_rate,
> + num_parents);
> + if (!divselxspi)
> + continue;
> +
> + /*
> + * DIVSELXSPIx supports 800MHz and 600MHz operation.
> + * When divselxspi is 4 (600MHz operation), only FSELXSPIn dividers of 8 and 16
> + * are supported. Otherwise, when divselxspi is 3 (800MHz operation),
> + * dividers of 6, 8, 16, 32, and 64 are supported. This check ensures that
> + * FSELXSPIx is set correctly based on hardware limitations.
> + */
> + if (divselxspi == 4 && (clkt->div != 8 && clkt->div != 16))
> + continue;
Inserting a blank line.
> + now = DIV_ROUND_UP_ULL(parent_rate, clkt->div);
> + if (abs(rate - now) < abs(rate - best)) {
> + div = clkt->div;
> + best = now;
> + req->best_parent_rate = parent_rate;
> + }
> + }
> +
> + if (!div) {
> + req->best_parent_rate = clk_hw_round_rate(req->best_parent_hw, 1);
> + divselxspi = r9a09g077_cpg_fselxspi_get_divider(req->best_parent_hw,
> + req->best_parent_rate,
> + num_parents);
> + /* default to divider 3 which will result DIVSELXSPIn = 800 MHz */
> + if (!divselxspi)
> + divselxspi = 3;
Inserting a blank line.
> + /*
> + * Use the maximum divider based on the parent clock rate:
> + * - 64 when DIVSELXSPIx is 800 MHz (divider = 3)
> + * - 16 when DIVSELXSPIx is 600 MHz (divider = 4)
> + */
> + if (divselxspi == 3)
> + div = 64;
> + else
> + div = 16;
Replacing by:
div = divselxspi == 3 ? 64 : 16;
> + }
> +
> + req->rate = DIV_ROUND_UP_ULL(req->best_parent_rate, div);
> +
> + return 0;
> +}
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk for v6.20, with the above changes.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Geert,
On Mon, Nov 24, 2025 at 4:14 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Mon, 17 Nov 2025 at 21:57, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add core clocks and module clock definitions required by the xSPI
> > (Expanded SPI) IP on the R9A09G077 SoC.
> >
> > Define the new SCKCR fields FSELXSPI0/FSELXSPI1 and DIVSEL_XSPI0/1 and
> > add two new core clocks XSPI_CLK0 and XSPI_CLK1. The xSPI block uses
> > PCLKH as its bus clock (use as module clock parent) while the operation
> > clock (XSPI_CLKn) is derived from PLL4. To support this arrangement
> > provide mux/div selectors and divider tables for the supported
> > XSPI operating rates.
> >
> > Add CLK_TYPE_RZT2H_FSELXSPI to implement a custom divider/mux clock
> > where the determine_rate() callback enforces the hardware constraint:
> > when the parent output is 600MHz only dividers 8 and 16 are valid,
> > whereas for 800MHz operation the full divider set (6,8,16,32,64) may
> > be used. The custom determine_rate() picks the best parent/divider pair
> > to match the requested rate and programs the appropriate SCKCR fields.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > Note this patch was originally part of series [0] as rest of the series
> > is already merged into linux-next, sending only this patch as v3.
> > [0] https://lore.kernel.org/all/20251028165127.991351-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> >
> > v2->v3:
> > - Dropped check for 800/600 MHz in
> > r9a09g077_cpg_fselxspi_determine_rate() instead compared divider values 3/4.
> > - Sorted pll4d1_div3/pll4d1_div4 definitions to be with other pll4d1 dividers.
> > - Dropped u64 caset in DIV_ROUND_UP_ULL()
> > - Hardcoded the maxdiv when no dividers are found
> > - Rebaesed to latest -next
>
> Thanks for the update!
>
> > --- a/drivers/clk/renesas/r9a09g077-cpg.c
> > +++ b/drivers/clk/renesas/r9a09g077-cpg.c
>
> > @@ -58,11 +60,16 @@
> > #define DIVSCI3ASYNC CONF_PACK(SCKCR3, 12, 2)
> > #define DIVSCI4ASYNC CONF_PACK(SCKCR3, 14, 2)
> >
> > +#define FSELXSPI0 CONF_PACK(SCKCR, 0, 3)
> > +#define FSELXSPI1 CONF_PACK(SCKCR, 8, 3)
> > +#define DIVSEL_XSPI0 CONF_PACK(SCKCR, 6, 1)
> > +#define DIVSEL_XSPI1 CONF_PACK(SCKCR, 14, 1)
> > #define SEL_PLL CONF_PACK(SCKCR, 22, 1)
>
> Moving all of these up while applying, so SCKCR comes before SCKCR2.
>
> >
> > enum rzt2h_clk_types {
> > CLK_TYPE_RZT2H_DIV = CLK_TYPE_CUSTOM, /* Clock with divider */
> > CLK_TYPE_RZT2H_MUX, /* Clock with clock source selector */
> > + CLK_TYPE_RZT2H_FSELXSPI, /* Clock with FSELXSPIn source selector */
> > };
> >
> > #define DEF_DIV(_name, _id, _parent, _conf, _dtable) \
>
>
> > @@ -148,6 +172,8 @@ static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = {
> > sel_clk_pll4, ARRAY_SIZE(sel_clk_pll4), CLK_MUX_READ_ONLY),
> >
> > DEF_FIXED(".pll4d1", CLK_PLL4D1, CLK_SEL_CLK_PLL4, 1, 1),
> > + DEF_FIXED(".pll4d1_div3", CLK_PLL4D1_DIV3, CLK_PLL4D1, 3, 1),
> > + DEF_FIXED(".pll4d1_div4", CLK_PLL4D1_DIV4, CLK_PLL4D1, 4, 1),
>
> Inserting a blank line.
>
> > DEF_DIV(".sci0async", CLK_SCI0ASYNC, CLK_PLL4D1, DIVSCI0ASYNC,
> > dtable_24_25_30_32),
> > DEF_DIV(".sci1async", CLK_SCI1ASYNC, CLK_PLL4D1, DIVSCI1ASYNC,
>
> > +static int r9a09g077_cpg_fselxspi_determine_rate(struct clk_hw *hw,
> > + struct clk_rate_request *req)
> > +{
> > + struct clk_divider *divider = to_clk_divider(hw);
> > + unsigned long parent_rate, best = 0, now;
> > + const struct clk_div_table *clkt;
> > + unsigned long rate = req->rate;
> > + unsigned int num_parents;
> > + unsigned int divselxspi;
> > + unsigned int div = 0;
> > +
> > + if (!rate)
> > + rate = 1;
> > +
> > + /* Get the number of parents for FSELXSPIn */
> > + num_parents = clk_hw_get_num_parents(req->best_parent_hw);
> > +
> > + for (clkt = divider->table; clkt->div; clkt++) {
> > + parent_rate = clk_hw_round_rate(req->best_parent_hw, rate * clkt->div);
> > + /* Skip if parent can't provide any valid rate */
> > + if (!parent_rate)
> > + continue;
> > +
> > + /* Determine which DIVSELXSPIn divider (3 or 4) provides this parent_rate */
> > + divselxspi = r9a09g077_cpg_fselxspi_get_divider(req->best_parent_hw, parent_rate,
> > + num_parents);
> > + if (!divselxspi)
> > + continue;
> > +
> > + /*
> > + * DIVSELXSPIx supports 800MHz and 600MHz operation.
> > + * When divselxspi is 4 (600MHz operation), only FSELXSPIn dividers of 8 and 16
> > + * are supported. Otherwise, when divselxspi is 3 (800MHz operation),
> > + * dividers of 6, 8, 16, 32, and 64 are supported. This check ensures that
> > + * FSELXSPIx is set correctly based on hardware limitations.
> > + */
> > + if (divselxspi == 4 && (clkt->div != 8 && clkt->div != 16))
> > + continue;
>
> Inserting a blank line.
>
> > + now = DIV_ROUND_UP_ULL(parent_rate, clkt->div);
> > + if (abs(rate - now) < abs(rate - best)) {
> > + div = clkt->div;
> > + best = now;
> > + req->best_parent_rate = parent_rate;
> > + }
> > + }
> > +
> > + if (!div) {
> > + req->best_parent_rate = clk_hw_round_rate(req->best_parent_hw, 1);
> > + divselxspi = r9a09g077_cpg_fselxspi_get_divider(req->best_parent_hw,
> > + req->best_parent_rate,
> > + num_parents);
> > + /* default to divider 3 which will result DIVSELXSPIn = 800 MHz */
> > + if (!divselxspi)
> > + divselxspi = 3;
>
> Inserting a blank line.
>
> > + /*
> > + * Use the maximum divider based on the parent clock rate:
> > + * - 64 when DIVSELXSPIx is 800 MHz (divider = 3)
> > + * - 16 when DIVSELXSPIx is 600 MHz (divider = 4)
> > + */
> > + if (divselxspi == 3)
> > + div = 64;
> > + else
> > + div = 16;
>
> Replacing by:
>
> div = divselxspi == 3 ? 64 : 16;
>
> > + }
> > +
> > + req->rate = DIV_ROUND_UP_ULL(req->best_parent_rate, div);
> > +
> > + return 0;
> > +}
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> i.e. will queue in renesas-clk for v6.20, with the above changes.
>
Thank you for taking care of the changes.
Cheers,
Prabhakar
Hi Prabhakar,
kernel test robot noticed the following build errors:
[auto build test ERROR on geert-renesas-drivers/renesas-clk]
[also build test ERROR on next-20251118]
[cannot apply to clk/clk-next linus/master v6.18-rc6]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Prabhakar/clk-renesas-r9a09g077-Add-xSPI-core-and-module-clocks/20251118-045831
base: https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git renesas-clk
patch link: https://lore.kernel.org/r/20251117205627.39376-1-prabhakar.mahadev-lad.rj%40bp.renesas.com
patch subject: [PATCH v3] clk: renesas: r9a09g077: Add xSPI core and module clocks
config: riscv-randconfig-002-20251118 (https://download.01.org/0day-ci/archive/20251118/202511181733.mdvppqVT-lkp@intel.com/config)
compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project 0bba1e76581bad04e7d7f09f5115ae5e2989e0d9)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251118/202511181733.mdvppqVT-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202511181733.mdvppqVT-lkp@intel.com/
All errors (new ones prefixed by >>):
>> drivers/clk/renesas/r9a09g077-cpg.c:88:21: error: use of undeclared identifier 'R9A09G077_XSPI_CLK1'
88 | LAST_DT_CORE_CLK = R9A09G077_XSPI_CLK1,
| ^~~~~~~~~~~~~~~~~~~
>> drivers/clk/renesas/r9a09g077-cpg.c:230:32: error: use of undeclared identifier 'R9A09G077_XSPI_CLK0'
230 | DEF_DIV_FSELXSPI("XSPI_CLK0", R9A09G077_XSPI_CLK0, CLK_DIVSELXSPI0_SCKCR,
| ^~~~~~~~~~~~~~~~~~~
drivers/clk/renesas/r9a09g077-cpg.c:232:32: error: use of undeclared identifier 'R9A09G077_XSPI_CLK1'
232 | DEF_DIV_FSELXSPI("XSPI_CLK1", R9A09G077_XSPI_CLK1, CLK_DIVSELXSPI1_SCKCR,
| ^~~~~~~~~~~~~~~~~~~
>> drivers/clk/renesas/r9a09g077-cpg.c:496:19: error: invalid application of 'sizeof' to an incomplete type 'const struct cpg_core_clk[]'
496 | .num_core_clks = ARRAY_SIZE(r9a09g077_core_clks),
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/array_size.h:11:32: note: expanded from macro 'ARRAY_SIZE'
11 | #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]) + __must_be_array(arr))
| ^~~~~
4 errors generated.
Kconfig warnings: (for reference only)
WARNING: unmet direct dependencies detected for ARCH_HAS_ELF_CORE_EFLAGS
Depends on [n]: BINFMT_ELF [=y] && ELF_CORE [=n]
Selected by [y]:
- RISCV [=y]
vim +/R9A09G077_XSPI_CLK1 +88 drivers/clk/renesas/r9a09g077-cpg.c
74
75 #define DEF_DIV(_name, _id, _parent, _conf, _dtable) \
76 DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_DIV, .conf = _conf, \
77 .parent = _parent, .dtable = _dtable, .flag = 0)
78 #define DEF_MUX(_name, _id, _conf, _parent_names, _num_parents, _mux_flags) \
79 DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_MUX, .conf = _conf, \
80 .parent_names = _parent_names, .num_parents = _num_parents, \
81 .flag = 0, .mux_flags = _mux_flags)
82 #define DEF_DIV_FSELXSPI(_name, _id, _parent, _conf, _dtable) \
83 DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_FSELXSPI, .conf = _conf, \
84 .parent = _parent, .dtable = _dtable, .flag = 0)
85
86 enum clk_ids {
87 /* Core Clock Outputs exported to DT */
> 88 LAST_DT_CORE_CLK = R9A09G077_XSPI_CLK1,
89
90 /* External Input Clocks */
91 CLK_EXTAL,
92
93 /* Internal Core Clocks */
94 CLK_LOCO,
95 CLK_PLL0,
96 CLK_PLL1,
97 CLK_PLL2,
98 CLK_PLL4,
99 CLK_SEL_CLK_PLL0,
100 CLK_SEL_CLK_PLL1,
101 CLK_SEL_CLK_PLL2,
102 CLK_SEL_CLK_PLL4,
103 CLK_PLL4D1,
104 CLK_PLL4D1_DIV3,
105 CLK_PLL4D1_DIV4,
106 CLK_SCI0ASYNC,
107 CLK_SCI1ASYNC,
108 CLK_SCI2ASYNC,
109 CLK_SCI3ASYNC,
110 CLK_SCI4ASYNC,
111 CLK_SCI5ASYNC,
112 CLK_SPI0ASYNC,
113 CLK_SPI1ASYNC,
114 CLK_SPI2ASYNC,
115 CLK_SPI3ASYNC,
116 CLK_DIVSELXSPI0_SCKCR,
117 CLK_DIVSELXSPI1_SCKCR,
118
119 /* Module Clocks */
120 MOD_CLK_BASE,
121 };
122
123 static const struct clk_div_table dtable_1_2[] = {
124 {0, 2},
125 {1, 1},
126 {0, 0},
127 };
128
129 static const struct clk_div_table dtable_6_8_16_32_64[] = {
130 {6, 64},
131 {5, 32},
132 {4, 16},
133 {3, 8},
134 {2, 6},
135 {0, 0},
136 };
137
138 static const struct clk_div_table dtable_24_25_30_32[] = {
139 {0, 32},
140 {1, 30},
141 {2, 25},
142 {3, 24},
143 {0, 0},
144 };
145
146 /* Mux clock tables */
147
148 static const char * const sel_clk_pll0[] = { ".loco", ".pll0" };
149 static const char * const sel_clk_pll1[] = { ".loco", ".pll1" };
150 static const char * const sel_clk_pll2[] = { ".loco", ".pll2" };
151 static const char * const sel_clk_pll4[] = { ".loco", ".pll4" };
152 static const char * const sel_clk_pll4d1_div3_div4[] = { ".pll4d1_div3", ".pll4d1_div4" };
153
154 static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = {
155 /* External Clock Inputs */
156 DEF_INPUT("extal", CLK_EXTAL),
157
158 /* Internal Core Clocks */
159 DEF_RATE(".loco", CLK_LOCO, 1000 * 1000),
160 DEF_FIXED(".pll0", CLK_PLL0, CLK_EXTAL, 1, 48),
161 DEF_FIXED(".pll1", CLK_PLL1, CLK_EXTAL, 1, 40),
162 DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 1, 32),
163 DEF_FIXED(".pll4", CLK_PLL4, CLK_EXTAL, 1, 96),
164
165 DEF_MUX(".sel_clk_pll0", CLK_SEL_CLK_PLL0, SEL_PLL,
166 sel_clk_pll0, ARRAY_SIZE(sel_clk_pll0), CLK_MUX_READ_ONLY),
167 DEF_MUX(".sel_clk_pll1", CLK_SEL_CLK_PLL1, SEL_PLL,
168 sel_clk_pll1, ARRAY_SIZE(sel_clk_pll1), CLK_MUX_READ_ONLY),
169 DEF_MUX(".sel_clk_pll2", CLK_SEL_CLK_PLL2, SEL_PLL,
170 sel_clk_pll2, ARRAY_SIZE(sel_clk_pll2), CLK_MUX_READ_ONLY),
171 DEF_MUX(".sel_clk_pll4", CLK_SEL_CLK_PLL4, SEL_PLL,
172 sel_clk_pll4, ARRAY_SIZE(sel_clk_pll4), CLK_MUX_READ_ONLY),
173
174 DEF_FIXED(".pll4d1", CLK_PLL4D1, CLK_SEL_CLK_PLL4, 1, 1),
175 DEF_FIXED(".pll4d1_div3", CLK_PLL4D1_DIV3, CLK_PLL4D1, 3, 1),
176 DEF_FIXED(".pll4d1_div4", CLK_PLL4D1_DIV4, CLK_PLL4D1, 4, 1),
177 DEF_DIV(".sci0async", CLK_SCI0ASYNC, CLK_PLL4D1, DIVSCI0ASYNC,
178 dtable_24_25_30_32),
179 DEF_DIV(".sci1async", CLK_SCI1ASYNC, CLK_PLL4D1, DIVSCI1ASYNC,
180 dtable_24_25_30_32),
181 DEF_DIV(".sci2async", CLK_SCI2ASYNC, CLK_PLL4D1, DIVSCI2ASYNC,
182 dtable_24_25_30_32),
183 DEF_DIV(".sci3async", CLK_SCI3ASYNC, CLK_PLL4D1, DIVSCI3ASYNC,
184 dtable_24_25_30_32),
185 DEF_DIV(".sci4async", CLK_SCI4ASYNC, CLK_PLL4D1, DIVSCI4ASYNC,
186 dtable_24_25_30_32),
187 DEF_DIV(".sci5async", CLK_SCI5ASYNC, CLK_PLL4D1, DIVSCI5ASYNC,
188 dtable_24_25_30_32),
189
190 DEF_DIV(".spi0async", CLK_SPI0ASYNC, CLK_PLL4D1, DIVSPI0ASYNC,
191 dtable_24_25_30_32),
192 DEF_DIV(".spi1async", CLK_SPI1ASYNC, CLK_PLL4D1, DIVSPI1ASYNC,
193 dtable_24_25_30_32),
194 DEF_DIV(".spi2async", CLK_SPI2ASYNC, CLK_PLL4D1, DIVSPI2ASYNC,
195 dtable_24_25_30_32),
196 DEF_DIV(".spi3async", CLK_SPI3ASYNC, CLK_PLL4D1, DIVSPI3ASYNC,
197 dtable_24_25_30_32),
198
199 DEF_MUX(".divselxspi0", CLK_DIVSELXSPI0_SCKCR, DIVSEL_XSPI0,
200 sel_clk_pll4d1_div3_div4,
201 ARRAY_SIZE(sel_clk_pll4d1_div3_div4), 0),
202 DEF_MUX(".divselxspi1", CLK_DIVSELXSPI1_SCKCR, DIVSEL_XSPI1,
203 sel_clk_pll4d1_div3_div4,
204 ARRAY_SIZE(sel_clk_pll4d1_div3_div4), 0),
205
206 /* Core output clk */
207 DEF_DIV("CA55C0", R9A09G077_CLK_CA55C0, CLK_SEL_CLK_PLL0, DIVCA55C0,
208 dtable_1_2),
209 DEF_DIV("CA55C1", R9A09G077_CLK_CA55C1, CLK_SEL_CLK_PLL0, DIVCA55C1,
210 dtable_1_2),
211 DEF_DIV("CA55C2", R9A09G077_CLK_CA55C2, CLK_SEL_CLK_PLL0, DIVCA55C2,
212 dtable_1_2),
213 DEF_DIV("CA55C3", R9A09G077_CLK_CA55C3, CLK_SEL_CLK_PLL0, DIVCA55C3,
214 dtable_1_2),
215 DEF_DIV("CA55S", R9A09G077_CLK_CA55S, CLK_SEL_CLK_PLL0, DIVCA55S,
216 dtable_1_2),
217 DEF_FIXED("PCLKGPTL", R9A09G077_CLK_PCLKGPTL, CLK_SEL_CLK_PLL1, 2, 1),
218 DEF_FIXED("PCLKH", R9A09G077_CLK_PCLKH, CLK_SEL_CLK_PLL1, 4, 1),
219 DEF_FIXED("PCLKM", R9A09G077_CLK_PCLKM, CLK_SEL_CLK_PLL1, 8, 1),
220 DEF_FIXED("PCLKL", R9A09G077_CLK_PCLKL, CLK_SEL_CLK_PLL1, 16, 1),
221 DEF_FIXED("PCLKAH", R9A09G077_CLK_PCLKAH, CLK_PLL4D1, 6, 1),
222 DEF_FIXED("PCLKAM", R9A09G077_CLK_PCLKAM, CLK_PLL4D1, 12, 1),
223 DEF_FIXED("SDHI_CLKHS", R9A09G077_SDHI_CLKHS, CLK_SEL_CLK_PLL2, 1, 1),
224 DEF_FIXED("USB_CLK", R9A09G077_USB_CLK, CLK_PLL4D1, 48, 1),
225 DEF_FIXED("ETCLKA", R9A09G077_ETCLKA, CLK_SEL_CLK_PLL1, 5, 1),
226 DEF_FIXED("ETCLKB", R9A09G077_ETCLKB, CLK_SEL_CLK_PLL1, 8, 1),
227 DEF_FIXED("ETCLKC", R9A09G077_ETCLKC, CLK_SEL_CLK_PLL1, 10, 1),
228 DEF_FIXED("ETCLKD", R9A09G077_ETCLKD, CLK_SEL_CLK_PLL1, 20, 1),
229 DEF_FIXED("ETCLKE", R9A09G077_ETCLKE, CLK_SEL_CLK_PLL1, 40, 1),
> 230 DEF_DIV_FSELXSPI("XSPI_CLK0", R9A09G077_XSPI_CLK0, CLK_DIVSELXSPI0_SCKCR,
231 FSELXSPI0, dtable_6_8_16_32_64),
232 DEF_DIV_FSELXSPI("XSPI_CLK1", R9A09G077_XSPI_CLK1, CLK_DIVSELXSPI1_SCKCR,
233 FSELXSPI1, dtable_6_8_16_32_64),
234 };
235
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Hi Prabhakar,
kernel test robot noticed the following build errors:
[auto build test ERROR on geert-renesas-drivers/renesas-clk]
[also build test ERROR on next-20251118]
[cannot apply to clk/clk-next linus/master v6.18-rc6]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Prabhakar/clk-renesas-r9a09g077-Add-xSPI-core-and-module-clocks/20251118-045831
base: https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git renesas-clk
patch link: https://lore.kernel.org/r/20251117205627.39376-1-prabhakar.mahadev-lad.rj%40bp.renesas.com
patch subject: [PATCH v3] clk: renesas: r9a09g077: Add xSPI core and module clocks
config: arm-randconfig-001-20251118 (https://download.01.org/0day-ci/archive/20251118/202511181758.cZTukDMh-lkp@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 8.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251118/202511181758.cZTukDMh-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202511181758.cZTukDMh-lkp@intel.com/
All errors (new ones prefixed by >>):
>> drivers/clk/renesas/r9a09g077-cpg.c:88:21: error: 'R9A09G077_XSPI_CLK1' undeclared here (not in a function); did you mean 'R9A09G077_USB_CLK'?
LAST_DT_CORE_CLK = R9A09G077_XSPI_CLK1,
^~~~~~~~~~~~~~~~~~~
R9A09G077_USB_CLK
In file included from drivers/clk/renesas/r9a09g077-cpg.c:19:
>> drivers/clk/renesas/r9a09g077-cpg.c:230:32: error: 'R9A09G077_XSPI_CLK0' undeclared here (not in a function); did you mean 'R9A09G077_USB_CLK'?
DEF_DIV_FSELXSPI("XSPI_CLK0", R9A09G077_XSPI_CLK0, CLK_DIVSELXSPI0_SCKCR,
^~~~~~~~~~~~~~~~~~~
drivers/clk/renesas/renesas-cpg-mssr.h:72:25: note: in definition of macro 'DEF_TYPE'
{ .name = _name, .id = _id, .type = _type }
^~~
drivers/clk/renesas/r9a09g077-cpg.c:230:2: note: in expansion of macro 'DEF_DIV_FSELXSPI'
DEF_DIV_FSELXSPI("XSPI_CLK0", R9A09G077_XSPI_CLK0, CLK_DIVSELXSPI0_SCKCR,
^~~~~~~~~~~~~~~~
vim +88 drivers/clk/renesas/r9a09g077-cpg.c
74
75 #define DEF_DIV(_name, _id, _parent, _conf, _dtable) \
76 DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_DIV, .conf = _conf, \
77 .parent = _parent, .dtable = _dtable, .flag = 0)
78 #define DEF_MUX(_name, _id, _conf, _parent_names, _num_parents, _mux_flags) \
79 DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_MUX, .conf = _conf, \
80 .parent_names = _parent_names, .num_parents = _num_parents, \
81 .flag = 0, .mux_flags = _mux_flags)
82 #define DEF_DIV_FSELXSPI(_name, _id, _parent, _conf, _dtable) \
83 DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_FSELXSPI, .conf = _conf, \
84 .parent = _parent, .dtable = _dtable, .flag = 0)
85
86 enum clk_ids {
87 /* Core Clock Outputs exported to DT */
> 88 LAST_DT_CORE_CLK = R9A09G077_XSPI_CLK1,
89
90 /* External Input Clocks */
91 CLK_EXTAL,
92
93 /* Internal Core Clocks */
94 CLK_LOCO,
95 CLK_PLL0,
96 CLK_PLL1,
97 CLK_PLL2,
98 CLK_PLL4,
99 CLK_SEL_CLK_PLL0,
100 CLK_SEL_CLK_PLL1,
101 CLK_SEL_CLK_PLL2,
102 CLK_SEL_CLK_PLL4,
103 CLK_PLL4D1,
104 CLK_PLL4D1_DIV3,
105 CLK_PLL4D1_DIV4,
106 CLK_SCI0ASYNC,
107 CLK_SCI1ASYNC,
108 CLK_SCI2ASYNC,
109 CLK_SCI3ASYNC,
110 CLK_SCI4ASYNC,
111 CLK_SCI5ASYNC,
112 CLK_SPI0ASYNC,
113 CLK_SPI1ASYNC,
114 CLK_SPI2ASYNC,
115 CLK_SPI3ASYNC,
116 CLK_DIVSELXSPI0_SCKCR,
117 CLK_DIVSELXSPI1_SCKCR,
118
119 /* Module Clocks */
120 MOD_CLK_BASE,
121 };
122
123 static const struct clk_div_table dtable_1_2[] = {
124 {0, 2},
125 {1, 1},
126 {0, 0},
127 };
128
129 static const struct clk_div_table dtable_6_8_16_32_64[] = {
130 {6, 64},
131 {5, 32},
132 {4, 16},
133 {3, 8},
134 {2, 6},
135 {0, 0},
136 };
137
138 static const struct clk_div_table dtable_24_25_30_32[] = {
139 {0, 32},
140 {1, 30},
141 {2, 25},
142 {3, 24},
143 {0, 0},
144 };
145
146 /* Mux clock tables */
147
148 static const char * const sel_clk_pll0[] = { ".loco", ".pll0" };
149 static const char * const sel_clk_pll1[] = { ".loco", ".pll1" };
150 static const char * const sel_clk_pll2[] = { ".loco", ".pll2" };
151 static const char * const sel_clk_pll4[] = { ".loco", ".pll4" };
152 static const char * const sel_clk_pll4d1_div3_div4[] = { ".pll4d1_div3", ".pll4d1_div4" };
153
154 static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = {
155 /* External Clock Inputs */
156 DEF_INPUT("extal", CLK_EXTAL),
157
158 /* Internal Core Clocks */
159 DEF_RATE(".loco", CLK_LOCO, 1000 * 1000),
160 DEF_FIXED(".pll0", CLK_PLL0, CLK_EXTAL, 1, 48),
161 DEF_FIXED(".pll1", CLK_PLL1, CLK_EXTAL, 1, 40),
162 DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 1, 32),
163 DEF_FIXED(".pll4", CLK_PLL4, CLK_EXTAL, 1, 96),
164
165 DEF_MUX(".sel_clk_pll0", CLK_SEL_CLK_PLL0, SEL_PLL,
166 sel_clk_pll0, ARRAY_SIZE(sel_clk_pll0), CLK_MUX_READ_ONLY),
167 DEF_MUX(".sel_clk_pll1", CLK_SEL_CLK_PLL1, SEL_PLL,
168 sel_clk_pll1, ARRAY_SIZE(sel_clk_pll1), CLK_MUX_READ_ONLY),
169 DEF_MUX(".sel_clk_pll2", CLK_SEL_CLK_PLL2, SEL_PLL,
170 sel_clk_pll2, ARRAY_SIZE(sel_clk_pll2), CLK_MUX_READ_ONLY),
171 DEF_MUX(".sel_clk_pll4", CLK_SEL_CLK_PLL4, SEL_PLL,
172 sel_clk_pll4, ARRAY_SIZE(sel_clk_pll4), CLK_MUX_READ_ONLY),
173
174 DEF_FIXED(".pll4d1", CLK_PLL4D1, CLK_SEL_CLK_PLL4, 1, 1),
175 DEF_FIXED(".pll4d1_div3", CLK_PLL4D1_DIV3, CLK_PLL4D1, 3, 1),
176 DEF_FIXED(".pll4d1_div4", CLK_PLL4D1_DIV4, CLK_PLL4D1, 4, 1),
177 DEF_DIV(".sci0async", CLK_SCI0ASYNC, CLK_PLL4D1, DIVSCI0ASYNC,
178 dtable_24_25_30_32),
179 DEF_DIV(".sci1async", CLK_SCI1ASYNC, CLK_PLL4D1, DIVSCI1ASYNC,
180 dtable_24_25_30_32),
181 DEF_DIV(".sci2async", CLK_SCI2ASYNC, CLK_PLL4D1, DIVSCI2ASYNC,
182 dtable_24_25_30_32),
183 DEF_DIV(".sci3async", CLK_SCI3ASYNC, CLK_PLL4D1, DIVSCI3ASYNC,
184 dtable_24_25_30_32),
185 DEF_DIV(".sci4async", CLK_SCI4ASYNC, CLK_PLL4D1, DIVSCI4ASYNC,
186 dtable_24_25_30_32),
187 DEF_DIV(".sci5async", CLK_SCI5ASYNC, CLK_PLL4D1, DIVSCI5ASYNC,
188 dtable_24_25_30_32),
189
190 DEF_DIV(".spi0async", CLK_SPI0ASYNC, CLK_PLL4D1, DIVSPI0ASYNC,
191 dtable_24_25_30_32),
192 DEF_DIV(".spi1async", CLK_SPI1ASYNC, CLK_PLL4D1, DIVSPI1ASYNC,
193 dtable_24_25_30_32),
194 DEF_DIV(".spi2async", CLK_SPI2ASYNC, CLK_PLL4D1, DIVSPI2ASYNC,
195 dtable_24_25_30_32),
196 DEF_DIV(".spi3async", CLK_SPI3ASYNC, CLK_PLL4D1, DIVSPI3ASYNC,
197 dtable_24_25_30_32),
198
199 DEF_MUX(".divselxspi0", CLK_DIVSELXSPI0_SCKCR, DIVSEL_XSPI0,
200 sel_clk_pll4d1_div3_div4,
201 ARRAY_SIZE(sel_clk_pll4d1_div3_div4), 0),
202 DEF_MUX(".divselxspi1", CLK_DIVSELXSPI1_SCKCR, DIVSEL_XSPI1,
203 sel_clk_pll4d1_div3_div4,
204 ARRAY_SIZE(sel_clk_pll4d1_div3_div4), 0),
205
206 /* Core output clk */
207 DEF_DIV("CA55C0", R9A09G077_CLK_CA55C0, CLK_SEL_CLK_PLL0, DIVCA55C0,
208 dtable_1_2),
209 DEF_DIV("CA55C1", R9A09G077_CLK_CA55C1, CLK_SEL_CLK_PLL0, DIVCA55C1,
210 dtable_1_2),
211 DEF_DIV("CA55C2", R9A09G077_CLK_CA55C2, CLK_SEL_CLK_PLL0, DIVCA55C2,
212 dtable_1_2),
213 DEF_DIV("CA55C3", R9A09G077_CLK_CA55C3, CLK_SEL_CLK_PLL0, DIVCA55C3,
214 dtable_1_2),
215 DEF_DIV("CA55S", R9A09G077_CLK_CA55S, CLK_SEL_CLK_PLL0, DIVCA55S,
216 dtable_1_2),
217 DEF_FIXED("PCLKGPTL", R9A09G077_CLK_PCLKGPTL, CLK_SEL_CLK_PLL1, 2, 1),
218 DEF_FIXED("PCLKH", R9A09G077_CLK_PCLKH, CLK_SEL_CLK_PLL1, 4, 1),
219 DEF_FIXED("PCLKM", R9A09G077_CLK_PCLKM, CLK_SEL_CLK_PLL1, 8, 1),
220 DEF_FIXED("PCLKL", R9A09G077_CLK_PCLKL, CLK_SEL_CLK_PLL1, 16, 1),
221 DEF_FIXED("PCLKAH", R9A09G077_CLK_PCLKAH, CLK_PLL4D1, 6, 1),
222 DEF_FIXED("PCLKAM", R9A09G077_CLK_PCLKAM, CLK_PLL4D1, 12, 1),
223 DEF_FIXED("SDHI_CLKHS", R9A09G077_SDHI_CLKHS, CLK_SEL_CLK_PLL2, 1, 1),
224 DEF_FIXED("USB_CLK", R9A09G077_USB_CLK, CLK_PLL4D1, 48, 1),
225 DEF_FIXED("ETCLKA", R9A09G077_ETCLKA, CLK_SEL_CLK_PLL1, 5, 1),
226 DEF_FIXED("ETCLKB", R9A09G077_ETCLKB, CLK_SEL_CLK_PLL1, 8, 1),
227 DEF_FIXED("ETCLKC", R9A09G077_ETCLKC, CLK_SEL_CLK_PLL1, 10, 1),
228 DEF_FIXED("ETCLKD", R9A09G077_ETCLKD, CLK_SEL_CLK_PLL1, 20, 1),
229 DEF_FIXED("ETCLKE", R9A09G077_ETCLKE, CLK_SEL_CLK_PLL1, 40, 1),
> 230 DEF_DIV_FSELXSPI("XSPI_CLK0", R9A09G077_XSPI_CLK0, CLK_DIVSELXSPI0_SCKCR,
231 FSELXSPI0, dtable_6_8_16_32_64),
232 DEF_DIV_FSELXSPI("XSPI_CLK1", R9A09G077_XSPI_CLK1, CLK_DIVSELXSPI1_SCKCR,
233 FSELXSPI1, dtable_6_8_16_32_64),
234 };
235
--
0-DAY CI Kernel Test Service
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